#ifndef DT_BINDINGS_MEMORY_TEGRA186_MC_H #define DT_BINDINGS_MEMORY_TEGRA186_MC_H /* special clients */ #define TEGRA186_SID_INVALID … #define TEGRA186_SID_PASSTHROUGH … /* host1x clients */ #define TEGRA186_SID_HOST1X … #define TEGRA186_SID_CSI … #define TEGRA186_SID_VIC … #define TEGRA186_SID_VI … #define TEGRA186_SID_ISP … #define TEGRA186_SID_NVDEC … #define TEGRA186_SID_NVENC … #define TEGRA186_SID_NVJPG … #define TEGRA186_SID_NVDISPLAY … #define TEGRA186_SID_TSEC … #define TEGRA186_SID_TSECB … #define TEGRA186_SID_SE … #define TEGRA186_SID_SE1 … #define TEGRA186_SID_SE2 … #define TEGRA186_SID_SE3 … /* GPU clients */ #define TEGRA186_SID_GPU … /* other SoC clients */ #define TEGRA186_SID_AFI … #define TEGRA186_SID_HDA … #define TEGRA186_SID_ETR … #define TEGRA186_SID_EQOS … #define TEGRA186_SID_UFSHC … #define TEGRA186_SID_AON … #define TEGRA186_SID_SDMMC4 … #define TEGRA186_SID_SDMMC3 … #define TEGRA186_SID_SDMMC2 … #define TEGRA186_SID_SDMMC1 … #define TEGRA186_SID_XUSB_HOST … #define TEGRA186_SID_XUSB_DEV … #define TEGRA186_SID_SATA … #define TEGRA186_SID_APE … #define TEGRA186_SID_SCE … /* GPC DMA clients */ #define TEGRA186_SID_GPCDMA_0 … #define TEGRA186_SID_GPCDMA_1 … #define TEGRA186_SID_GPCDMA_2 … #define TEGRA186_SID_GPCDMA_3 … #define TEGRA186_SID_GPCDMA_4 … #define TEGRA186_SID_GPCDMA_5 … #define TEGRA186_SID_GPCDMA_6 … #define TEGRA186_SID_GPCDMA_7 … /* APE DMA clients */ #define TEGRA186_SID_APE_1 … #define TEGRA186_SID_APE_2 … /* camera RTCPU */ #define TEGRA186_SID_RCE … /* camera RTCPU on host1x address space */ #define TEGRA186_SID_RCE_1X … /* APE DMA clients */ #define TEGRA186_SID_APE_3 … /* camera RTCPU running on APE */ #define TEGRA186_SID_APE_CAM … #define TEGRA186_SID_APE_CAM_1X … /* * The BPMP has its SID value hardcoded in the firmware. Changing it requires * considerable effort. */ #define TEGRA186_SID_BPMP … /* for SMMU tests */ #define TEGRA186_SID_SMMU_TEST … /* host1x virtualization channels */ #define TEGRA186_SID_HOST1X_CTX0 … #define TEGRA186_SID_HOST1X_CTX1 … #define TEGRA186_SID_HOST1X_CTX2 … #define TEGRA186_SID_HOST1X_CTX3 … #define TEGRA186_SID_HOST1X_CTX4 … #define TEGRA186_SID_HOST1X_CTX5 … #define TEGRA186_SID_HOST1X_CTX6 … #define TEGRA186_SID_HOST1X_CTX7 … /* host1x command buffers */ #define TEGRA186_SID_HOST1X_VM0 … #define TEGRA186_SID_HOST1X_VM1 … #define TEGRA186_SID_HOST1X_VM2 … #define TEGRA186_SID_HOST1X_VM3 … #define TEGRA186_SID_HOST1X_VM4 … #define TEGRA186_SID_HOST1X_VM5 … #define TEGRA186_SID_HOST1X_VM6 … #define TEGRA186_SID_HOST1X_VM7 … /* SE data buffers */ #define TEGRA186_SID_SE_VM0 … #define TEGRA186_SID_SE_VM1 … #define TEGRA186_SID_SE_VM2 … #define TEGRA186_SID_SE_VM3 … #define TEGRA186_SID_SE_VM4 … #define TEGRA186_SID_SE_VM5 … #define TEGRA186_SID_SE_VM6 … #define TEGRA186_SID_SE_VM7 … /* * memory client IDs */ /* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ #define TEGRA186_MEMORY_CLIENT_PTCR … /* PCIE reads */ #define TEGRA186_MEMORY_CLIENT_AFIR … /* High-definition audio (HDA) reads */ #define TEGRA186_MEMORY_CLIENT_HDAR … /* Host channel data reads */ #define TEGRA186_MEMORY_CLIENT_HOST1XDMAR … #define TEGRA186_MEMORY_CLIENT_NVENCSRD … /* SATA reads */ #define TEGRA186_MEMORY_CLIENT_SATAR … /* Reads from Cortex-A9 4 CPU cores via the L2 cache */ #define TEGRA186_MEMORY_CLIENT_MPCORER … #define TEGRA186_MEMORY_CLIENT_NVENCSWR … /* PCIE writes */ #define TEGRA186_MEMORY_CLIENT_AFIW … /* High-definition audio (HDA) writes */ #define TEGRA186_MEMORY_CLIENT_HDAW … /* Writes from Cortex-A9 4 CPU cores via the L2 cache */ #define TEGRA186_MEMORY_CLIENT_MPCOREW … /* SATA writes */ #define TEGRA186_MEMORY_CLIENT_SATAW … /* ISP Read client for Crossbar A */ #define TEGRA186_MEMORY_CLIENT_ISPRA … /* ISP Write client for Crossbar A */ #define TEGRA186_MEMORY_CLIENT_ISPWA … /* ISP Write client Crossbar B */ #define TEGRA186_MEMORY_CLIENT_ISPWB … /* XUSB reads */ #define TEGRA186_MEMORY_CLIENT_XUSB_HOSTR … /* XUSB_HOST writes */ #define TEGRA186_MEMORY_CLIENT_XUSB_HOSTW … /* XUSB reads */ #define TEGRA186_MEMORY_CLIENT_XUSB_DEVR … /* XUSB_DEV writes */ #define TEGRA186_MEMORY_CLIENT_XUSB_DEVW … /* TSEC Memory Return Data Client Description */ #define TEGRA186_MEMORY_CLIENT_TSECSRD … /* TSEC Memory Write Client Description */ #define TEGRA186_MEMORY_CLIENT_TSECSWR … /* 3D, ltcx reads instance 0 */ #define TEGRA186_MEMORY_CLIENT_GPUSRD … /* 3D, ltcx writes instance 0 */ #define TEGRA186_MEMORY_CLIENT_GPUSWR … /* sdmmca memory read client */ #define TEGRA186_MEMORY_CLIENT_SDMMCRA … /* sdmmcbmemory read client */ #define TEGRA186_MEMORY_CLIENT_SDMMCRAA … /* sdmmc memory read client */ #define TEGRA186_MEMORY_CLIENT_SDMMCR … /* sdmmcd memory read client */ #define TEGRA186_MEMORY_CLIENT_SDMMCRAB … /* sdmmca memory write client */ #define TEGRA186_MEMORY_CLIENT_SDMMCWA … /* sdmmcb memory write client */ #define TEGRA186_MEMORY_CLIENT_SDMMCWAA … /* sdmmc memory write client */ #define TEGRA186_MEMORY_CLIENT_SDMMCW … /* sdmmcd memory write client */ #define TEGRA186_MEMORY_CLIENT_SDMMCWAB … #define TEGRA186_MEMORY_CLIENT_VICSRD … #define TEGRA186_MEMORY_CLIENT_VICSWR … /* VI Write client */ #define TEGRA186_MEMORY_CLIENT_VIW … #define TEGRA186_MEMORY_CLIENT_NVDECSRD … #define TEGRA186_MEMORY_CLIENT_NVDECSWR … /* Audio Processing (APE) engine reads */ #define TEGRA186_MEMORY_CLIENT_APER … /* Audio Processing (APE) engine writes */ #define TEGRA186_MEMORY_CLIENT_APEW … #define TEGRA186_MEMORY_CLIENT_NVJPGSRD … #define TEGRA186_MEMORY_CLIENT_NVJPGSWR … /* SE Memory Return Data Client Description */ #define TEGRA186_MEMORY_CLIENT_SESRD … /* SE Memory Write Client Description */ #define TEGRA186_MEMORY_CLIENT_SESWR … /* ETR reads */ #define TEGRA186_MEMORY_CLIENT_ETRR … /* ETR writes */ #define TEGRA186_MEMORY_CLIENT_ETRW … /* TSECB Memory Return Data Client Description */ #define TEGRA186_MEMORY_CLIENT_TSECSRDB … /* TSECB Memory Write Client Description */ #define TEGRA186_MEMORY_CLIENT_TSECSWRB … /* 3D, ltcx reads instance 1 */ #define TEGRA186_MEMORY_CLIENT_GPUSRD2 … /* 3D, ltcx writes instance 1 */ #define TEGRA186_MEMORY_CLIENT_GPUSWR2 … /* AXI Switch read client */ #define TEGRA186_MEMORY_CLIENT_AXISR … /* AXI Switch write client */ #define TEGRA186_MEMORY_CLIENT_AXISW … /* EQOS read client */ #define TEGRA186_MEMORY_CLIENT_EQOSR … /* EQOS write client */ #define TEGRA186_MEMORY_CLIENT_EQOSW … /* UFSHC read client */ #define TEGRA186_MEMORY_CLIENT_UFSHCR … /* UFSHC write client */ #define TEGRA186_MEMORY_CLIENT_UFSHCW … /* NVDISPLAY read client */ #define TEGRA186_MEMORY_CLIENT_NVDISPLAYR … /* BPMP read client */ #define TEGRA186_MEMORY_CLIENT_BPMPR … /* BPMP write client */ #define TEGRA186_MEMORY_CLIENT_BPMPW … /* BPMPDMA read client */ #define TEGRA186_MEMORY_CLIENT_BPMPDMAR … /* BPMPDMA write client */ #define TEGRA186_MEMORY_CLIENT_BPMPDMAW … /* AON read client */ #define TEGRA186_MEMORY_CLIENT_AONR … /* AON write client */ #define TEGRA186_MEMORY_CLIENT_AONW … /* AONDMA read client */ #define TEGRA186_MEMORY_CLIENT_AONDMAR … /* AONDMA write client */ #define TEGRA186_MEMORY_CLIENT_AONDMAW … /* SCE read client */ #define TEGRA186_MEMORY_CLIENT_SCER … /* SCE write client */ #define TEGRA186_MEMORY_CLIENT_SCEW … /* SCEDMA read client */ #define TEGRA186_MEMORY_CLIENT_SCEDMAR … /* SCEDMA write client */ #define TEGRA186_MEMORY_CLIENT_SCEDMAW … /* APEDMA read client */ #define TEGRA186_MEMORY_CLIENT_APEDMAR … /* APEDMA write client */ #define TEGRA186_MEMORY_CLIENT_APEDMAW … /* NVDISPLAY read client instance 2 */ #define TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 … #define TEGRA186_MEMORY_CLIENT_VICSRD1 … #define TEGRA186_MEMORY_CLIENT_NVDECSRD1 … #endif
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