// SPDX-License-Identifier: GPL-2.0-only /* * Broadcom STB SoCs Bus Unit Interface controls * * Copyright (C) 2015, Broadcom Corporation */ #define pr_fmt(fmt) … #include <linux/kernel.h> #include <linux/io.h> #include <linux/of_address.h> #include <linux/syscore_ops.h> #include <linux/soc/brcmstb/brcmstb.h> #define RACENPREF_MASK … #define RACPREFINST_SHIFT … #define RACENINST_SHIFT … #define RACPREFDATA_SHIFT … #define RACENDATA_SHIFT … #define RAC_CPU_SHIFT … #define RACCFG_MASK … #define DPREF_LINE_2_SHIFT … #define DPREF_LINE_2_MASK … /* Bitmask to enable instruction and data prefetching with a 256-bytes stride */ #define RAC_DATA_INST_EN_MASK … #define CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK … #define CPU_CREDIT_REG_MCPx_READ_CRED_MASK … #define CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK … #define CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(x) … #define CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(x) … #define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(x) … #define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK … #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK … #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK … #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT … #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE … static void __iomem *cpubiuctrl_base; static bool mcp_wr_pairing_en; static const int *cpubiuctrl_regs; enum cpubiuctrl_regs { … }; static inline u32 cbc_readl(int reg) { … } static inline void cbc_writel(u32 val, int reg) { … } static const int b15_cpubiuctrl_regs[] = …; /* Odd cases, e.g: 7260A0 */ static const int b53_cpubiuctrl_no_wb_regs[] = …; static const int b53_cpubiuctrl_regs[] = …; static const int a72_cpubiuctrl_regs[] = …; static int __init mcp_write_pairing_set(void) { … } static const u32 a72_b53_mach_compat[] = …; /* The read-ahead cache present in the Brahma-B53 CPU is a special piece of * hardware after the integrated L2 cache of the B53 CPU complex whose purpose * is to prefetch instruction and/or data with a line size of either 64 bytes * or 256 bytes. The rationale is that the data-bus of the CPU interface is * optimized for 256-byte transactions, and enabling the read-ahead cache * provides a significant performance boost (typically twice the performance * for a memcpy benchmark application). * * The read-ahead cache is transparent for Virtual Address cache maintenance * operations: IC IVAU, DC IVAC, DC CVAC, DC CVAU and DC CIVAC. So no special * handling is needed for the DMA API above and beyond what is included in the * arm64 implementation. * * In addition, since the Point of Unification is typically between L1 and L2 * for the Brahma-B53 processor no special read-ahead cache handling is needed * for the IC IALLU and IC IALLUIS cache maintenance operations. * * However, it is not possible to specify the cache level (L3) for the cache * maintenance instructions operating by set/way to operate on the read-ahead * cache. The read-ahead cache will maintain coherency when inner cache lines * are cleaned by set/way, but if it is necessary to invalidate inner cache * lines by set/way to maintain coherency with system masters operating on * shared memory that does not have hardware support for coherency, then it * will also be necessary to explicitly invalidate the read-ahead cache. */ static void __init a72_b53_rac_enable_all(struct device_node *np) { … } static void __init mcp_a72_b53_set(void) { … } static int __init setup_hifcpubiuctrl_regs(struct device_node *np) { … } #ifdef CONFIG_PM_SLEEP static u32 cpubiuctrl_reg_save[NUM_CPU_BIUCTRL_REGS]; static int brcmstb_cpu_credit_reg_suspend(void) { … } static void brcmstb_cpu_credit_reg_resume(void) { … } static struct syscore_ops brcmstb_cpu_credit_syscore_ops = …; #endif static int __init brcmstb_biuctrl_init(void) { … } early_initcall(brcmstb_biuctrl_init);
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