linux/include/linux/litex.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Common LiteX header providing
 * helper functions for accessing CSRs.
 *
 * Copyright (C) 2019-2020 Antmicro <www.antmicro.com>
 */

#ifndef _LINUX_LITEX_H
#define _LINUX_LITEX_H

#include <linux/io.h>

static inline void _write_litex_subregister(u32 val, void __iomem *addr)
{ … }

static inline u32 _read_litex_subregister(void __iomem *addr)
{ … }

/*
 * LiteX SoC Generator, depending on the configuration, can split a single
 * logical CSR (Control&Status Register) into a series of consecutive physical
 * registers.
 *
 * For example, in the configuration with 8-bit CSR Bus, a 32-bit aligned,
 * 32-bit wide logical CSR will be laid out as four 32-bit physical
 * subregisters, each one containing one byte of meaningful data.
 *
 * For Linux support, upstream LiteX enforces a 32-bit wide CSR bus, which
 * means that only larger-than-32-bit CSRs will be split across multiple
 * subregisters (e.g., a 64-bit CSR will be spread across two consecutive
 * 32-bit subregisters).
 *
 * For details see: https://github.com/enjoy-digital/litex/wiki/CSR-Bus
 */

static inline void litex_write8(void __iomem *reg, u8 val)
{ … }

static inline void litex_write16(void __iomem *reg, u16 val)
{ … }

static inline void litex_write32(void __iomem *reg, u32 val)
{ … }

static inline void litex_write64(void __iomem *reg, u64 val)
{ … }

static inline u8 litex_read8(void __iomem *reg)
{ … }

static inline u16 litex_read16(void __iomem *reg)
{ … }

static inline u32 litex_read32(void __iomem *reg)
{ … }

static inline u64 litex_read64(void __iomem *reg)
{ … }

#endif /* _LINUX_LITEX_H */