/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2018 MediaTek Inc. * */ #ifndef __MTK_CMDQ_MAILBOX_H__ #define __MTK_CMDQ_MAILBOX_H__ #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/types.h> #define CMDQ_INST_SIZE … #define CMDQ_SUBSYS_SHIFT … #define CMDQ_OP_CODE_SHIFT … #define CMDQ_JUMP_PASS … #define CMDQ_WFE_UPDATE … #define CMDQ_WFE_UPDATE_VALUE … #define CMDQ_WFE_WAIT … #define CMDQ_WFE_WAIT_VALUE … /* * WFE arg_b * bit 0-11: wait value * bit 15: 1 - wait, 0 - no wait * bit 16-27: update value * bit 31: 1 - update, 0 - no update */ #define CMDQ_WFE_OPTION … /** cmdq event maximum */ #define CMDQ_MAX_EVENT … /* * CMDQ_CODE_MASK: * set write mask * format: op mask * CMDQ_CODE_WRITE: * write value into target register * format: op subsys address value * CMDQ_CODE_JUMP: * jump by offset * format: op offset * CMDQ_CODE_WFE: * wait for event and clear * it is just clear if no wait * format: [wait] op event update:1 to_wait:1 wait:1 * [clear] op event update:1 to_wait:0 wait:0 * CMDQ_CODE_EOC: * end of command * format: op irq_flag */ enum cmdq_code { … }; struct cmdq_cb_data { … }; struct cmdq_pkt { … }; u8 cmdq_get_shift_pa(struct mbox_chan *chan); #endif /* __MTK_CMDQ_MAILBOX_H__ */
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