/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __SOC_MEDIATEK_MTK_MMSYS_H #define __SOC_MEDIATEK_MTK_MMSYS_H #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN … #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN … #define DISP_REG_CONFIG_DISP_OD_MOUT_EN … #define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN … #define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN … #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN … #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN … #define DISP_REG_CONFIG_DSIE_SEL_IN … #define DISP_REG_CONFIG_DSIO_SEL_IN … #define DISP_REG_CONFIG_DPI_SEL_IN … #define DISP_REG_CONFIG_DISP_RDMA2_SOUT … #define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN … #define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN … #define DISP_REG_CONFIG_MMSYS_CG_CON0 … #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN … #define DISP_REG_CONFIG_OUT_SEL … #define DISP_REG_CONFIG_DSI_SEL … #define DISP_REG_CONFIG_DPI_SEL … #define OVL0_MOUT_EN_COLOR0 … #define OD_MOUT_EN_RDMA0 … #define OD1_MOUT_EN_RDMA1 … #define UFOE_MOUT_EN_DSI0 … #define COLOR0_SEL_IN_OVL0 … #define OVL1_MOUT_EN_COLOR1 … #define GAMMA_MOUT_EN_RDMA1 … #define RDMA0_SOUT_DPI0 … #define RDMA0_SOUT_DPI1 … #define RDMA0_SOUT_DSI1 … #define RDMA0_SOUT_DSI2 … #define RDMA0_SOUT_DSI3 … #define RDMA0_SOUT_MASK … #define RDMA1_SOUT_DPI0 … #define RDMA1_SOUT_DPI1 … #define RDMA1_SOUT_DSI1 … #define RDMA1_SOUT_DSI2 … #define RDMA1_SOUT_DSI3 … #define RDMA1_SOUT_MASK … #define RDMA2_SOUT_DPI0 … #define RDMA2_SOUT_DPI1 … #define RDMA2_SOUT_DSI1 … #define RDMA2_SOUT_DSI2 … #define RDMA2_SOUT_DSI3 … #define RDMA2_SOUT_MASK … #define DPI0_SEL_IN_RDMA1 … #define DPI0_SEL_IN_RDMA2 … #define DPI0_SEL_IN_MASK … #define DPI1_SEL_IN_RDMA1 … #define DPI1_SEL_IN_RDMA2 … #define DPI1_SEL_IN_MASK … #define DSI0_SEL_IN_RDMA1 … #define DSI0_SEL_IN_RDMA2 … #define DSI0_SEL_IN_MASK … #define DSI1_SEL_IN_RDMA1 … #define DSI1_SEL_IN_RDMA2 … #define DSI1_SEL_IN_MASK … #define DSI2_SEL_IN_RDMA1 … #define DSI2_SEL_IN_RDMA2 … #define DSI2_SEL_IN_MASK … #define DSI3_SEL_IN_RDMA1 … #define DSI3_SEL_IN_RDMA2 … #define DSI3_SEL_IN_MASK … #define COLOR1_SEL_IN_OVL1 … #define OVL_MOUT_EN_RDMA … #define BLS_TO_DSI_RDMA1_TO_DPI1 … #define BLS_TO_DPI_RDMA1_TO_DSI … #define BLS_RDMA1_DSI_DPI_MASK … #define DSI_SEL_IN_BLS … #define DPI_SEL_IN_BLS … #define DPI_SEL_IN_MASK … #define DSI_SEL_IN_RDMA … #define DSI_SEL_IN_MASK … #define MMSYS_RST_NR(bank, bit) … struct mtk_mmsys_routes { … }; /** * struct mtk_mmsys_driver_data - Settings of the mmsys * @clk_driver: Clock driver name that the mmsys is using * (defined in drivers/clk/mediatek/clk-*.c). * @routes: Routing table of the mmsys. * It provides mux settings from one module to another. * @num_routes: Array size of the routes. * @sw0_rst_offset: Register offset for the reset control. * @num_resets: Number of reset bits that are defined * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe) * or VDOSYS (Video). Only VDOSYS needs to be added to drm driver. * @vsync_len: VSYNC length of the MIXER. * VSYNC is usually triggered by the connector, so its length is a * fixed value when the frame rate is decided, but ETHDR and * MIXER generate their own VSYNC due to hardware design, therefore * MIXER has to sync with ETHDR by adjusting VSYNC length. * On MT8195, there is no such setting so we use the gap between * falling edge and rising edge of SOF (Start of Frame) signal to * do the job, but since MT8188, VSYNC_LEN setting is introduced to * solve the problem and is given 0x40 (ticks) as the default value. * Please notice that this value has to be set to 1 (minimum) if * ETHDR is bypassed, otherwise MIXER could wait too long and causing * underflow. * * Each MMSYS (multi-media system) may have different settings, they may use * different clock sources, mux settings, reset control ...etc., and these * differences are all stored here. */ struct mtk_mmsys_driver_data { … }; /* * Routes in mt2701 and mt2712 are different. That means * in the same register address, it controls different input/output * selection for each SoC. But, right now, they use the same table as * default routes meet their requirements. But we don't have the complete * route information for these three SoC, so just keep them in the same * table. After we've more information, we could separate mt2701, mt2712 * to an independent table. */ static const struct mtk_mmsys_routes mmsys_default_routing_table[] = …; #endif /* __SOC_MEDIATEK_MTK_MMSYS_H */
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