#ifndef __SOC_MEDIATEK_MT8188_MMSYS_H
#define __SOC_MEDIATEK_MT8188_MMSYS_H
#include <linux/soc/mediatek/mtk-mmsys.h>
#include <dt-bindings/reset/mt8188-resets.h>
#define MT8188_VDO0_SW0_RST_B …
#define MT8188_VDO0_OVL_MOUT_EN …
#define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 …
#define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 …
#define MT8188_MOUT_DISP_OVL0_TO_DISP_OVL1 …
#define MT8188_MOUT_DISP_OVL1_TO_DISP_RDMA1 …
#define MT8188_MOUT_DISP_OVL1_TO_DISP_WDMA1 …
#define MT8188_MOUT_DISP_OVL1_TO_DISP_OVL0 …
#define MT8188_VDO0_SEL_IN …
#define MT8188_VDO0_SEL_OUT …
#define MT8188_VDO0_DISP_RDMA_SEL …
#define MT8188_SOUT_DISP_RDMA0_TO_MASK …
#define MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0 …
#define MT8188_SOUT_DISP_RDMA0_TO_DISP_DSI0 …
#define MT8188_SOUT_DISP_RDMA0_TO_DISP_DP_INTF0 …
#define MT8188_SEL_IN_DISP_RDMA0_FROM_MASK …
#define MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0 …
#define MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_RSZ0 …
#define MT8188_VDO0_DSI0_SEL_IN …
#define MT8188_SEL_IN_DSI0_FROM_MASK …
#define MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT …
#define MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0 …
#define MT8188_VDO0_DP_INTF0_SEL_IN …
#define MT8188_SEL_IN_DP_INTF0_FROM_MASK …
#define MT8188_SEL_IN_DP_INTF0_FROM_DSC_WRAP0C1_OUT …
#define MT8188_SEL_IN_DP_INTF0_FROM_VPP_MERGE …
#define MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0 …
#define MT8188_VDO0_DISP_DITHER0_SEL_OUT …
#define MT8188_SOUT_DISP_DITHER0_TO_MASK …
#define MT8188_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN …
#define MT8188_SOUT_DISP_DITHER0_TO_DSI0 …
#define MT8188_SOUT_DISP_DITHER0_TO_VPP_MERGE0 …
#define MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0 …
#define MT8188_VDO0_VPP_MERGE_SEL …
#define MT8188_SEL_IN_VPP_MERGE_FROM_MASK …
#define MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT …
#define MT8188_SEL_IN_VPP_MERGE_FROM_DITHER0_OUT …
#define MT8188_SOUT_VPP_MERGE_TO_MASK …
#define MT8188_SOUT_VPP_MERGE_TO_DSI1 …
#define MT8188_SOUT_VPP_MERGE_TO_DP_INTF0 …
#define MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 …
#define MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA1 …
#define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN …
#define MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0 …
#define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK …
#define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN …
#define MT8188_VDO0_DSC_WARP_SEL …
#define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK …
#define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0 …
#define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_VPP_MERGE …
#define MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK …
#define MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0 …
#define MT8188_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 …
#define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE …
#define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 …
#define MT8188_VDO1_SW0_RST_B …
#define MT8188_VDO1_HDR_TOP_CFG …
#define MT8188_VDO1_MIXER_IN1_ALPHA …
#define MT8188_VDO1_MIXER_IN1_PAD …
#define MT8188_VDO1_MIXER_VSYNC_LEN …
#define MT8188_VDO1_MERGE0_ASYNC_CFG_WD …
#define MT8188_VDO1_HDRBE_ASYNC_CFG_WD …
#define MT8188_VDO1_VPP_MERGE0_P0_SEL_IN …
#define MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 …
#define MT8188_VDO1_VPP_MERGE0_P1_SEL_IN …
#define MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 …
#define MT8188_VDO1_DISP_DPI1_SEL_IN …
#define MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT …
#define MT8188_VDO1_DISP_DP_INTF0_SEL_IN …
#define MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT …
#define MT8188_VDO1_MERGE4_SOUT_SEL …
#define MT8188_MERGE4_SOUT_TO_DPI1_SEL …
#define MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL …
#define MT8188_VDO1_MIXER_IN1_SEL_IN …
#define MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT …
#define MT8188_VDO1_MIXER_IN2_SEL_IN …
#define MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT …
#define MT8188_VDO1_MIXER_IN3_SEL_IN …
#define MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT …
#define MT8188_VDO1_MIXER_IN4_SEL_IN …
#define MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT …
#define MT8188_VDO1_MIXER_OUT_SOUT_SEL …
#define MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL …
#define MT8188_VDO1_VPP_MERGE1_P0_SEL_IN …
#define MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 …
#define MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL …
#define MT8188_SOUT_TO_MIXER_IN1_SEL …
#define MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL …
#define MT8188_SOUT_TO_MIXER_IN2_SEL …
#define MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL …
#define MT8188_SOUT_TO_MIXER_IN3_SEL …
#define MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL …
#define MT8188_SOUT_TO_MIXER_IN4_SEL …
#define MT8188_VDO1_MERGE4_ASYNC_SEL_IN …
#define MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT …
#define MT8188_VDO1_MIXER_IN1_SOUT_SEL …
#define MT8188_MIXER_IN1_SOUT_TO_DISP_MIXER …
#define MT8188_VDO1_MIXER_IN2_SOUT_SEL …
#define MT8188_MIXER_IN2_SOUT_TO_DISP_MIXER …
#define MT8188_VDO1_MIXER_IN3_SOUT_SEL …
#define MT8188_MIXER_IN3_SOUT_TO_DISP_MIXER …
#define MT8188_VDO1_MIXER_IN4_SOUT_SEL …
#define MT8188_MIXER_IN4_SOUT_TO_DISP_MIXER …
#define MT8188_VDO1_MIXER_SOUT_SEL_IN …
#define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER …
static const u8 mmsys_mt8188_vdo0_rst_tb[] = …;
static const u8 mmsys_mt8188_vdo1_rst_tb[] = …;
static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = …;
static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] = …;
#endif