#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/firmware/qcom/qcom_scm.h>
#include <soc/qcom/ice.h>
#define AES_256_XTS_KEY_SIZE …
#define QCOM_ICE_REG_VERSION …
#define QCOM_ICE_REG_FUSE_SETTING …
#define QCOM_ICE_REG_BIST_STATUS …
#define QCOM_ICE_REG_ADVANCED_CONTROL …
#define QCOM_ICE_BIST_STATUS_MASK …
#define QCOM_ICE_FUSE_SETTING_MASK …
#define QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK …
#define QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK …
#define qcom_ice_writel(engine, val, reg) …
#define qcom_ice_readl(engine, reg) …
struct qcom_ice { … };
static bool qcom_ice_check_supported(struct qcom_ice *ice)
{ … }
static void qcom_ice_low_power_mode_enable(struct qcom_ice *ice)
{ … }
static void qcom_ice_optimization_enable(struct qcom_ice *ice)
{ … }
static int qcom_ice_wait_bist_status(struct qcom_ice *ice)
{ … }
int qcom_ice_enable(struct qcom_ice *ice)
{ … }
EXPORT_SYMBOL_GPL(…);
int qcom_ice_resume(struct qcom_ice *ice)
{ … }
EXPORT_SYMBOL_GPL(…);
int qcom_ice_suspend(struct qcom_ice *ice)
{ … }
EXPORT_SYMBOL_GPL(…);
int qcom_ice_program_key(struct qcom_ice *ice,
u8 algorithm_id, u8 key_size,
const u8 crypto_key[], u8 data_unit_size,
int slot)
{ … }
EXPORT_SYMBOL_GPL(…);
int qcom_ice_evict_key(struct qcom_ice *ice, int slot)
{ … }
EXPORT_SYMBOL_GPL(…);
static struct qcom_ice *qcom_ice_create(struct device *dev,
void __iomem *base)
{ … }
struct qcom_ice *of_qcom_ice_get(struct device *dev)
{ … }
EXPORT_SYMBOL_GPL(…);
static int qcom_ice_probe(struct platform_device *pdev)
{ … }
static const struct of_device_id qcom_ice_of_match_table[] = …;
MODULE_DEVICE_TABLE(of, qcom_ice_of_match_table);
static struct platform_driver qcom_ice_driver = …;
module_platform_driver(…) …;
MODULE_DESCRIPTION(…) …;
MODULE_LICENSE(…) …;