linux/drivers/pmdomain/starfive/jh71xx-pmu.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * StarFive JH71XX PMU (Power Management Unit) Controller Driver
 *
 * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
 */

#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <dt-bindings/power/starfive,jh7110-pmu.h>

/* register offset */
#define JH71XX_PMU_SW_TURN_ON_POWER
#define JH71XX_PMU_SW_TURN_OFF_POWER
#define JH71XX_PMU_SW_ENCOURAGE
#define JH71XX_PMU_TIMER_INT_MASK
#define JH71XX_PMU_CURR_POWER_MODE
#define JH71XX_PMU_EVENT_STATUS
#define JH71XX_PMU_INT_STATUS

/* aon pmu register offset */
#define JH71XX_AON_PMU_SWITCH

/* sw encourage cfg */
#define JH71XX_PMU_SW_ENCOURAGE_EN_LO
#define JH71XX_PMU_SW_ENCOURAGE_EN_HI
#define JH71XX_PMU_SW_ENCOURAGE_DIS_LO
#define JH71XX_PMU_SW_ENCOURAGE_DIS_HI
#define JH71XX_PMU_SW_ENCOURAGE_ON

/* pmu int status */
#define JH71XX_PMU_INT_SEQ_DONE
#define JH71XX_PMU_INT_HW_REQ
#define JH71XX_PMU_INT_SW_FAIL
#define JH71XX_PMU_INT_HW_FAIL
#define JH71XX_PMU_INT_PCH_FAIL
#define JH71XX_PMU_INT_ALL_MASK

/*
 * The time required for switching power status is based on the time
 * to turn on the largest domain's power, which is at microsecond level
 */
#define JH71XX_PMU_TIMEOUT_US

struct jh71xx_domain_info {};

struct jh71xx_pmu;
struct jh71xx_pmu_dev;

struct jh71xx_pmu_match_data {};

struct jh71xx_pmu {};

struct jh71xx_pmu_dev {};

static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool *is_on)
{}

static int jh7110_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
{}

static int jh7110_aon_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
{}

static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
{}

static int jh71xx_pmu_on(struct generic_pm_domain *genpd)
{}

static int jh71xx_pmu_off(struct generic_pm_domain *genpd)
{}

static void jh71xx_pmu_int_enable(struct jh71xx_pmu *pmu, u32 mask, bool enable)
{}

static irqreturn_t jh71xx_pmu_interrupt(int irq, void *data)
{}

static int jh7110_pmu_parse_irq(struct platform_device *pdev, struct jh71xx_pmu *pmu)
{}

static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index)
{}

static int jh71xx_pmu_probe(struct platform_device *pdev)
{}

static const struct jh71xx_domain_info jh7110_power_domains[] =;

static const struct jh71xx_pmu_match_data jh7110_pmu =;

static const struct jh71xx_domain_info jh7110_aon_power_domains[] =;

static const struct jh71xx_pmu_match_data jh7110_aon_pmu =;

static const struct of_device_id jh71xx_pmu_of_match[] =;

static struct platform_driver jh71xx_pmu_driver =;
builtin_platform_driver();

MODULE_AUTHOR();
MODULE_AUTHOR();
MODULE_DESCRIPTION();
MODULE_LICENSE();