linux/include/dt-bindings/power/mt8195-power.h

/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
 * Copyright (c) 2021 MediaTek Inc.
 * Author: Chun-Jie Chen <[email protected]>
 */

#ifndef _DT_BINDINGS_POWER_MT8195_POWER_H
#define _DT_BINDINGS_POWER_MT8195_POWER_H

#define MT8195_POWER_DOMAIN_PCIE_MAC_P0 …
#define MT8195_POWER_DOMAIN_PCIE_MAC_P1 …
#define MT8195_POWER_DOMAIN_PCIE_PHY …
#define MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY …
#define MT8195_POWER_DOMAIN_CSI_RX_TOP …
#define MT8195_POWER_DOMAIN_ETHER …
#define MT8195_POWER_DOMAIN_ADSP …
#define MT8195_POWER_DOMAIN_AUDIO …
#define MT8195_POWER_DOMAIN_MFG0 …
#define MT8195_POWER_DOMAIN_MFG1 …
#define MT8195_POWER_DOMAIN_MFG2 …
#define MT8195_POWER_DOMAIN_MFG3 …
#define MT8195_POWER_DOMAIN_MFG4 …
#define MT8195_POWER_DOMAIN_MFG5 …
#define MT8195_POWER_DOMAIN_MFG6 …
#define MT8195_POWER_DOMAIN_VPPSYS0 …
#define MT8195_POWER_DOMAIN_VDOSYS0 …
#define MT8195_POWER_DOMAIN_VPPSYS1 …
#define MT8195_POWER_DOMAIN_VDOSYS1 …
#define MT8195_POWER_DOMAIN_DP_TX …
#define MT8195_POWER_DOMAIN_EPD_TX …
#define MT8195_POWER_DOMAIN_HDMI_TX …
#define MT8195_POWER_DOMAIN_WPESYS …
#define MT8195_POWER_DOMAIN_VDEC0 …
#define MT8195_POWER_DOMAIN_VDEC1 …
#define MT8195_POWER_DOMAIN_VDEC2 …
#define MT8195_POWER_DOMAIN_VENC …
#define MT8195_POWER_DOMAIN_VENC_CORE1 …
#define MT8195_POWER_DOMAIN_IMG …
#define MT8195_POWER_DOMAIN_DIP …
#define MT8195_POWER_DOMAIN_IPE …
#define MT8195_POWER_DOMAIN_CAM …
#define MT8195_POWER_DOMAIN_CAM_RAWA …
#define MT8195_POWER_DOMAIN_CAM_RAWB …
#define MT8195_POWER_DOMAIN_CAM_MRAW …

#endif /* _DT_BINDINGS_POWER_MT8195_POWER_H */