/* * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ #ifndef MLX5_IFC_FPGA_H #define MLX5_IFC_FPGA_H struct mlx5_ifc_fpga_shell_caps_bits { … }; struct mlx5_ifc_fpga_cap_bits { … }; enum { … }; struct mlx5_ifc_fpga_ctrl_bits { … }; enum { … }; struct mlx5_ifc_fpga_error_event_bits { … }; #define MLX5_FPGA_ACCESS_REG_SIZE_MAX … struct mlx5_ifc_fpga_access_reg_bits { … }; enum mlx5_ifc_fpga_qp_state { … }; enum mlx5_ifc_fpga_qp_type { … }; enum mlx5_ifc_fpga_qp_service_type { … }; struct mlx5_ifc_fpga_qpc_bits { … }; struct mlx5_ifc_fpga_create_qp_in_bits { … }; struct mlx5_ifc_fpga_create_qp_out_bits { … }; struct mlx5_ifc_fpga_modify_qp_in_bits { … }; struct mlx5_ifc_fpga_modify_qp_out_bits { … }; struct mlx5_ifc_fpga_query_qp_in_bits { … }; struct mlx5_ifc_fpga_query_qp_out_bits { … }; struct mlx5_ifc_fpga_query_qp_counters_in_bits { … }; struct mlx5_ifc_fpga_query_qp_counters_out_bits { … }; struct mlx5_ifc_fpga_destroy_qp_in_bits { … }; struct mlx5_ifc_fpga_destroy_qp_out_bits { … }; enum { … }; struct mlx5_ifc_fpga_qp_error_event_bits { … }; #endif /* MLX5_IFC_FPGA_H */