/* * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ #ifndef MLX5_DEVICE_H #define MLX5_DEVICE_H #include <linux/types.h> #include <rdma/ib_verbs.h> #include <linux/mlx5/mlx5_ifc.h> #include <linux/bitfield.h> #if defined(__LITTLE_ENDIAN) #define MLX5_SET_HOST_ENDIANNESS … #elif defined(__BIG_ENDIAN) #define MLX5_SET_HOST_ENDIANNESS … #else #error Host endianness not defined #endif /* helper macros */ #define __mlx5_nullp(typ) … #define __mlx5_bit_sz(typ, fld) … #define __mlx5_bit_off(typ, fld) … #define __mlx5_16_off(typ, fld) … #define __mlx5_dw_off(typ, fld) … #define __mlx5_64_off(typ, fld) … #define __mlx5_16_bit_off(typ, fld) … #define __mlx5_dw_bit_off(typ, fld) … #define __mlx5_mask(typ, fld) … #define __mlx5_dw_mask(typ, fld) … #define __mlx5_mask16(typ, fld) … #define __mlx5_16_mask(typ, fld) … #define __mlx5_st_sz_bits(typ) … #define MLX5_FLD_SZ_BYTES(typ, fld) … #define MLX5_ST_SZ_BYTES(typ) … #define MLX5_ST_SZ_DW(typ) … #define MLX5_ST_SZ_QW(typ) … #define MLX5_UN_SZ_BYTES(typ) … #define MLX5_UN_SZ_DW(typ) … #define MLX5_BYTE_OFF(typ, fld) … #define MLX5_ADDR_OF(typ, p, fld) … /* insert a value to a struct */ #define MLX5_SET(typ, p, fld, v) … #define MLX5_ARRAY_SET(typ, p, fld, idx, v) … #define MLX5_SET_TO_ONES(typ, p, fld) … #define MLX5_GET(typ, p, fld) … #define MLX5_GET_PR(typ, p, fld) … #define __MLX5_SET64(typ, p, fld, v) … #define MLX5_SET64(typ, p, fld, v) … #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) … #define MLX5_GET64(typ, p, fld) … #define MLX5_GET64_PR(typ, p, fld) … #define MLX5_GET16(typ, p, fld) … #define MLX5_SET16(typ, p, fld, v) … /* Big endian getters */ #define MLX5_GET64_BE(typ, p, fld) … #define MLX5_GET_BE(type_t, typ, p, fld) … enum mlx5_inline_modes { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum wqe_page_fault_type { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; #define MLX5_UMR_FLEX_ALIGNMENT … #define MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT … #define MLX5_UMR_KLM_NUM_ENTRIES_ALIGNMENT … #define MLX5_UMR_KSM_NUM_ENTRIES_ALIGNMENT … #define MLX5_USER_INDEX_LEN … enum { … }; /* mlx5 components can subscribe to any one of these events via * mlx5_eq_notifier_register API. */ enum mlx5_event { … }; enum mlx5_driver_event { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; struct mlx5_wqe_tls_static_params_seg { … }; struct mlx5_wqe_tls_progress_params_seg { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum mlx5_odp_transport_cap_bits { … }; struct mlx5_odp_caps { … }; struct mlx5_cmd_layout { … }; enum mlx5_rfr_severity_bit_offsets { … }; struct health_buffer { … }; enum mlx5_initializing_bit_offsets { … }; enum mlx5_cmd_addr_l_sz_offset { … }; struct mlx5_init_seg { … }; struct mlx5_eqe_comp { … }; struct mlx5_eqe_qp_srq { … }; struct mlx5_eqe_cq_err { … }; struct mlx5_eqe_xrq_err { … }; struct mlx5_eqe_port_state { … }; struct mlx5_eqe_gpio { … }; struct mlx5_eqe_congestion { … }; struct mlx5_eqe_stall_vl { … }; struct mlx5_eqe_cmd { … }; struct mlx5_eqe_page_req { … }; struct mlx5_eqe_page_fault { … } __packed; struct mlx5_eqe_vport_change { … } __packed; struct mlx5_eqe_port_module { … } __packed; struct mlx5_eqe_pps { … } __packed; struct mlx5_eqe_dct { … }; struct mlx5_eqe_temp_warning { … } __packed; struct mlx5_eqe_obj_change { … } __packed; #define SYNC_RST_STATE_MASK … enum sync_rst_state_type { … }; struct mlx5_eqe_sync_fw_update { … }; struct mlx5_eqe_vhca_state { … } __packed; ev_data __packed; struct mlx5_eqe { … } __packed; struct mlx5_cmd_prot_block { … }; enum { … }; struct mlx5_err_cqe { … }; struct mlx5_cqe64 { … }; struct mlx5_mini_cqe8 { … }; enum { … }; enum { … }; enum { … }; #define MLX5_MINI_CQE_ARRAY_SIZE … static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe) { … } static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe) { … } static inline u8 get_cqe_enhanced_num_mini_cqes(struct mlx5_cqe64 *cqe) { … } static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) { … } static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) { … } static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) { … } static inline u8 get_cqe_tls_offload(struct mlx5_cqe64 *cqe) { … } static inline bool cqe_has_vlan(const struct mlx5_cqe64 *cqe) { … } static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe) { … } static inline u16 get_cqe_flow_tag(struct mlx5_cqe64 *cqe) { … } #define MLX5_MPWQE_LOG_NUM_STRIDES_EXT_BASE … #define MLX5_MPWQE_LOG_NUM_STRIDES_BASE … #define MLX5_MPWQE_LOG_NUM_STRIDES_MAX … #define MLX5_MPWQE_LOG_STRIDE_SZ_BASE … #define MLX5_MPWQE_LOG_STRIDE_SZ_MAX … struct mpwrq_cqe_bc { … }; static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe) { … } static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc) { … } static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe) { … } static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe) { … } static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe) { … } enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; struct mlx5_sig_err_cqe { … }; struct mlx5_wqe_srq_next_seg { … }; mlx5_ext_cqe; struct mlx5_cqe128 { … }; enum { … }; enum { … }; struct mlx5_mkey_seg { … }; #define MLX5_ATTR_EXTENDED_PORT_INFO … enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum mlx5_list_type { … }; enum { … }; enum mlx5_wol_mode { … }; enum mlx5_mpls_supported_fields { … }; enum mlx5_flex_parser_protos { … }; /* MLX5 DEV CAPs */ /* TODO: EAT.ME */ enum mlx5_cap_mode { … }; /* Any new cap addition must update mlx5_hca_caps_alloc() to allocate * capability memory. */ enum mlx5_cap_type { … }; enum mlx5_pcam_reg_groups { … }; enum mlx5_pcam_feature_groups { … }; enum mlx5_mcam_reg_groups { … }; enum mlx5_mcam_feature_groups { … }; enum mlx5_qcam_reg_groups { … }; enum mlx5_qcam_feature_groups { … }; /* GET Dev Caps macros */ #define MLX5_CAP_GEN(mdev, cap) … #define MLX5_CAP_GEN_64(mdev, cap) … #define MLX5_CAP_GEN_MAX(mdev, cap) … #define MLX5_CAP_GEN_2(mdev, cap) … #define MLX5_CAP_GEN_2_64(mdev, cap) … #define MLX5_CAP_GEN_2_MAX(mdev, cap) … #define MLX5_CAP_ETH(mdev, cap) … #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) … #define MLX5_CAP_ROCE(mdev, cap) … #define MLX5_CAP_ROCE_MAX(mdev, cap) … #define MLX5_CAP_ATOMIC(mdev, cap) … #define MLX5_CAP_ATOMIC_MAX(mdev, cap) … #define MLX5_CAP_FLOWTABLE(mdev, cap) … #define MLX5_CAP64_FLOWTABLE(mdev, cap) … #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) … #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) … #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) … #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) … #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) … #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) … #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) … #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) … #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) … #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) … #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2(mdev, cap) … #define MLX5_CAP_NIC_RX_FT_FIELD_SUPPORT_2(mdev, cap) … #define MLX5_CAP_ESW(mdev, cap) … #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) … #define MLX5_CAP_PORT_SELECTION(mdev, cap) … #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) … #define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) … #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) … #define MLX5_CAP_PORT_SELECTION_FT_FIELD_SUPPORT_2(mdev, cap) … #define MLX5_CAP_ODP(mdev, cap) … #define MLX5_CAP_ODP_MAX(mdev, cap) … #define MLX5_CAP_QOS(mdev, cap) … #define MLX5_CAP_DEBUG(mdev, cap) … #define MLX5_CAP_PCAM_FEATURE(mdev, fld) … #define MLX5_CAP_PCAM_REG(mdev, reg) … #define MLX5_CAP_MCAM_REG(mdev, reg) … #define MLX5_CAP_MCAM_REG2(mdev, reg) … #define MLX5_CAP_MCAM_FEATURE(mdev, fld) … #define MLX5_CAP_QCAM_REG(mdev, fld) … #define MLX5_CAP_QCAM_FEATURE(mdev, fld) … #define MLX5_CAP_FPGA(mdev, cap) … #define MLX5_CAP64_FPGA(mdev, cap) … #define MLX5_CAP_DEV_MEM(mdev, cap) … #define MLX5_CAP64_DEV_MEM(mdev, cap) … #define MLX5_CAP_TLS(mdev, cap) … #define MLX5_CAP_DEV_EVENT(mdev, cap) … #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap) … #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap) … #define MLX5_CAP_IPSEC(mdev, cap) … #define MLX5_CAP_CRYPTO(mdev, cap) … #define MLX5_CAP_MACSEC(mdev, cap) … enum { … }; enum { … }; enum { … }; static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) { … } #define MLX5_RDMA_RX_NUM_COUNTERS_PRIOS … #define MLX5_RDMA_TX_NUM_COUNTERS_PRIOS … #define MLX5_BY_PASS_NUM_REGULAR_PRIOS … #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS … #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS … #define MLX5_BY_PASS_NUM_PRIOS … #endif /* MLX5_DEVICE_H */
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