linux/include/linux/mlx5/qp.h

/*
 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef MLX5_QP_H
#define MLX5_QP_H

#include <linux/mlx5/device.h>
#include <linux/mlx5/driver.h>

#define MLX5_TERMINATE_SCATTER_LIST_LKEY
/* UMR (3 WQE_BB's) + SIG (3 WQE_BB's) + PSV (mem) + PSV (wire) */
#define MLX5_SIG_WQE_SIZE
#define MLX5_DIF_SIZE
#define MLX5_STRIDE_BLOCK_OP
#define MLX5_CPY_GRD_MASK
#define MLX5_CPY_APP_MASK
#define MLX5_CPY_REF_MASK
#define MLX5_BSF_INC_REFTAG
#define MLX5_BSF_INL_VALID
#define MLX5_BSF_REFRESH_DIF
#define MLX5_BSF_REPEAT_BLOCK
#define MLX5_BSF_APPTAG_ESCAPE
#define MLX5_BSF_APPREF_ESCAPE

enum mlx5_qp_optpar {};

enum mlx5_qp_state {};

enum {};

enum {};

enum {};

enum {};

/* TODO REM */
enum {};

enum {};

enum {};

#define MLX5_SEND_WQEBB_NUM_DS

enum {};

#define MLX5_SEND_WQE_MAX_SIZE

enum {};

enum {};

enum {};

enum {};

struct mlx5_wqe_fmr_seg {};

struct mlx5_wqe_ctrl_seg {};

#define MLX5_WQE_CTRL_DS_MASK
#define MLX5_WQE_CTRL_QPN_MASK
#define MLX5_WQE_CTRL_QPN_SHIFT
#define MLX5_WQE_DS_UNITS
#define MLX5_WQE_CTRL_OPCODE_MASK
#define MLX5_WQE_CTRL_WQE_INDEX_MASK
#define MLX5_WQE_CTRL_WQE_INDEX_SHIFT

enum {};

enum {};

enum {};

enum {};

struct mlx5_wqe_eth_seg {};

struct mlx5_wqe_xrc_seg {};

struct mlx5_wqe_masked_atomic_seg {};

struct mlx5_base_av {};

struct mlx5_av {};

struct mlx5_ib_ah {};

static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah)
{}

struct mlx5_wqe_datagram_seg {};

struct mlx5_wqe_raddr_seg {};

struct mlx5_wqe_atomic_seg {};

struct mlx5_wqe_data_seg {};

struct mlx5_wqe_umr_ctrl_seg {};

struct mlx5_seg_set_psv {};

struct mlx5_seg_get_psv {};

struct mlx5_seg_check_psv {};

struct mlx5_rwqe_sig {};

struct mlx5_wqe_signature_seg {};

#define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK

struct mlx5_wqe_inline_seg {};

enum mlx5_sig_type {};

struct mlx5_bsf_inl {};

struct mlx5_bsf {};

struct mlx5_mtt {};

struct mlx5_klm {};

struct mlx5_ksm {};

struct mlx5_stride_block_entry {};

struct mlx5_stride_block_ctrl_seg {};

struct mlx5_wqe_flow_update_ctrl_seg {};

struct mlx5_wqe_header_modify_argument_update_seg {};

struct mlx5_core_qp {};

struct mlx5_core_dct {};

int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);

static inline const char *mlx5_qp_type_str(int type)
{}

static inline const char *mlx5_qp_state_str(int state)
{}

static inline int mlx5_get_qp_default_ts(struct mlx5_core_dev *dev)
{}

#endif /* MLX5_QP_H */