/* SPDX-License-Identifier: GPL-2.0+ */ /* * max77693-private.h - Voltage regulator driver for the Maxim 77693 * * Copyright (C) 2012 Samsung Electrnoics * SangYoung Son <[email protected]> * * This program is not provided / owned by Maxim Integrated Products. */ #ifndef __LINUX_MFD_MAX77693_PRIV_H #define __LINUX_MFD_MAX77693_PRIV_H #include <linux/i2c.h> #define MAX77693_REG_INVALID … /* Slave addr = 0xCC: PMIC, Charger, Flash LED */ enum max77693_pmic_reg { … }; /* MAX77693 ITORCH register */ #define TORCH_IOUT1_SHIFT … #define TORCH_IOUT2_SHIFT … #define TORCH_IOUT_MASK(x) … #define TORCH_IOUT_MIN … #define TORCH_IOUT_MAX … #define TORCH_IOUT_STEP … /* MAX77693 IFLASH1 and IFLASH2 registers */ #define FLASH_IOUT_MIN … #define FLASH_IOUT_MAX_1LED … #define FLASH_IOUT_MAX_2LEDS … #define FLASH_IOUT_STEP … /* MAX77693 TORCH_TIMER register */ #define TORCH_TMR_NO_TIMER … #define TORCH_TIMEOUT_MIN … #define TORCH_TIMEOUT_MAX … /* MAX77693 FLASH_TIMER register */ #define FLASH_TMR_LEVEL … #define FLASH_TIMEOUT_MIN … #define FLASH_TIMEOUT_MAX … #define FLASH_TIMEOUT_STEP … /* MAX77693 FLASH_EN register */ #define FLASH_EN_OFF … #define FLASH_EN_FLASH … #define FLASH_EN_TORCH … #define FLASH_EN_ON … #define FLASH_EN_SHIFT(x) … #define TORCH_EN_SHIFT(x) … /* MAX77693 MAX_FLASH1 register */ #define MAX_FLASH1_MAX_FL_EN … #define MAX_FLASH1_VSYS_MIN … #define MAX_FLASH1_VSYS_MAX … #define MAX_FLASH1_VSYS_STEP … /* MAX77693 VOUT_CNTL register */ #define FLASH_BOOST_FIXED … #define FLASH_BOOST_LEDNUM_2 … /* MAX77693 VOUT_FLASH1 register */ #define FLASH_VOUT_MIN … #define FLASH_VOUT_MAX … #define FLASH_VOUT_STEP … #define FLASH_VOUT_RMIN … /* MAX77693 FLASH_STATUS register */ #define FLASH_STATUS_FLASH_ON … #define FLASH_STATUS_TORCH_ON … /* MAX77693 FLASH_INT register */ #define FLASH_INT_FLED2_OPEN … #define FLASH_INT_FLED2_SHORT … #define FLASH_INT_FLED1_OPEN … #define FLASH_INT_FLED1_SHORT … #define FLASH_INT_OVER_CURRENT … /* Fast charge timer in hours */ #define DEFAULT_FAST_CHARGE_TIMER … /* microamps */ #define DEFAULT_TOP_OFF_THRESHOLD_CURRENT … /* minutes */ #define DEFAULT_TOP_OFF_TIMER … /* microvolts */ #define DEFAULT_CONSTANT_VOLT … /* microvolts */ #define DEFAULT_MIN_SYSTEM_VOLT … /* celsius */ #define DEFAULT_THERMAL_REGULATION_TEMP … /* microamps */ #define DEFAULT_BATTERY_OVERCURRENT … /* microvolts */ #define DEFAULT_CHARGER_INPUT_THRESHOLD_VOLT … /* MAX77693_CHG_REG_CHG_INT_OK register */ #define CHG_INT_OK_BYP_SHIFT … #define CHG_INT_OK_BAT_SHIFT … #define CHG_INT_OK_CHG_SHIFT … #define CHG_INT_OK_CHGIN_SHIFT … #define CHG_INT_OK_DETBAT_SHIFT … #define CHG_INT_OK_BYP_MASK … #define CHG_INT_OK_BAT_MASK … #define CHG_INT_OK_CHG_MASK … #define CHG_INT_OK_CHGIN_MASK … #define CHG_INT_OK_DETBAT_MASK … /* MAX77693_CHG_REG_CHG_DETAILS_00 register */ #define CHG_DETAILS_00_CHGIN_SHIFT … #define CHG_DETAILS_00_CHGIN_MASK … /* MAX77693_CHG_REG_CHG_DETAILS_01 register */ #define CHG_DETAILS_01_CHG_SHIFT … #define CHG_DETAILS_01_BAT_SHIFT … #define CHG_DETAILS_01_TREG_SHIFT … #define CHG_DETAILS_01_CHG_MASK … #define CHG_DETAILS_01_BAT_MASK … #define CHG_DETAILS_01_TREG_MASK … /* MAX77693_CHG_REG_CHG_DETAILS_01/CHG field */ enum max77693_charger_charging_state { … }; /* MAX77693_CHG_REG_CHG_DETAILS_01/BAT field */ enum max77693_charger_battery_state { … }; /* MAX77693_CHG_REG_CHG_DETAILS_02 register */ #define CHG_DETAILS_02_BYP_SHIFT … #define CHG_DETAILS_02_BYP_MASK … /* MAX77693 CHG_CNFG_00 register */ #define CHG_CNFG_00_CHG_MASK … #define CHG_CNFG_00_BUCK_MASK … /* MAX77693_CHG_REG_CHG_CNFG_01 register */ #define CHG_CNFG_01_FCHGTIME_SHIFT … #define CHG_CNFG_01_CHGRSTRT_SHIFT … #define CHG_CNFG_01_PQEN_SHIFT … #define CHG_CNFG_01_FCHGTIME_MASK … #define CHG_CNFG_01_CHGRSTRT_MASK … #define CHG_CNFG_01_PQEN_MAKS … /* MAX77693_CHG_REG_CHG_CNFG_03 register */ #define CHG_CNFG_03_TOITH_SHIFT … #define CHG_CNFG_03_TOTIME_SHIFT … #define CHG_CNFG_03_TOITH_MASK … #define CHG_CNFG_03_TOTIME_MASK … /* MAX77693_CHG_REG_CHG_CNFG_04 register */ #define CHG_CNFG_04_CHGCVPRM_SHIFT … #define CHG_CNFG_04_MINVSYS_SHIFT … #define CHG_CNFG_04_CHGCVPRM_MASK … #define CHG_CNFG_04_MINVSYS_MASK … /* MAX77693_CHG_REG_CHG_CNFG_06 register */ #define CHG_CNFG_06_CHGPROT_SHIFT … #define CHG_CNFG_06_CHGPROT_MASK … /* MAX77693_CHG_REG_CHG_CNFG_07 register */ #define CHG_CNFG_07_REGTEMP_SHIFT … #define CHG_CNFG_07_REGTEMP_MASK … /* MAX77693_CHG_REG_CHG_CNFG_12 register */ #define CHG_CNFG_12_B2SOVRC_SHIFT … #define CHG_CNFG_12_VCHGINREG_SHIFT … #define CHG_CNFG_12_B2SOVRC_MASK … #define CHG_CNFG_12_VCHGINREG_MASK … /* MAX77693 CHG_CNFG_09 Register */ #define CHG_CNFG_09_CHGIN_ILIM_MASK … /* MAX77693 CHG_CTRL Register */ #define SAFEOUT_CTRL_SAFEOUT1_MASK … #define SAFEOUT_CTRL_SAFEOUT2_MASK … #define SAFEOUT_CTRL_ENSAFEOUT1_MASK … #define SAFEOUT_CTRL_ENSAFEOUT2_MASK … /* Slave addr = 0x4A: MUIC */ enum max77693_muic_reg { … }; /* MAX77693 INTMASK1~2 Register */ #define INTMASK1_ADC1K_SHIFT … #define INTMASK1_ADCERR_SHIFT … #define INTMASK1_ADCLOW_SHIFT … #define INTMASK1_ADC_SHIFT … #define INTMASK1_ADC1K_MASK … #define INTMASK1_ADCERR_MASK … #define INTMASK1_ADCLOW_MASK … #define INTMASK1_ADC_MASK … #define INTMASK2_VIDRM_SHIFT … #define INTMASK2_VBVOLT_SHIFT … #define INTMASK2_DXOVP_SHIFT … #define INTMASK2_DCDTMR_SHIFT … #define INTMASK2_CHGDETRUN_SHIFT … #define INTMASK2_CHGTYP_SHIFT … #define INTMASK2_VIDRM_MASK … #define INTMASK2_VBVOLT_MASK … #define INTMASK2_DXOVP_MASK … #define INTMASK2_DCDTMR_MASK … #define INTMASK2_CHGDETRUN_MASK … #define INTMASK2_CHGTYP_MASK … /* MAX77693 MUIC - STATUS1~3 Register */ #define MAX77693_STATUS1_ADC_SHIFT … #define MAX77693_STATUS1_ADCLOW_SHIFT … #define MAX77693_STATUS1_ADCERR_SHIFT … #define MAX77693_STATUS1_ADC1K_SHIFT … #define MAX77693_STATUS1_ADC_MASK … #define MAX77693_STATUS1_ADCLOW_MASK … #define MAX77693_STATUS1_ADCERR_MASK … #define MAX77693_STATUS1_ADC1K_MASK … #define MAX77693_STATUS2_CHGTYP_SHIFT … #define MAX77693_STATUS2_CHGDETRUN_SHIFT … #define MAX77693_STATUS2_DCDTMR_SHIFT … #define MAX77693_STATUS2_DXOVP_SHIFT … #define MAX77693_STATUS2_VBVOLT_SHIFT … #define MAX77693_STATUS2_VIDRM_SHIFT … #define MAX77693_STATUS2_CHGTYP_MASK … #define MAX77693_STATUS2_CHGDETRUN_MASK … #define MAX77693_STATUS2_DCDTMR_MASK … #define MAX77693_STATUS2_DXOVP_MASK … #define MAX77693_STATUS2_VBVOLT_MASK … #define MAX77693_STATUS2_VIDRM_MASK … #define MAX77693_STATUS3_OVP_SHIFT … #define MAX77693_STATUS3_OVP_MASK … /* MAX77693 CDETCTRL1~2 register */ #define CDETCTRL1_CHGDETEN_SHIFT … #define CDETCTRL1_CHGTYPMAN_SHIFT … #define CDETCTRL1_DCDEN_SHIFT … #define CDETCTRL1_DCD2SCT_SHIFT … #define CDETCTRL1_CDDELAY_SHIFT … #define CDETCTRL1_DCDCPL_SHIFT … #define CDETCTRL1_CDPDET_SHIFT … #define CDETCTRL1_CHGDETEN_MASK … #define CDETCTRL1_CHGTYPMAN_MASK … #define CDETCTRL1_DCDEN_MASK … #define CDETCTRL1_DCD2SCT_MASK … #define CDETCTRL1_CDDELAY_MASK … #define CDETCTRL1_DCDCPL_MASK … #define CDETCTRL1_CDPDET_MASK … #define CDETCTRL2_VIDRMEN_SHIFT … #define CDETCTRL2_DXOVPEN_SHIFT … #define CDETCTRL2_VIDRMEN_MASK … #define CDETCTRL2_DXOVPEN_MASK … /* MAX77693 MUIC - CONTROL1~3 register */ #define COMN1SW_SHIFT … #define COMP2SW_SHIFT … #define COMN1SW_MASK … #define COMP2SW_MASK … #define COMP_SW_MASK … #define MAX77693_CONTROL1_SW_USB … #define MAX77693_CONTROL1_SW_AUDIO … #define MAX77693_CONTROL1_SW_UART … #define MAX77693_CONTROL1_SW_OPEN … #define MAX77693_CONTROL2_LOWPWR_SHIFT … #define MAX77693_CONTROL2_ADCEN_SHIFT … #define MAX77693_CONTROL2_CPEN_SHIFT … #define MAX77693_CONTROL2_SFOUTASRT_SHIFT … #define MAX77693_CONTROL2_SFOUTORD_SHIFT … #define MAX77693_CONTROL2_ACCDET_SHIFT … #define MAX77693_CONTROL2_USBCPINT_SHIFT … #define MAX77693_CONTROL2_RCPS_SHIFT … #define MAX77693_CONTROL2_LOWPWR_MASK … #define MAX77693_CONTROL2_ADCEN_MASK … #define MAX77693_CONTROL2_CPEN_MASK … #define MAX77693_CONTROL2_SFOUTASRT_MASK … #define MAX77693_CONTROL2_SFOUTORD_MASK … #define MAX77693_CONTROL2_ACCDET_MASK … #define MAX77693_CONTROL2_USBCPINT_MASK … #define MAX77693_CONTROL2_RCPS_MASK … #define MAX77693_CONTROL3_JIGSET_SHIFT … #define MAX77693_CONTROL3_BTLDSET_SHIFT … #define MAX77693_CONTROL3_ADCDBSET_SHIFT … #define MAX77693_CONTROL3_JIGSET_MASK … #define MAX77693_CONTROL3_BTLDSET_MASK … #define MAX77693_CONTROL3_ADCDBSET_MASK … /* Slave addr = 0x90: Haptic */ enum max77693_haptic_reg { … }; /* max77693-pmic LSCNFG configuration register */ #define MAX77693_PMIC_LOW_SYS_MASK … #define MAX77693_PMIC_LOW_SYS_SHIFT … /* max77693-haptic configuration register */ #define MAX77693_CONFIG2_MODE … #define MAX77693_CONFIG2_MEN … #define MAX77693_CONFIG2_HTYP … enum max77693_irq_source { … }; #define SRC_IRQ_CHARGER … #define SRC_IRQ_TOP … #define SRC_IRQ_FLASH … #define SRC_IRQ_MUIC … #define SRC_IRQ_ALL … #define LED_IRQ_FLED2_OPEN … #define LED_IRQ_FLED2_SHORT … #define LED_IRQ_FLED1_OPEN … #define LED_IRQ_FLED1_SHORT … #define LED_IRQ_MAX_FLASH … #define TOPSYS_IRQ_T120C_INT … #define TOPSYS_IRQ_T140C_INT … #define TOPSYS_IRQ_LOWSYS_INT … #define CHG_IRQ_BYP_I … #define CHG_IRQ_THM_I … #define CHG_IRQ_BAT_I … #define CHG_IRQ_CHG_I … #define CHG_IRQ_CHGIN_I … #define MUIC_IRQ_INT1_ADC … #define MUIC_IRQ_INT1_ADC_LOW … #define MUIC_IRQ_INT1_ADC_ERR … #define MUIC_IRQ_INT1_ADC1K … #define MUIC_IRQ_INT2_CHGTYP … #define MUIC_IRQ_INT2_CHGDETREUN … #define MUIC_IRQ_INT2_DCDTMR … #define MUIC_IRQ_INT2_DXOVP … #define MUIC_IRQ_INT2_VBVOLT … #define MUIC_IRQ_INT2_VIDRM … #define MUIC_IRQ_INT3_EOC … #define MUIC_IRQ_INT3_CGMBC … #define MUIC_IRQ_INT3_OVP … #define MUIC_IRQ_INT3_MBCCHG_ERR … #define MUIC_IRQ_INT3_CHG_ENABLED … #define MUIC_IRQ_INT3_BAT_DET … enum max77693_irq { … }; enum max77693_irq_muic { … }; #endif /* __LINUX_MFD_MAX77693_PRIV_H */
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