linux/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h

/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
 * Copyright (C) 2023 Renesas Electronics Corp.
 */
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__

#include <dt-bindings/clock/renesas-cpg-mssr.h>

/* r8a779h0 CPG Core Clocks */

#define R8A779H0_CLK_ZX …
#define R8A779H0_CLK_ZD …
#define R8A779H0_CLK_ZS …
#define R8A779H0_CLK_ZT …
#define R8A779H0_CLK_ZTR …
#define R8A779H0_CLK_S0D2 …
#define R8A779H0_CLK_S0D3 …
#define R8A779H0_CLK_S0D4 …
#define R8A779H0_CLK_S0D1_VIO …
#define R8A779H0_CLK_S0D2_VIO …
#define R8A779H0_CLK_S0D4_VIO …
#define R8A779H0_CLK_S0D8_VIO …
#define R8A779H0_CLK_VIOBUSD1 …
#define R8A779H0_CLK_VIOBUSD2 …
#define R8A779H0_CLK_S0D1_VC …
#define R8A779H0_CLK_S0D2_VC …
#define R8A779H0_CLK_S0D4_VC …
#define R8A779H0_CLK_VCBUSD1 …
#define R8A779H0_CLK_VCBUSD2 …
#define R8A779H0_CLK_S0D2_MM …
#define R8A779H0_CLK_S0D4_MM …
#define R8A779H0_CLK_S0D2_U3DG …
#define R8A779H0_CLK_S0D4_U3DG …
#define R8A779H0_CLK_S0D2_RT …
#define R8A779H0_CLK_S0D3_RT …
#define R8A779H0_CLK_S0D4_RT …
#define R8A779H0_CLK_S0D6_RT …
#define R8A779H0_CLK_S0D2_PER …
#define R8A779H0_CLK_S0D3_PER …
#define R8A779H0_CLK_S0D4_PER …
#define R8A779H0_CLK_S0D6_PER …
#define R8A779H0_CLK_S0D12_PER …
#define R8A779H0_CLK_S0D24_PER …
#define R8A779H0_CLK_S0D1_HSC …
#define R8A779H0_CLK_S0D2_HSC …
#define R8A779H0_CLK_S0D4_HSC …
#define R8A779H0_CLK_S0D8_HSC …
#define R8A779H0_CLK_SVD1_IR …
#define R8A779H0_CLK_SVD2_IR …
#define R8A779H0_CLK_IMPAD1 …
#define R8A779H0_CLK_IMPAD4 …
#define R8A779H0_CLK_IMPB …
#define R8A779H0_CLK_SVD1_VIP …
#define R8A779H0_CLK_SVD2_VIP …
#define R8A779H0_CLK_CL …
#define R8A779H0_CLK_CL16M …
#define R8A779H0_CLK_CL16M_MM …
#define R8A779H0_CLK_CL16M_RT …
#define R8A779H0_CLK_CL16M_PER …
#define R8A779H0_CLK_CL16M_HSC …
#define R8A779H0_CLK_ZC0 …
#define R8A779H0_CLK_ZC1 …
#define R8A779H0_CLK_ZC2 …
#define R8A779H0_CLK_ZC3 …
#define R8A779H0_CLK_ZB3 …
#define R8A779H0_CLK_ZB3D2 …
#define R8A779H0_CLK_ZB3D4 …
#define R8A779H0_CLK_ZG …
#define R8A779H0_CLK_SD0H …
#define R8A779H0_CLK_SD0 …
#define R8A779H0_CLK_RPC …
#define R8A779H0_CLK_RPCD2 …
#define R8A779H0_CLK_MSO …
#define R8A779H0_CLK_CANFD …
#define R8A779H0_CLK_CSI …
#define R8A779H0_CLK_FRAY …
#define R8A779H0_CLK_IPC …
#define R8A779H0_CLK_SASYNCRT …
#define R8A779H0_CLK_SASYNCPERD1 …
#define R8A779H0_CLK_SASYNCPERD2 …
#define R8A779H0_CLK_SASYNCPERD4 …
#define R8A779H0_CLK_DSIEXT …
#define R8A779H0_CLK_DSIREF …
#define R8A779H0_CLK_ADGH …
#define R8A779H0_CLK_OSC …
#define R8A779H0_CLK_ZR0 …
#define R8A779H0_CLK_ZR1 …
#define R8A779H0_CLK_ZR2 …
#define R8A779H0_CLK_RGMII …
#define R8A779H0_CLK_CPEX …
#define R8A779H0_CLK_CP …
#define R8A779H0_CLK_CBFUSA …
#define R8A779H0_CLK_R …

#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ */