/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright Intel Corporation (C) 2014-2016. All Rights Reserved * * Declarations for Altera Arria10 MAX5 System Resource Chip * * Adapted from DA9052 */ #ifndef __MFD_ALTERA_A10SR_H #define __MFD_ALTERA_A10SR_H #include <linux/completion.h> #include <linux/list.h> #include <linux/mfd/core.h> #include <linux/regmap.h> #include <linux/slab.h> /* Write registers are always on even addresses */ #define WRITE_REG_MASK … /* Odd registers are always on odd addresses */ #define READ_REG_MASK … #define ALTR_A10SR_BITS_PER_REGISTER … /* * To find the correct register, we divide the input GPIO by * the number of GPIO in each register. We then need to multiply * by 2 because the reads are at odd addresses. */ #define ALTR_A10SR_REG_OFFSET(X) … #define ALTR_A10SR_REG_BIT(X) … #define ALTR_A10SR_REG_BIT_CHG(X, Y) … #define ALTR_A10SR_REG_BIT_MASK(X) … /* Arria10 System Controller Register Defines */ #define ALTR_A10SR_NOP … #define ALTR_A10SR_VERSION_READ … #define ALTR_A10SR_LED_REG … /* LED register Bit Definitions */ #define ALTR_A10SR_LED_VALID_SHIFT … #define ALTR_A10SR_OUT_VALID_RANGE_LO … #define ALTR_A10SR_OUT_VALID_RANGE_HI … #define ALTR_A10SR_PBDSW_REG … #define ALTR_A10SR_PBDSW_IRQ_REG … /* Pushbutton & DIP Switch Bit Definitions */ #define ALTR_A10SR_IN_VALID_RANGE_LO … #define ALTR_A10SR_IN_VALID_RANGE_HI … #define ALTR_A10SR_PWR_GOOD1_REG … #define ALTR_A10SR_PWR_GOOD2_REG … #define ALTR_A10SR_PWR_GOOD3_REG … #define ALTR_A10SR_FMCAB_REG … #define ALTR_A10SR_HPS_RST_REG … #define ALTR_A10SR_USB_QSPI_REG … #define ALTR_A10SR_SFPA_REG … #define ALTR_A10SR_SFPB_REG … #define ALTR_A10SR_I2C_M_REG … #define ALTR_A10SR_WARM_RST_REG … #define ALTR_A10SR_WR_KEY_REG … #define ALTR_A10SR_PMBUS_REG … /** * struct altr_a10sr - Altera Max5 MFD device private data structure * @dev: : this device * @regmap: the regmap assigned to the parent device. */ struct altr_a10sr { … }; #endif /* __MFD_ALTERA_A10SR_H */
Codebase Browser
linux