/* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* * Copyright (C) 2022 Emil Renner Berthing <[email protected]> * Copyright (C) 2022 StarFive Technology Co., Ltd. */ #ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ #define __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ /* SYSCRG resets */ #define JH7110_SYSRST_JTAG_APB … #define JH7110_SYSRST_SYSCON_APB … #define JH7110_SYSRST_IOMUX_APB … #define JH7110_SYSRST_BUS … #define JH7110_SYSRST_DEBUG … #define JH7110_SYSRST_CORE0 … #define JH7110_SYSRST_CORE1 … #define JH7110_SYSRST_CORE2 … #define JH7110_SYSRST_CORE3 … #define JH7110_SYSRST_CORE4 … #define JH7110_SYSRST_CORE0_ST … #define JH7110_SYSRST_CORE1_ST … #define JH7110_SYSRST_CORE2_ST … #define JH7110_SYSRST_CORE3_ST … #define JH7110_SYSRST_CORE4_ST … #define JH7110_SYSRST_TRACE0 … #define JH7110_SYSRST_TRACE1 … #define JH7110_SYSRST_TRACE2 … #define JH7110_SYSRST_TRACE3 … #define JH7110_SYSRST_TRACE4 … #define JH7110_SYSRST_TRACE_COM … #define JH7110_SYSRST_GPU_APB … #define JH7110_SYSRST_GPU_DOMA … #define JH7110_SYSRST_NOC_BUS_APB … #define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI … #define JH7110_SYSRST_NOC_BUS_CPU_AXI … #define JH7110_SYSRST_NOC_BUS_DISP_AXI … #define JH7110_SYSRST_NOC_BUS_GPU_AXI … #define JH7110_SYSRST_NOC_BUS_ISP_AXI … #define JH7110_SYSRST_NOC_BUS_DDRC … #define JH7110_SYSRST_NOC_BUS_STG_AXI … #define JH7110_SYSRST_NOC_BUS_VDEC_AXI … #define JH7110_SYSRST_NOC_BUS_VENC_AXI … #define JH7110_SYSRST_AXI_CFG1_AHB … #define JH7110_SYSRST_AXI_CFG1_MAIN … #define JH7110_SYSRST_AXI_CFG0_MAIN … #define JH7110_SYSRST_AXI_CFG0_MAIN_DIV … #define JH7110_SYSRST_AXI_CFG0_HIFI4 … #define JH7110_SYSRST_DDR_AXI … #define JH7110_SYSRST_DDR_OSC … #define JH7110_SYSRST_DDR_APB … #define JH7110_SYSRST_ISP_TOP … #define JH7110_SYSRST_ISP_TOP_AXI … #define JH7110_SYSRST_VOUT_TOP_SRC … #define JH7110_SYSRST_CODAJ12_AXI … #define JH7110_SYSRST_CODAJ12_CORE … #define JH7110_SYSRST_CODAJ12_APB … #define JH7110_SYSRST_WAVE511_AXI … #define JH7110_SYSRST_WAVE511_BPU … #define JH7110_SYSRST_WAVE511_VCE … #define JH7110_SYSRST_WAVE511_APB … #define JH7110_SYSRST_VDEC_JPG … #define JH7110_SYSRST_VDEC_MAIN … #define JH7110_SYSRST_AXIMEM0_AXI … #define JH7110_SYSRST_WAVE420L_AXI … #define JH7110_SYSRST_WAVE420L_BPU … #define JH7110_SYSRST_WAVE420L_VCE … #define JH7110_SYSRST_WAVE420L_APB … #define JH7110_SYSRST_AXIMEM1_AXI … #define JH7110_SYSRST_AXIMEM2_AXI … #define JH7110_SYSRST_INTMEM … #define JH7110_SYSRST_QSPI_AHB … #define JH7110_SYSRST_QSPI_APB … #define JH7110_SYSRST_QSPI_REF … #define JH7110_SYSRST_SDIO0_AHB … #define JH7110_SYSRST_SDIO1_AHB … #define JH7110_SYSRST_GMAC1_AXI … #define JH7110_SYSRST_GMAC1_AHB … #define JH7110_SYSRST_MAILBOX_APB … #define JH7110_SYSRST_SPI0_APB … #define JH7110_SYSRST_SPI1_APB … #define JH7110_SYSRST_SPI2_APB … #define JH7110_SYSRST_SPI3_APB … #define JH7110_SYSRST_SPI4_APB … #define JH7110_SYSRST_SPI5_APB … #define JH7110_SYSRST_SPI6_APB … #define JH7110_SYSRST_I2C0_APB … #define JH7110_SYSRST_I2C1_APB … #define JH7110_SYSRST_I2C2_APB … #define JH7110_SYSRST_I2C3_APB … #define JH7110_SYSRST_I2C4_APB … #define JH7110_SYSRST_I2C5_APB … #define JH7110_SYSRST_I2C6_APB … #define JH7110_SYSRST_UART0_APB … #define JH7110_SYSRST_UART0_CORE … #define JH7110_SYSRST_UART1_APB … #define JH7110_SYSRST_UART1_CORE … #define JH7110_SYSRST_UART2_APB … #define JH7110_SYSRST_UART2_CORE … #define JH7110_SYSRST_UART3_APB … #define JH7110_SYSRST_UART3_CORE … #define JH7110_SYSRST_UART4_APB … #define JH7110_SYSRST_UART4_CORE … #define JH7110_SYSRST_UART5_APB … #define JH7110_SYSRST_UART5_CORE … #define JH7110_SYSRST_SPDIF_APB … #define JH7110_SYSRST_PWMDAC_APB … #define JH7110_SYSRST_PDM_DMIC … #define JH7110_SYSRST_PDM_APB … #define JH7110_SYSRST_I2SRX_APB … #define JH7110_SYSRST_I2SRX_BCLK … #define JH7110_SYSRST_I2STX0_APB … #define JH7110_SYSRST_I2STX0_BCLK … #define JH7110_SYSRST_I2STX1_APB … #define JH7110_SYSRST_I2STX1_BCLK … #define JH7110_SYSRST_TDM_AHB … #define JH7110_SYSRST_TDM_CORE … #define JH7110_SYSRST_TDM_APB … #define JH7110_SYSRST_PWM_APB … #define JH7110_SYSRST_WDT_APB … #define JH7110_SYSRST_WDT_CORE … #define JH7110_SYSRST_CAN0_APB … #define JH7110_SYSRST_CAN0_CORE … #define JH7110_SYSRST_CAN0_TIMER … #define JH7110_SYSRST_CAN1_APB … #define JH7110_SYSRST_CAN1_CORE … #define JH7110_SYSRST_CAN1_TIMER … #define JH7110_SYSRST_TIMER_APB … #define JH7110_SYSRST_TIMER0 … #define JH7110_SYSRST_TIMER1 … #define JH7110_SYSRST_TIMER2 … #define JH7110_SYSRST_TIMER3 … #define JH7110_SYSRST_INT_CTRL_APB … #define JH7110_SYSRST_TEMP_APB … #define JH7110_SYSRST_TEMP_CORE … #define JH7110_SYSRST_JTAG_CERTIFICATION … #define JH7110_SYSRST_END … /* AONCRG resets */ #define JH7110_AONRST_GMAC0_AXI … #define JH7110_AONRST_GMAC0_AHB … #define JH7110_AONRST_IOMUX … #define JH7110_AONRST_PMU_APB … #define JH7110_AONRST_PMU_WKUP … #define JH7110_AONRST_RTC_APB … #define JH7110_AONRST_RTC_CAL … #define JH7110_AONRST_RTC_32K … #define JH7110_AONRST_END … /* STGCRG resets */ #define JH7110_STGRST_SYSCON … #define JH7110_STGRST_HIFI4_CORE … #define JH7110_STGRST_HIFI4_AXI … #define JH7110_STGRST_SEC_AHB … #define JH7110_STGRST_E24_CORE … #define JH7110_STGRST_DMA1P_AXI … #define JH7110_STGRST_DMA1P_AHB … #define JH7110_STGRST_USB0_AXI … #define JH7110_STGRST_USB0_APB … #define JH7110_STGRST_USB0_UTMI_APB … #define JH7110_STGRST_USB0_PWRUP … #define JH7110_STGRST_PCIE0_AXI_MST0 … #define JH7110_STGRST_PCIE0_AXI_SLV0 … #define JH7110_STGRST_PCIE0_AXI_SLV … #define JH7110_STGRST_PCIE0_BRG … #define JH7110_STGRST_PCIE0_CORE … #define JH7110_STGRST_PCIE0_APB … #define JH7110_STGRST_PCIE1_AXI_MST0 … #define JH7110_STGRST_PCIE1_AXI_SLV0 … #define JH7110_STGRST_PCIE1_AXI_SLV … #define JH7110_STGRST_PCIE1_BRG … #define JH7110_STGRST_PCIE1_CORE … #define JH7110_STGRST_PCIE1_APB … #define JH7110_STGRST_END … /* ISPCRG resets */ #define JH7110_ISPRST_ISPV2_TOP_WRAPPER_P … #define JH7110_ISPRST_ISPV2_TOP_WRAPPER_C … #define JH7110_ISPRST_M31DPHY_HW … #define JH7110_ISPRST_M31DPHY_B09_AON … #define JH7110_ISPRST_VIN_APB … #define JH7110_ISPRST_VIN_PIXEL_IF0 … #define JH7110_ISPRST_VIN_PIXEL_IF1 … #define JH7110_ISPRST_VIN_PIXEL_IF2 … #define JH7110_ISPRST_VIN_PIXEL_IF3 … #define JH7110_ISPRST_VIN_SYS … #define JH7110_ISPRST_VIN_P_AXI_RD … #define JH7110_ISPRST_VIN_P_AXI_WR … #define JH7110_ISPRST_END … /* VOUTCRG resets */ #define JH7110_VOUTRST_DC8200_AXI … #define JH7110_VOUTRST_DC8200_AHB … #define JH7110_VOUTRST_DC8200_CORE … #define JH7110_VOUTRST_DSITX_DPI … #define JH7110_VOUTRST_DSITX_APB … #define JH7110_VOUTRST_DSITX_RXESC … #define JH7110_VOUTRST_DSITX_SYS … #define JH7110_VOUTRST_DSITX_TXBYTEHS … #define JH7110_VOUTRST_DSITX_TXESC … #define JH7110_VOUTRST_HDMI_TX_HDMI … #define JH7110_VOUTRST_MIPITX_DPHY_SYS … #define JH7110_VOUTRST_MIPITX_DPHY_TXBYTEHS … #define JH7110_VOUTRST_END … #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */
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