linux/include/dt-bindings/reset/starfive-jh7100.h

/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
 * Copyright (C) 2021 Ahmad Fatoum, Pengutronix
 */

#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7100_H__
#define __DT_BINDINGS_RESET_STARFIVE_JH7100_H__

#define JH7100_RSTN_DOM3AHB_BUS
#define JH7100_RSTN_DOM7AHB_BUS
#define JH7100_RST_U74
#define JH7100_RSTN_U74_AXI
#define JH7100_RSTN_SGDMA2P_AHB
#define JH7100_RSTN_SGDMA2P_AXI
#define JH7100_RSTN_DMA2PNOC_AXI
#define JH7100_RSTN_DLA_AXI
#define JH7100_RSTN_DLANOC_AXI
#define JH7100_RSTN_DLA_APB
#define JH7100_RST_VP6_DRESET
#define JH7100_RST_VP6_BRESET
#define JH7100_RSTN_VP6_AXI
#define JH7100_RSTN_VDECBRG_MAIN
#define JH7100_RSTN_VDEC_AXI
#define JH7100_RSTN_VDEC_BCLK
#define JH7100_RSTN_VDEC_CCLK
#define JH7100_RSTN_VDEC_APB
#define JH7100_RSTN_JPEG_AXI
#define JH7100_RSTN_JPEG_CCLK
#define JH7100_RSTN_JPEG_APB
#define JH7100_RSTN_JPCGC300_MAIN
#define JH7100_RSTN_GC300_2X
#define JH7100_RSTN_GC300_AXI
#define JH7100_RSTN_GC300_AHB
#define JH7100_RSTN_VENC_AXI
#define JH7100_RSTN_VENCBRG_MAIN
#define JH7100_RSTN_VENC_BCLK
#define JH7100_RSTN_VENC_CCLK
#define JH7100_RSTN_VENC_APB
#define JH7100_RSTN_DDRPHY_APB
#define JH7100_RSTN_NOC_ROB
#define JH7100_RSTN_NOC_COG
#define JH7100_RSTN_HIFI4_AXI
#define JH7100_RSTN_HIFI4NOC_AXI
#define JH7100_RST_HIFI4_DRESET
#define JH7100_RST_HIFI4_BRESET
#define JH7100_RSTN_USB_AXI
#define JH7100_RSTN_USBNOC_AXI
#define JH7100_RSTN_SGDMA1P_AXI
#define JH7100_RSTN_DMA1P_AXI
#define JH7100_RSTN_X2C_AXI
#define JH7100_RSTN_NNE_AHB
#define JH7100_RSTN_NNE_AXI
#define JH7100_RSTN_NNENOC_AXI
#define JH7100_RSTN_DLASLV_AXI
#define JH7100_RSTN_DSPX2C_AXI
#define JH7100_RSTN_VIN_SRC
#define JH7100_RSTN_ISPSLV_AXI
#define JH7100_RSTN_VIN_AXI
#define JH7100_RSTN_VINNOC_AXI
#define JH7100_RSTN_ISP0_AXI
#define JH7100_RSTN_ISP0NOC_AXI
#define JH7100_RSTN_ISP1_AXI
#define JH7100_RSTN_ISP1NOC_AXI
#define JH7100_RSTN_VOUT_SRC
#define JH7100_RSTN_DISP_AXI
#define JH7100_RSTN_DISPNOC_AXI
#define JH7100_RSTN_SDIO0_AHB
#define JH7100_RSTN_SDIO1_AHB
#define JH7100_RSTN_GMAC_AHB
#define JH7100_RSTN_SPI2AHB_AHB
#define JH7100_RSTN_SPI2AHB_CORE
#define JH7100_RSTN_EZMASTER_AHB
#define JH7100_RST_E24
#define JH7100_RSTN_QSPI_AHB
#define JH7100_RSTN_QSPI_CORE
#define JH7100_RSTN_QSPI_APB
#define JH7100_RSTN_SEC_AHB
#define JH7100_RSTN_AES
#define JH7100_RSTN_PKA
#define JH7100_RSTN_SHA
#define JH7100_RSTN_TRNG_APB
#define JH7100_RSTN_OTP_APB
#define JH7100_RSTN_UART0_APB
#define JH7100_RSTN_UART0_CORE
#define JH7100_RSTN_UART1_APB
#define JH7100_RSTN_UART1_CORE
#define JH7100_RSTN_SPI0_APB
#define JH7100_RSTN_SPI0_CORE
#define JH7100_RSTN_SPI1_APB
#define JH7100_RSTN_SPI1_CORE
#define JH7100_RSTN_I2C0_APB
#define JH7100_RSTN_I2C0_CORE
#define JH7100_RSTN_I2C1_APB
#define JH7100_RSTN_I2C1_CORE
#define JH7100_RSTN_GPIO_APB
#define JH7100_RSTN_UART2_APB
#define JH7100_RSTN_UART2_CORE
#define JH7100_RSTN_UART3_APB
#define JH7100_RSTN_UART3_CORE
#define JH7100_RSTN_SPI2_APB
#define JH7100_RSTN_SPI2_CORE
#define JH7100_RSTN_SPI3_APB
#define JH7100_RSTN_SPI3_CORE
#define JH7100_RSTN_I2C2_APB
#define JH7100_RSTN_I2C2_CORE
#define JH7100_RSTN_I2C3_APB
#define JH7100_RSTN_I2C3_CORE
#define JH7100_RSTN_WDTIMER_APB
#define JH7100_RSTN_WDT
#define JH7100_RSTN_TIMER0
#define JH7100_RSTN_TIMER1
#define JH7100_RSTN_TIMER2
#define JH7100_RSTN_TIMER3
#define JH7100_RSTN_TIMER4
#define JH7100_RSTN_TIMER5
#define JH7100_RSTN_TIMER6
#define JH7100_RSTN_VP6INTC_APB
#define JH7100_RSTN_PWM_APB
#define JH7100_RSTN_MSI_APB
#define JH7100_RSTN_TEMP_APB
#define JH7100_RSTN_TEMP_SENSE
#define JH7100_RSTN_SYSERR_APB

#define JH7100_RSTN_END

#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7100_H__ */