// SPDX-License-Identifier: GPL-2.0-or-later /* * Reset driver for the StarFive JH7100 SoC * * Copyright (C) 2021 Emil Renner Berthing <[email protected]> */ #include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "reset-starfive-jh71x0.h" #include <dt-bindings/reset/starfive-jh7100.h> /* register offsets */ #define JH7100_RESET_ASSERT0 … #define JH7100_RESET_ASSERT1 … #define JH7100_RESET_ASSERT2 … #define JH7100_RESET_ASSERT3 … #define JH7100_RESET_STATUS0 … #define JH7100_RESET_STATUS1 … #define JH7100_RESET_STATUS2 … #define JH7100_RESET_STATUS3 … /* * Writing a 1 to the n'th bit of the m'th ASSERT register asserts * line 32m + n, and writing a 0 deasserts the same line. * Most reset lines have their status inverted so a 0 bit in the STATUS * register means the line is asserted and a 1 means it's deasserted. A few * lines don't though, so store the expected value of the status registers when * all lines are asserted. */ static const u32 jh7100_reset_asserted[4] = …; static int __init jh7100_reset_probe(struct platform_device *pdev) { … } static const struct of_device_id jh7100_reset_dt_ids[] = …; static struct platform_driver jh7100_reset_driver = …; builtin_platform_driver_probe(…);
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