/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2017 Impinj, Inc. * * Author: Andrey Smirnov <[email protected]> */ #ifndef DT_BINDING_RESET_IMX7_H #define DT_BINDING_RESET_IMX7_H #define IMX7_RESET_A7_CORE_POR_RESET0 … #define IMX7_RESET_A7_CORE_POR_RESET1 … #define IMX7_RESET_A7_CORE_RESET0 … #define IMX7_RESET_A7_CORE_RESET1 … #define IMX7_RESET_A7_DBG_RESET0 … #define IMX7_RESET_A7_DBG_RESET1 … #define IMX7_RESET_A7_ETM_RESET0 … #define IMX7_RESET_A7_ETM_RESET1 … #define IMX7_RESET_A7_SOC_DBG_RESET … #define IMX7_RESET_A7_L2RESET … #define IMX7_RESET_SW_M4C_RST … #define IMX7_RESET_SW_M4P_RST … #define IMX7_RESET_EIM_RST … #define IMX7_RESET_HSICPHY_PORT_RST … #define IMX7_RESET_USBPHY1_POR … #define IMX7_RESET_USBPHY1_PORT_RST … #define IMX7_RESET_USBPHY2_POR … #define IMX7_RESET_USBPHY2_PORT_RST … #define IMX7_RESET_MIPI_PHY_MRST … #define IMX7_RESET_MIPI_PHY_SRST … /* * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN * and PCIEPHY_G_RST */ #define IMX7_RESET_PCIEPHY … #define IMX7_RESET_PCIEPHY_PERST … /* * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht * of as one */ #define IMX7_RESET_PCIE_CTRL_APPS_EN … #define IMX7_RESET_DDRC_PRST … #define IMX7_RESET_DDRC_CORE_RST … #define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF … #define IMX7_RESET_NUM … #endif
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