linux/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

/*
 * Copyright 2023 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include <linux/list.h>
#include "amdgpu.h"
#include "amdgpu_aca.h"
#include "amdgpu_ras.h"

#define ACA_BANK_HWID(type, hwid, mcatype)

bank_handler_t;

struct aca_banks {};

struct aca_hwip {};

static struct aca_hwip aca_hwid_mcatypes[ACA_HWIP_TYPE_COUNT] =;

static void aca_banks_init(struct aca_banks *banks)
{}

static int aca_banks_add_bank(struct aca_banks *banks, struct aca_bank *bank)
{}

static void aca_banks_release(struct aca_banks *banks)
{}

static int aca_smu_get_valid_aca_count(struct amdgpu_device *adev, enum aca_smu_type type, u32 *count)
{}

static struct aca_regs_dump {} aca_regs[] =;

static void aca_smu_bank_dump(struct amdgpu_device *adev, int idx, int total, struct aca_bank *bank,
			      struct ras_query_context *qctx)
{}

static int aca_smu_get_valid_aca_banks(struct amdgpu_device *adev, enum aca_smu_type type,
				       int start, int count,
				       struct aca_banks *banks, struct ras_query_context *qctx)
{}

static bool aca_bank_hwip_is_matched(struct aca_bank *bank, enum aca_hwip_type type)
{}

static bool aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type)
{}

static struct aca_bank_error *new_bank_error(struct aca_error *aerr, struct aca_bank_info *info)
{}

static struct aca_bank_error *find_bank_error(struct aca_error *aerr, struct aca_bank_info *info)
{}

static void aca_bank_error_remove(struct aca_error *aerr, struct aca_bank_error *bank_error)
{}

static struct aca_bank_error *get_bank_error(struct aca_error *aerr, struct aca_bank_info *info)
{}

int aca_error_cache_log_bank_error(struct aca_handle *handle, struct aca_bank_info *info,
				   enum aca_error_type type, u64 count)
{}

static int aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type)
{}

static int handler_aca_log_bank_error(struct aca_handle *handle, struct aca_bank *bank,
				      enum aca_smu_type type, void *data)
{}

static int aca_dispatch_bank(struct aca_handle_manager *mgr, struct aca_bank *bank,
			     enum aca_smu_type type, bank_handler_t handler, void *data)
{}

static int aca_dispatch_banks(struct aca_handle_manager *mgr, struct aca_banks *banks,
			      enum aca_smu_type type, bank_handler_t handler, void *data)
{}

static bool aca_bank_should_update(struct amdgpu_device *adev, enum aca_smu_type type)
{}

static int aca_banks_update(struct amdgpu_device *adev, enum aca_smu_type type,
			    bank_handler_t handler, struct ras_query_context *qctx, void *data)
{}

static int aca_log_aca_error_data(struct aca_bank_error *bank_error, enum aca_error_type type, struct ras_err_data *err_data)
{}

static int aca_log_aca_error(struct aca_handle *handle, enum aca_error_type type, struct ras_err_data *err_data)
{}

static int __aca_get_error_data(struct amdgpu_device *adev, struct aca_handle *handle, enum aca_error_type type,
				struct ras_err_data *err_data, struct ras_query_context *qctx)
{}

static bool aca_handle_is_valid(struct aca_handle *handle)
{}

int amdgpu_aca_get_error_data(struct amdgpu_device *adev, struct aca_handle *handle,
			      enum aca_error_type type, struct ras_err_data *err_data,
			      struct ras_query_context *qctx)
{}

static void aca_error_init(struct aca_error *aerr, enum aca_error_type type)
{}

static void aca_init_error_cache(struct aca_handle *handle)
{}

static void aca_error_fini(struct aca_error *aerr)
{}

static void aca_fini_error_cache(struct aca_handle *handle)
{}

static int add_aca_handle(struct amdgpu_device *adev, struct aca_handle_manager *mgr, struct aca_handle *handle,
			  const char *name, const struct aca_info *ras_info, void *data)
{}

static ssize_t aca_sysfs_read(struct device *dev,
			      struct device_attribute *attr, char *buf)
{}

static int add_aca_sysfs(struct amdgpu_device *adev, struct aca_handle *handle)
{}

int amdgpu_aca_add_handle(struct amdgpu_device *adev, struct aca_handle *handle,
			  const char *name, const struct aca_info *ras_info, void *data)
{}

static void remove_aca_handle(struct aca_handle *handle)
{}

static void remove_aca_sysfs(struct aca_handle *handle)
{}

void amdgpu_aca_remove_handle(struct aca_handle *handle)
{}

static int aca_manager_init(struct aca_handle_manager *mgr)
{}

static void aca_manager_fini(struct aca_handle_manager *mgr)
{}

bool amdgpu_aca_is_enabled(struct amdgpu_device *adev)
{}

int amdgpu_aca_init(struct amdgpu_device *adev)
{}

void amdgpu_aca_fini(struct amdgpu_device *adev)
{}

int amdgpu_aca_reset(struct amdgpu_device *adev)
{}

void amdgpu_aca_set_smu_funcs(struct amdgpu_device *adev, const struct aca_smu_funcs *smu_funcs)
{}

int aca_bank_info_decode(struct aca_bank *bank, struct aca_bank_info *info)
{}

static int aca_bank_get_error_code(struct amdgpu_device *adev, struct aca_bank *bank)
{}

int aca_bank_check_error_codes(struct amdgpu_device *adev, struct aca_bank *bank, int *err_codes, int size)
{}

int amdgpu_aca_smu_set_debug_mode(struct amdgpu_device *adev, bool en)
{}

#if defined(CONFIG_DEBUG_FS)
static int amdgpu_aca_smu_debug_mode_set(void *data, u64 val)
{}

static void aca_dump_entry(struct seq_file *m, struct aca_bank *bank, enum aca_smu_type type, int idx)
{}

struct aca_dump_context {};

static int handler_aca_bank_dump(struct aca_handle *handle, struct aca_bank *bank,
				 enum aca_smu_type type, void *data)
{}

static int aca_dump_show(struct seq_file *m, enum aca_smu_type type)
{}

static int aca_dump_ce_show(struct seq_file *m, void *unused)
{}

static int aca_dump_ce_open(struct inode *inode, struct file *file)
{}

static const struct file_operations aca_ce_dump_debug_fops =;

static int aca_dump_ue_show(struct seq_file *m, void *unused)
{}

static int aca_dump_ue_open(struct inode *inode, struct file *file)
{}

static const struct file_operations aca_ue_dump_debug_fops =;

DEFINE_DEBUGFS_ATTRIBUTE();
#endif

void amdgpu_aca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root)
{}