// SPDX-License-Identifier: GPL-2.0+ /* * *************************************************************************** * Marvell Armada-3700 Serial Driver * Author: Wilson Ding <[email protected]> * Copyright (C) 2015 Marvell International Ltd. * *************************************************************************** */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/console.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/init.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/math64.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_device.h> #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/serial.h> #include <linux/serial_core.h> #include <linux/slab.h> #include <linux/tty.h> #include <linux/tty_flip.h> /* Register Map */ #define UART_STD_RBR … #define UART_EXT_RBR … #define UART_STD_TSH … #define UART_EXT_TSH … #define UART_STD_CTRL1 … #define UART_EXT_CTRL1 … #define CTRL_SOFT_RST … #define CTRL_TXFIFO_RST … #define CTRL_RXFIFO_RST … #define CTRL_SND_BRK_SEQ … #define CTRL_BRK_DET_INT … #define CTRL_FRM_ERR_INT … #define CTRL_PAR_ERR_INT … #define CTRL_OVR_ERR_INT … #define CTRL_BRK_INT … #define UART_STD_CTRL2 … #define UART_EXT_CTRL2 … #define CTRL_STD_TX_RDY_INT … #define CTRL_EXT_TX_RDY_INT … #define CTRL_STD_RX_RDY_INT … #define CTRL_EXT_RX_RDY_INT … #define UART_STAT … #define STAT_TX_FIFO_EMP … #define STAT_TX_FIFO_FUL … #define STAT_TX_EMP … #define STAT_STD_TX_RDY … #define STAT_EXT_TX_RDY … #define STAT_STD_RX_RDY … #define STAT_EXT_RX_RDY … #define STAT_BRK_DET … #define STAT_FRM_ERR … #define STAT_PAR_ERR … #define STAT_OVR_ERR … #define STAT_BRK_ERR … /* * Marvell Armada 3700 Functional Specifications describes that bit 21 of UART * Clock Control register controls UART1 and bit 20 controls UART2. But in * reality bit 21 controls UART2 and bit 20 controls UART1. This seems to be an * error in Marvell's documentation. Hence following CLK_DIS macros are swapped. */ #define UART_BRDV … /* These bits are located in UART1 address space and control UART2 */ #define UART2_CLK_DIS … /* These bits are located in UART1 address space and control UART1 */ #define UART1_CLK_DIS … /* These bits are located in UART1 address space and control both UARTs */ #define CLK_NO_XTAL … #define CLK_TBG_DIV1_SHIFT … #define CLK_TBG_DIV1_MASK … #define CLK_TBG_DIV1_MAX … #define CLK_TBG_DIV2_SHIFT … #define CLK_TBG_DIV2_MASK … #define CLK_TBG_DIV2_MAX … #define CLK_TBG_SEL_SHIFT … #define CLK_TBG_SEL_MASK … /* These bits are located in both UARTs address space */ #define BRDV_BAUD_MASK … #define BRDV_BAUD_MAX … #define UART_OSAMP … #define OSAMP_DEFAULT_DIVISOR … #define OSAMP_DIVISORS_MASK … #define OSAMP_MAX_DIVISOR … #define MVEBU_NR_UARTS … #define MVEBU_UART_TYPE … #define DRIVER_NAME … enum { … }; /* Diverging register offsets */ struct uart_regs_layout { … }; /* Diverging flags */ struct uart_flags { … }; /* Driver data, a structure for each UART port */ struct mvebu_uart_driver_data { … }; /* Saved registers during suspend */ struct mvebu_uart_pm_regs { … }; /* MVEBU UART driver structure */ struct mvebu_uart { … }; static struct mvebu_uart *to_mvuart(struct uart_port *port) { … } #define IS_EXTENDED(port) … #define UART_RBR(port) … #define UART_TSH(port) … #define UART_CTRL(port) … #define UART_INTR(port) … #define CTRL_TX_RDY_INT(port) … #define CTRL_RX_RDY_INT(port) … #define STAT_TX_RDY(port) … #define STAT_RX_RDY(port) … static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS]; static DEFINE_SPINLOCK(mvebu_uart_lock); /* Core UART Driver Operations */ static unsigned int mvebu_uart_tx_empty(struct uart_port *port) { … } static unsigned int mvebu_uart_get_mctrl(struct uart_port *port) { … } static void mvebu_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) { … } static void mvebu_uart_stop_tx(struct uart_port *port) { … } static void mvebu_uart_start_tx(struct uart_port *port) { … } static void mvebu_uart_stop_rx(struct uart_port *port) { … } static void mvebu_uart_break_ctl(struct uart_port *port, int brk) { … } static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status) { … } static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status) { … } static irqreturn_t mvebu_uart_isr(int irq, void *dev_id) { … } static irqreturn_t mvebu_uart_rx_isr(int irq, void *dev_id) { … } static irqreturn_t mvebu_uart_tx_isr(int irq, void *dev_id) { … } static int mvebu_uart_startup(struct uart_port *port) { … } static void mvebu_uart_shutdown(struct uart_port *port) { … } static unsigned int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud) { … } static void mvebu_uart_set_termios(struct uart_port *port, struct ktermios *termios, const struct ktermios *old) { … } static const char *mvebu_uart_type(struct uart_port *port) { … } static void mvebu_uart_release_port(struct uart_port *port) { … } static int mvebu_uart_request_port(struct uart_port *port) { … } #ifdef CONFIG_CONSOLE_POLL static int mvebu_uart_get_poll_char(struct uart_port *port) { … } static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c) { … } #endif static const struct uart_ops mvebu_uart_ops = …; /* Console Driver Operations */ #ifdef CONFIG_SERIAL_MVEBU_CONSOLE /* Early Console */ static void mvebu_uart_putc(struct uart_port *port, unsigned char c) { … } static void mvebu_uart_putc_early_write(struct console *con, const char *s, unsigned int n) { … } static int __init mvebu_uart_early_console_setup(struct earlycon_device *device, const char *opt) { … } EARLYCON_DECLARE(…); OF_EARLYCON_DECLARE(…); static void wait_for_xmitr(struct uart_port *port) { … } static void wait_for_xmite(struct uart_port *port) { … } static void mvebu_uart_console_putchar(struct uart_port *port, unsigned char ch) { … } static void mvebu_uart_console_write(struct console *co, const char *s, unsigned int count) { … } static int mvebu_uart_console_setup(struct console *co, char *options) { … } static struct uart_driver mvebu_uart_driver; static struct console mvebu_uart_console = …; static int __init mvebu_uart_console_init(void) { … } console_initcall(mvebu_uart_console_init); #endif /* CONFIG_SERIAL_MVEBU_CONSOLE */ static struct uart_driver mvebu_uart_driver = …; #if defined(CONFIG_PM) static int mvebu_uart_suspend(struct device *dev) { … } static int mvebu_uart_resume(struct device *dev) { … } static const struct dev_pm_ops mvebu_uart_pm_ops = …; #endif /* CONFIG_PM */ static const struct of_device_id mvebu_uart_of_match[]; /* Counter to keep track of each UART port id when not using CONFIG_OF */ static int uart_num_counter; static int mvebu_uart_probe(struct platform_device *pdev) { … } static struct mvebu_uart_driver_data uart_std_driver_data = …; static struct mvebu_uart_driver_data uart_ext_driver_data = …; /* Match table for of_platform binding */ static const struct of_device_id mvebu_uart_of_match[] = …; static struct platform_driver mvebu_uart_platform_driver = …; /* This code is based on clk-fixed-factor.c driver and modified. */ struct mvebu_uart_clock { … }; struct mvebu_uart_clock_base { … }; #define PARENT_CLOCK_XTAL … #define to_uart_clock(hw) … #define to_uart_clock_base(uart_clock) … static int mvebu_uart_clock_prepare(struct clk_hw *hw) { … } static int mvebu_uart_clock_enable(struct clk_hw *hw) { … } static void mvebu_uart_clock_disable(struct clk_hw *hw) { … } static int mvebu_uart_clock_is_enabled(struct clk_hw *hw) { … } static int mvebu_uart_clock_save_context(struct clk_hw *hw) { … } static void mvebu_uart_clock_restore_context(struct clk_hw *hw) { … } static unsigned long mvebu_uart_clock_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long mvebu_uart_clock_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { … } static int mvebu_uart_clock_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static const struct clk_ops mvebu_uart_clock_ops = …; static int mvebu_uart_clock_register(struct device *dev, struct mvebu_uart_clock *uart_clock, const char *name, const char *parent_name) { … } static int mvebu_uart_clock_probe(struct platform_device *pdev) { … } static const struct of_device_id mvebu_uart_clock_of_match[] = …; static struct platform_driver mvebu_uart_clock_platform_driver = …; static int __init mvebu_uart_init(void) { … } arch_initcall(mvebu_uart_init);
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