/* SPDX-License-Identifier: GPL-2.0-only */ /* * IOMMU API for ARM architected SMMU implementations. * * Copyright (C) 2013 ARM Limited * * Author: Will Deacon <[email protected]> */ #ifndef _ARM_SMMU_H #define _ARM_SMMU_H #include <linux/atomic.h> #include <linux/bitfield.h> #include <linux/bits.h> #include <linux/clk.h> #include <linux/device.h> #include <linux/io-64-nonatomic-hi-lo.h> #include <linux/io-pgtable.h> #include <linux/iommu.h> #include <linux/irqreturn.h> #include <linux/mutex.h> #include <linux/spinlock.h> #include <linux/types.h> /* Configuration registers */ #define ARM_SMMU_GR0_sCR0 … #define ARM_SMMU_sCR0_VMID16EN … #define ARM_SMMU_sCR0_BSU … #define ARM_SMMU_sCR0_FB … #define ARM_SMMU_sCR0_PTM … #define ARM_SMMU_sCR0_VMIDPNE … #define ARM_SMMU_sCR0_USFCFG … #define ARM_SMMU_sCR0_GCFGFIE … #define ARM_SMMU_sCR0_GCFGFRE … #define ARM_SMMU_sCR0_EXIDENABLE … #define ARM_SMMU_sCR0_GFIE … #define ARM_SMMU_sCR0_GFRE … #define ARM_SMMU_sCR0_CLIENTPD … /* Auxiliary Configuration register */ #define ARM_SMMU_GR0_sACR … /* Identification registers */ #define ARM_SMMU_GR0_ID0 … #define ARM_SMMU_ID0_S1TS … #define ARM_SMMU_ID0_S2TS … #define ARM_SMMU_ID0_NTS … #define ARM_SMMU_ID0_SMS … #define ARM_SMMU_ID0_ATOSNS … #define ARM_SMMU_ID0_PTFS_NO_AARCH32 … #define ARM_SMMU_ID0_PTFS_NO_AARCH32S … #define ARM_SMMU_ID0_NUMIRPT … #define ARM_SMMU_ID0_CTTW … #define ARM_SMMU_ID0_NUMSIDB … #define ARM_SMMU_ID0_EXIDS … #define ARM_SMMU_ID0_NUMSMRG … #define ARM_SMMU_GR0_ID1 … #define ARM_SMMU_ID1_PAGESIZE … #define ARM_SMMU_ID1_NUMPAGENDXB … #define ARM_SMMU_ID1_NUMS2CB … #define ARM_SMMU_ID1_NUMCB … #define ARM_SMMU_GR0_ID2 … #define ARM_SMMU_ID2_VMID16 … #define ARM_SMMU_ID2_PTFS_64K … #define ARM_SMMU_ID2_PTFS_16K … #define ARM_SMMU_ID2_PTFS_4K … #define ARM_SMMU_ID2_UBS … #define ARM_SMMU_ID2_OAS … #define ARM_SMMU_ID2_IAS … #define ARM_SMMU_GR0_ID3 … #define ARM_SMMU_GR0_ID4 … #define ARM_SMMU_GR0_ID5 … #define ARM_SMMU_GR0_ID6 … #define ARM_SMMU_GR0_ID7 … #define ARM_SMMU_ID7_MAJOR … #define ARM_SMMU_ID7_MINOR … #define ARM_SMMU_GR0_sGFSR … #define ARM_SMMU_sGFSR_USF … #define ARM_SMMU_GR0_sGFSYNR0 … #define ARM_SMMU_GR0_sGFSYNR1 … #define ARM_SMMU_GR0_sGFSYNR2 … /* Global TLB invalidation */ #define ARM_SMMU_GR0_TLBIVMID … #define ARM_SMMU_GR0_TLBIALLNSNH … #define ARM_SMMU_GR0_TLBIALLH … #define ARM_SMMU_GR0_sTLBGSYNC … #define ARM_SMMU_GR0_sTLBGSTATUS … #define ARM_SMMU_sTLBGSTATUS_GSACTIVE … /* Stream mapping registers */ #define ARM_SMMU_GR0_SMR(n) … #define ARM_SMMU_SMR_VALID … #define ARM_SMMU_SMR_MASK … #define ARM_SMMU_SMR_ID … #define ARM_SMMU_GR0_S2CR(n) … #define ARM_SMMU_S2CR_PRIVCFG … enum arm_smmu_s2cr_privcfg { … }; #define ARM_SMMU_S2CR_TYPE … enum arm_smmu_s2cr_type { … }; #define ARM_SMMU_S2CR_EXIDVALID … #define ARM_SMMU_S2CR_CBNDX … /* Context bank attribute registers */ #define ARM_SMMU_GR1_CBAR(n) … #define ARM_SMMU_CBAR_IRPTNDX … #define ARM_SMMU_CBAR_TYPE … enum arm_smmu_cbar_type { … }; #define ARM_SMMU_CBAR_S1_MEMATTR … #define ARM_SMMU_CBAR_S1_MEMATTR_WB … #define ARM_SMMU_CBAR_S1_BPSHCFG … #define ARM_SMMU_CBAR_S1_BPSHCFG_NSH … #define ARM_SMMU_CBAR_VMID … #define ARM_SMMU_GR1_CBFRSYNRA(n) … #define ARM_SMMU_CBFRSYNRA_SID … #define ARM_SMMU_GR1_CBA2R(n) … #define ARM_SMMU_CBA2R_VMID16 … #define ARM_SMMU_CBA2R_VA64 … #define ARM_SMMU_CB_SCTLR … #define ARM_SMMU_SCTLR_S1_ASIDPNE … #define ARM_SMMU_SCTLR_CFCFG … #define ARM_SMMU_SCTLR_HUPCF … #define ARM_SMMU_SCTLR_CFIE … #define ARM_SMMU_SCTLR_CFRE … #define ARM_SMMU_SCTLR_E … #define ARM_SMMU_SCTLR_AFE … #define ARM_SMMU_SCTLR_TRE … #define ARM_SMMU_SCTLR_M … #define ARM_SMMU_CB_ACTLR … #define ARM_SMMU_CB_RESUME … #define ARM_SMMU_RESUME_TERMINATE … #define ARM_SMMU_CB_TCR2 … #define ARM_SMMU_TCR2_SEP … #define ARM_SMMU_TCR2_SEP_UPSTREAM … #define ARM_SMMU_TCR2_AS … #define ARM_SMMU_TCR2_PASIZE … #define ARM_SMMU_CB_TTBR0 … #define ARM_SMMU_CB_TTBR1 … #define ARM_SMMU_TTBRn_ASID … #define ARM_SMMU_CB_TCR … #define ARM_SMMU_TCR_EAE … #define ARM_SMMU_TCR_EPD1 … #define ARM_SMMU_TCR_A1 … #define ARM_SMMU_TCR_TG0 … #define ARM_SMMU_TCR_SH0 … #define ARM_SMMU_TCR_ORGN0 … #define ARM_SMMU_TCR_IRGN0 … #define ARM_SMMU_TCR_EPD0 … #define ARM_SMMU_TCR_T0SZ … #define ARM_SMMU_VTCR_RES1 … #define ARM_SMMU_VTCR_PS … #define ARM_SMMU_VTCR_TG0 … #define ARM_SMMU_VTCR_SH0 … #define ARM_SMMU_VTCR_ORGN0 … #define ARM_SMMU_VTCR_IRGN0 … #define ARM_SMMU_VTCR_SL0 … #define ARM_SMMU_VTCR_T0SZ … #define ARM_SMMU_CB_CONTEXTIDR … #define ARM_SMMU_CB_S1_MAIR0 … #define ARM_SMMU_CB_S1_MAIR1 … #define ARM_SMMU_CB_PAR … #define ARM_SMMU_CB_PAR_F … #define ARM_SMMU_CB_FSR … #define ARM_SMMU_CB_FSR_MULTI … #define ARM_SMMU_CB_FSR_SS … #define ARM_SMMU_CB_FSR_FORMAT … #define ARM_SMMU_CB_FSR_UUT … #define ARM_SMMU_CB_FSR_ASF … #define ARM_SMMU_CB_FSR_TLBLKF … #define ARM_SMMU_CB_FSR_TLBMCF … #define ARM_SMMU_CB_FSR_EF … #define ARM_SMMU_CB_FSR_PF … #define ARM_SMMU_CB_FSR_AFF … #define ARM_SMMU_CB_FSR_TF … #define ARM_SMMU_CB_FSR_IGN … #define ARM_SMMU_CB_FSR_FAULT … #define ARM_SMMU_CB_FAR … #define ARM_SMMU_CB_FSYNR0 … #define ARM_SMMU_CB_FSYNR0_PLVL … #define ARM_SMMU_CB_FSYNR0_WNR … #define ARM_SMMU_CB_FSYNR0_PNU … #define ARM_SMMU_CB_FSYNR0_IND … #define ARM_SMMU_CB_FSYNR0_NSATTR … #define ARM_SMMU_CB_FSYNR0_PTWF … #define ARM_SMMU_CB_FSYNR0_AFR … #define ARM_SMMU_CB_FSYNR0_S1CBNDX … #define ARM_SMMU_CB_FSYNR1 … #define ARM_SMMU_CB_S1_TLBIVA … #define ARM_SMMU_CB_S1_TLBIASID … #define ARM_SMMU_CB_S1_TLBIVAL … #define ARM_SMMU_CB_S2_TLBIIPAS2 … #define ARM_SMMU_CB_S2_TLBIIPAS2L … #define ARM_SMMU_CB_TLBSYNC … #define ARM_SMMU_CB_TLBSTATUS … #define ARM_SMMU_CB_ATS1PR … #define ARM_SMMU_CB_ATSR … #define ARM_SMMU_CB_ATSR_ACTIVE … #define ARM_SMMU_RESUME_TERMINATE … /* Maximum number of context banks per SMMU */ #define ARM_SMMU_MAX_CBS … #define TLB_LOOP_TIMEOUT … #define TLB_SPIN_COUNT … /* Shared driver definitions */ enum arm_smmu_arch_version { … }; enum arm_smmu_implementation { … }; struct arm_smmu_s2cr { … }; struct arm_smmu_smr { … }; struct arm_smmu_device { … }; enum arm_smmu_context_fmt { … }; struct arm_smmu_cfg { … }; #define ARM_SMMU_INVALID_IRPTNDX … struct arm_smmu_cb { … }; enum arm_smmu_domain_stage { … }; struct arm_smmu_domain { … }; struct arm_smmu_master_cfg { … }; static inline u32 arm_smmu_lpae_tcr(const struct io_pgtable_cfg *cfg) { … } static inline u32 arm_smmu_lpae_tcr2(const struct io_pgtable_cfg *cfg) { … } static inline u32 arm_smmu_lpae_vtcr(const struct io_pgtable_cfg *cfg) { … } /* Implementation details, yay! */ struct arm_smmu_impl { … }; #define INVALID_SMENDX … #define cfg_smendx(cfg, fw, i) … #define for_each_cfg_sme(cfg, fw, i, idx) … static inline int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end) { … } static inline void __iomem *arm_smmu_page(struct arm_smmu_device *smmu, int n) { … } static inline u32 arm_smmu_readl(struct arm_smmu_device *smmu, int page, int offset) { … } static inline void arm_smmu_writel(struct arm_smmu_device *smmu, int page, int offset, u32 val) { … } static inline u64 arm_smmu_readq(struct arm_smmu_device *smmu, int page, int offset) { … } static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page, int offset, u64 val) { … } #define ARM_SMMU_GR0 … #define ARM_SMMU_GR1 … #define ARM_SMMU_CB(s, n) … #define arm_smmu_gr0_read(s, o) … #define arm_smmu_gr0_write(s, o, v) … #define arm_smmu_gr1_read(s, o) … #define arm_smmu_gr1_write(s, o, v) … #define arm_smmu_cb_read(s, n, o) … #define arm_smmu_cb_write(s, n, o, v) … #define arm_smmu_cb_readq(s, n, o) … #define arm_smmu_cb_writeq(s, n, o, v) … struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu); struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu); struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu); void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx); int arm_mmu500_reset(struct arm_smmu_device *smmu); struct arm_smmu_context_fault_info { … }; void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx, struct arm_smmu_context_fault_info *cfi); void arm_smmu_print_context_fault_info(struct arm_smmu_device *smmu, int idx, const struct arm_smmu_context_fault_info *cfi); #endif /* _ARM_SMMU_H */
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