/* SPDX-License-Identifier: GPL-2.0-only */ /* * omap iommu: main structures * * Copyright (C) 2008-2009 Nokia Corporation * * Written by Hiroshi DOYU <[email protected]> */ #ifndef _OMAP_IOMMU_H #define _OMAP_IOMMU_H #include <linux/bitops.h> #include <linux/iommu.h> #define for_each_iotlb_cr(obj, n, __i, cr) … struct iotlb_entry { … }; /** * struct omap_iommu_device - omap iommu device data * @pgtable: page table used by an omap iommu attached to a domain * @iommu_dev: pointer to store an omap iommu instance attached to a domain */ struct omap_iommu_device { … }; /** * struct omap_iommu_domain - omap iommu domain * @num_iommus: number of iommus in this domain * @iommus: omap iommu device data for all iommus in this domain * @dev: Device using this domain. * @lock: domain lock, should be taken when attaching/detaching * @domain: generic domain handle used by iommu core code */ struct omap_iommu_domain { … }; struct omap_iommu { … }; /** * struct omap_iommu_arch_data - omap iommu private data * @iommu_dev: handle of the OMAP iommu device * @dev: handle of the iommu device * * This is an omap iommu private data object, which binds an iommu user * to its iommu device. This object should be placed at the iommu user's * dev_archdata so generic IOMMU API can be used without having to * utilize omap-specific plumbing anymore. */ struct omap_iommu_arch_data { … }; struct cr_regs { … }; struct iotlb_lock { … }; /* * MMU Register offsets */ #define MMU_REVISION … #define MMU_IRQSTATUS … #define MMU_IRQENABLE … #define MMU_WALKING_ST … #define MMU_CNTL … #define MMU_FAULT_AD … #define MMU_TTB … #define MMU_LOCK … #define MMU_LD_TLB … #define MMU_CAM … #define MMU_RAM … #define MMU_GFLUSH … #define MMU_FLUSH_ENTRY … #define MMU_READ_CAM … #define MMU_READ_RAM … #define MMU_EMU_FAULT_AD … #define MMU_GP_REG … #define MMU_REG_SIZE … /* * MMU Register bit definitions */ /* IRQSTATUS & IRQENABLE */ #define MMU_IRQ_MULTIHITFAULT … #define MMU_IRQ_TABLEWALKFAULT … #define MMU_IRQ_EMUMISS … #define MMU_IRQ_TRANSLATIONFAULT … #define MMU_IRQ_TLBMISS … #define __MMU_IRQ_FAULT … #define MMU_IRQ_MASK … #define MMU_IRQ_TWL_MASK … #define MMU_IRQ_TLB_MISS_MASK … /* MMU_CNTL */ #define MMU_CNTL_SHIFT … #define MMU_CNTL_MASK … #define MMU_CNTL_EML_TLB … #define MMU_CNTL_TWL_EN … #define MMU_CNTL_MMU_EN … /* CAM */ #define MMU_CAM_VATAG_SHIFT … #define MMU_CAM_VATAG_MASK … #define MMU_CAM_P … #define MMU_CAM_V … #define MMU_CAM_PGSZ_MASK … #define MMU_CAM_PGSZ_1M … #define MMU_CAM_PGSZ_64K … #define MMU_CAM_PGSZ_4K … #define MMU_CAM_PGSZ_16M … /* RAM */ #define MMU_RAM_PADDR_SHIFT … #define MMU_RAM_PADDR_MASK … #define MMU_RAM_ENDIAN_SHIFT … #define MMU_RAM_ENDIAN_MASK … #define MMU_RAM_ENDIAN_LITTLE … #define MMU_RAM_ENDIAN_BIG … #define MMU_RAM_ELSZ_SHIFT … #define MMU_RAM_ELSZ_MASK … #define MMU_RAM_ELSZ_8 … #define MMU_RAM_ELSZ_16 … #define MMU_RAM_ELSZ_32 … #define MMU_RAM_ELSZ_NONE … #define MMU_RAM_MIXED_SHIFT … #define MMU_RAM_MIXED_MASK … #define MMU_RAM_MIXED … #define MMU_GP_REG_BUS_ERR_BACK_EN … #define get_cam_va_mask(pgsz) … /* * DSP_SYSTEM registers and bit definitions (applicable only for DRA7xx DSP) */ #define DSP_SYS_REVISION … #define DSP_SYS_MMU_CONFIG … #define DSP_SYS_MMU_CONFIG_EN_SHIFT … /* * utilities for super page(16MB, 1MB, 64KB and 4KB) */ #define iopgsz_max(bytes) … #define bytes_to_iopgsz(bytes) … #define iopgsz_to_bytes(iopgsz) … #define iopgsz_ok(bytes) … /* * global functions */ struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n); void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l); void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l); #ifdef CONFIG_OMAP_IOMMU_DEBUG void omap_iommu_debugfs_init(void); void omap_iommu_debugfs_exit(void); void omap_iommu_debugfs_add(struct omap_iommu *obj); void omap_iommu_debugfs_remove(struct omap_iommu *obj); #else static inline void omap_iommu_debugfs_init(void) { } static inline void omap_iommu_debugfs_exit(void) { } static inline void omap_iommu_debugfs_add(struct omap_iommu *obj) { } static inline void omap_iommu_debugfs_remove(struct omap_iommu *obj) { } #endif /* * register accessors */ static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs) { … } static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs) { … } static inline int iotlb_cr_valid(struct cr_regs *cr) { … } #endif /* _OMAP_IOMMU_H */
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