linux/drivers/gpu/host1x/dev.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Tegra host1x driver
 *
 * Copyright (c) 2010-2013, NVIDIA Corporation.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>

#include <soc/tegra/common.h>

#define CREATE_TRACE_POINTS
#include <trace/events/host1x.h>
#undef CREATE_TRACE_POINTS

#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
#include <asm/dma-iommu.h>
#endif

#include "bus.h"
#include "channel.h"
#include "context.h"
#include "debug.h"
#include "dev.h"
#include "intr.h"

#include "hw/host1x01.h"
#include "hw/host1x02.h"
#include "hw/host1x04.h"
#include "hw/host1x05.h"
#include "hw/host1x06.h"
#include "hw/host1x07.h"
#include "hw/host1x08.h"

void host1x_common_writel(struct host1x *host1x, u32 v, u32 r)
{ … }

void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)
{ … }

u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r)
{ … }

void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
{ … }

u32 host1x_sync_readl(struct host1x *host1x, u32 r)
{ … }

void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
{ … }

u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
{ … }

static const struct host1x_info host1x01_info = …;

static const struct host1x_info host1x02_info = …;

static const struct host1x_info host1x04_info = …;

static const struct host1x_info host1x05_info = …;

static const struct host1x_sid_entry tegra186_sid_table[] = …;

static const struct host1x_info host1x06_info = …;

static const struct host1x_sid_entry tegra194_sid_table[] = …;

static const struct host1x_info host1x07_info = …;

/*
 * Tegra234 has two stream ID protection tables, one for setting stream IDs
 * through the channel path via SETSTREAMID, and one for setting them via
 * MMIO. We program each engine's data stream ID in the channel path table
 * and firmware stream ID in the MMIO path table.
 */
static const struct host1x_sid_entry tegra234_sid_table[] = …;

static const struct host1x_info host1x08_info = …;

static const struct of_device_id host1x_of_match[] = …;
MODULE_DEVICE_TABLE(of, host1x_of_match);

static void host1x_setup_virtualization_tables(struct host1x *host)
{ … }

static bool host1x_wants_iommu(struct host1x *host1x)
{ … }

static struct iommu_domain *host1x_iommu_attach(struct host1x *host)
{ … }

static int host1x_iommu_init(struct host1x *host)
{ … }

static void host1x_iommu_exit(struct host1x *host)
{ … }

static int host1x_get_resets(struct host1x *host)
{ … }

static int host1x_probe(struct platform_device *pdev)
{ … }

static void host1x_remove(struct platform_device *pdev)
{ … }

static int __maybe_unused host1x_runtime_suspend(struct device *dev)
{ … }

static int __maybe_unused host1x_runtime_resume(struct device *dev)
{ … }

static const struct dev_pm_ops host1x_pm_ops = …;

static struct platform_driver tegra_host1x_driver = …;

static struct platform_driver * const drivers[] = …;

static int __init tegra_host1x_init(void)
{ … }
module_init(…) …;

static void __exit tegra_host1x_exit(void)
{ … }
module_exit(tegra_host1x_exit);

/**
 * host1x_get_dma_mask() - query the supported DMA mask for host1x
 * @host1x: host1x instance
 *
 * Note that this returns the supported DMA mask for host1x, which can be
 * different from the applicable DMA mask under certain circumstances.
 */
u64 host1x_get_dma_mask(struct host1x *host1x)
{ … }
EXPORT_SYMBOL(…);

MODULE_AUTHOR(…) …;
MODULE_AUTHOR(…) …;
MODULE_DESCRIPTION(…) …;
MODULE_LICENSE(…) …;