linux/drivers/gpu/host1x/hw/opcodes.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Tegra host1x opcodes
 *
 * Copyright (c) 2022 NVIDIA Corporation.
 */

#ifndef __HOST1X_OPCODES_H
#define __HOST1X_OPCODES_H

#include <linux/types.h>

static inline u32 host1x_class_host_wait_syncpt(
	unsigned indx, unsigned threshold)
{ … }

static inline u32 host1x_class_host_load_syncpt_base(
	unsigned indx, unsigned threshold)
{ … }

static inline u32 host1x_class_host_wait_syncpt_base(
	unsigned indx, unsigned base_indx, unsigned offset)
{ … }

static inline u32 host1x_class_host_incr_syncpt_base(
	unsigned base_indx, unsigned offset)
{ … }

static inline u32 host1x_class_host_incr_syncpt(
	unsigned cond, unsigned indx)
{ … }

static inline u32 host1x_class_host_indoff_reg_write(
	unsigned mod_id, unsigned offset, bool auto_inc)
{ … }

static inline u32 host1x_class_host_indoff_reg_read(
	unsigned mod_id, unsigned offset, bool auto_inc)
{ … }

static inline u32 host1x_opcode_setclass(
	unsigned class_id, unsigned offset, unsigned mask)
{ … }

static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
{ … }

static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
{ … }

static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
{ … }

static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
{ … }

static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
{ … }

static inline u32 host1x_opcode_restart(unsigned address)
{ … }

static inline u32 host1x_opcode_gather(unsigned count)
{ … }

static inline u32 host1x_opcode_gather_nonincr(unsigned offset,	unsigned count)
{ … }

static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
{ … }

static inline u32 host1x_opcode_setstreamid(unsigned streamid)
{ … }

static inline u32 host1x_opcode_setpayload(unsigned payload)
{ … }

static inline u32 host1x_opcode_gather_wide(unsigned count)
{ … }

static inline u32 host1x_opcode_acquire_mlock(unsigned mlock)
{ … }

static inline u32 host1x_opcode_release_mlock(unsigned mlock)
{ … }

#define HOST1X_OPCODE_NOP …

#endif