/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2015 NVIDIA Corporation. */ /* * Function naming determines intended use: * * <x>_r(void) : Returns the offset for register <x>. * * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. * * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. * * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted * and masked to place it at field <y> of register <x>. This value * can be |'d with others to produce a full register value for * register <x>. * * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This * value can be ~'d and then &'d to clear the value of field <y> for * register <x>. * * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted * to place it at field <y> of register <x>. This value can be |'d * with others to produce a full register value for <x>. * * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register * <x> value 'r' after being shifted to place its LSB at bit 0. * This value is suitable for direct comparison with other unshifted * values appropriate for use in field <y> of register <x>. * * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for * field <y> of register <x>. This value is suitable for direct * comparison with unshifted values appropriate for use in field <y> * of register <x>. */ #ifndef HOST1X_HW_HOST1X05_UCLASS_H #define HOST1X_HW_HOST1X05_UCLASS_H static inline u32 host1x_uclass_incr_syncpt_r(void) { … } #define HOST1X_UCLASS_INCR_SYNCPT … static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) { … } #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) … static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) { … } #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) … static inline u32 host1x_uclass_wait_syncpt_r(void) { … } #define HOST1X_UCLASS_WAIT_SYNCPT … static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v) { … } #define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) … static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v) { … } #define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) … static inline u32 host1x_uclass_wait_syncpt_base_r(void) { … } #define HOST1X_UCLASS_WAIT_SYNCPT_BASE … static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v) { … } #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) … static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v) { … } #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) … static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v) { … } #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) … static inline u32 host1x_uclass_load_syncpt_base_r(void) { … } #define HOST1X_UCLASS_LOAD_SYNCPT_BASE … static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v) { … } #define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) … static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v) { … } #define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) … static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v) { … } #define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) … static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v) { … } #define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) … static inline u32 host1x_uclass_indoff_r(void) { … } #define HOST1X_UCLASS_INDOFF … static inline u32 host1x_uclass_indoff_indbe_f(u32 v) { … } #define HOST1X_UCLASS_INDOFF_INDBE_F(v) … static inline u32 host1x_uclass_indoff_autoinc_f(u32 v) { … } #define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) … static inline u32 host1x_uclass_indoff_indmodid_f(u32 v) { … } #define HOST1X_UCLASS_INDOFF_INDMODID_F(v) … static inline u32 host1x_uclass_indoff_indroffset_f(u32 v) { … } #define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) … static inline u32 host1x_uclass_indoff_rwn_read_v(void) { … } #define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) … static inline u32 host1x_uclass_load_syncpt_payload_32_r(void) { … } #define HOST1X_UCLASS_LOAD_SYNCPT_PAYLOAD_32 … static inline u32 host1x_uclass_wait_syncpt_32_r(void) { … } #define HOST1X_UCLASS_WAIT_SYNCPT_32 … #endif
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