/* SPDX-License-Identifier: GPL-2.0 */ /* * (C) COPYRIGHT 2018 ARM Limited. All rights reserved. * Author: James.Qian.Wang <[email protected]> * */ #ifndef _D71_REG_H_ #define _D71_REG_H_ /* Common block registers offset */ #define BLK_BLOCK_INFO … #define BLK_PIPELINE_INFO … #define BLK_MAX_LINE_SIZE … #define BLK_VALID_INPUT_ID0 … #define BLK_OUTPUT_ID0 … #define BLK_INPUT_ID0 … #define BLK_IRQ_RAW_STATUS … #define BLK_IRQ_CLEAR … #define BLK_IRQ_MASK … #define BLK_IRQ_STATUS … #define BLK_STATUS … #define BLK_INFO … #define BLK_CONTROL … #define BLK_SIZE … #define BLK_IN_SIZE … #define BLK_P0_PTR_LOW … #define BLK_P0_PTR_HIGH … #define BLK_P0_STRIDE … #define BLK_P1_PTR_LOW … #define BLK_P1_PTR_HIGH … #define BLK_P1_STRIDE … #define BLK_P2_PTR_LOW … #define BLK_P2_PTR_HIGH … #define BLOCK_INFO_N_SUBBLKS(x) … #define BLOCK_INFO_BLK_ID(x) … #define BLOCK_INFO_BLK_TYPE(x) … #define BLOCK_INFO_INPUT_ID(x) … #define BLOCK_INFO_TYPE_ID(x) … #define PIPELINE_INFO_N_OUTPUTS(x) … #define PIPELINE_INFO_N_VALID_INPUTS(x) … /* Common block control register bits */ #define BLK_CTRL_EN … /* Common size macro */ #define HV_SIZE(h, v) … #define HV_OFFSET(h, v) … #define HV_CROP(h, v) … /* AD_CONTROL register */ #define AD_CONTROL … /* AD_CONTROL register bits */ #define AD_AEN … #define AD_YT … #define AD_BS … #define AD_WB … #define AD_TH … /* Global Control Unit */ #define GLB_ARCH_ID … #define GLB_CORE_ID … #define GLB_CORE_INFO … #define GLB_IRQ_STATUS … #define GCU_CONFIG_VALID0 … #define GCU_CONFIG_VALID1 … /* GCU_CONTROL_BITS */ #define GCU_CONTROL_MODE(x) … #define GCU_CONTROL_SRST … /* GCU_CONFIGURATION registers */ #define GCU_CONFIGURATION_ID0 … #define GCU_CONFIGURATION_ID1 … /* GCU configuration */ #define GCU_MAX_LINE_SIZE(x) … #define GCU_MAX_NUM_LINES(x) … #define GCU_NUM_RICH_LAYERS(x) … #define GCU_NUM_PIPELINES(x) … #define GCU_NUM_SCALERS(x) … #define GCU_DISPLAY_SPLIT_EN(x) … #define GCU_DISPLAY_TBU_EN(x) … /* GCU opmode */ #define INACTIVE_MODE … #define TBU_CONNECT_MODE … #define TBU_DISCONNECT_MODE … #define DO0_ACTIVE_MODE … #define DO1_ACTIVE_MODE … #define DO01_ACTIVE_MODE … /* GLB_IRQ_STATUS bits */ #define GLB_IRQ_STATUS_GCU … #define GLB_IRQ_STATUS_LPU0 … #define GLB_IRQ_STATUS_LPU1 … #define GLB_IRQ_STATUS_ATU0 … #define GLB_IRQ_STATUS_ATU1 … #define GLB_IRQ_STATUS_ATU2 … #define GLB_IRQ_STATUS_ATU3 … #define GLB_IRQ_STATUS_CU0 … #define GLB_IRQ_STATUS_CU1 … #define GLB_IRQ_STATUS_DOU0 … #define GLB_IRQ_STATUS_DOU1 … #define GLB_IRQ_STATUS_PIPE0 … #define GLB_IRQ_STATUS_PIPE1 … #define GLB_IRQ_STATUS_ATU … /* GCU_IRQ_BITS */ #define GCU_IRQ_CVAL0 … #define GCU_IRQ_CVAL1 … #define GCU_IRQ_MODE … #define GCU_IRQ_ERR … /* GCU_STATUS_BITS */ #define GCU_STATUS_MODE(x) … #define GCU_STATUS_MERR … #define GCU_STATUS_TCS0 … #define GCU_STATUS_TCS1 … #define GCU_STATUS_ACTIVE … /* GCU_CONFIG_VALIDx BITS */ #define GCU_CONFIG_CVAL … /* PERIPHERAL registers */ #define PERIPH_MAX_LINE_SIZE … #define PERIPH_NUM_RICH_LAYERS … #define PERIPH_SPLIT_EN … #define PERIPH_TBU_EN … #define PERIPH_AFBC_DMA_EN … #define PERIPH_CONFIGURATION_ID … /* LPU register */ #define LPU_TBU_STATUS … #define LPU_RAXI_CONTROL … #define LPU_WAXI_CONTROL … #define LPU_TBU_CONTROL … /* LPU_xAXI_CONTROL_BITS */ #define TO_RAXI_AOUTSTDCAPB(x) … #define TO_RAXI_BOUTSTDCAPB(x) … #define TO_RAXI_BEN(x) … #define TO_xAXI_BURSTLEN(x) … #define TO_xAXI_AxQOS(x) … #define TO_xAXI_ORD(x) … #define TO_WAXI_OUTSTDCAPB(x) … #define RAXI_AOUTSTDCAPB_MASK … #define RAXI_BOUTSTDCAPB_MASK … #define RAXI_BEN_MASK … #define xAXI_BURSTLEN_MASK … #define xAXI_AxQOS_MASK … #define xAXI_ORD_MASK … #define WAXI_OUTSTDCAPB_MASK … /* LPU_TBU_CONTROL BITS */ #define TO_TBU_DOUTSTDCAPB(x) … #define TBU_DOUTSTDCAPB_MASK … /* LPU_IRQ_BITS */ #define LPU_IRQ_OVR … #define LPU_IRQ_IBSY … #define LPU_IRQ_ERR … #define LPU_IRQ_EOW … #define LPU_IRQ_PL0 … /* LPU_STATUS_BITS */ #define LPU_STATUS_AXIED(x) … #define LPU_STATUS_AXIE … #define LPU_STATUS_AXIRP … #define LPU_STATUS_AXIWP … #define LPU_STATUS_FEMPTY … #define LPU_STATUS_FFULL … #define LPU_STATUS_ACE0 … #define LPU_STATUS_ACE1 … #define LPU_STATUS_ACE2 … #define LPU_STATUS_ACE3 … #define LPU_STATUS_ACTIVE … #define AXIEID_MASK … #define AXIE_MASK … #define AXIRP_MASK … #define AXIWP_MASK … #define FROM_AXIEID(reg) … #define TO_AXIE(x) … #define FROM_AXIRP(reg) … #define FROM_AXIWP(reg) … /* LPU_TBU_STATUS_BITS */ #define LPU_TBU_STATUS_TCF … #define LPU_TBU_STATUS_TTNG … #define LPU_TBU_STATUS_TITR … #define LPU_TBU_STATUS_TEMR … #define LPU_TBU_STATUS_TTF … /* LPU_TBU_CONTROL BITS */ #define LPU_TBU_CTRL_TLBPEN … /* CROSSBAR CONTROL BITS */ #define CBU_INPUT_CTRL_EN … #define CBU_NUM_INPUT_IDS … #define CBU_NUM_OUTPUT_IDS … /* CU register */ #define CU_BG_COLOR … #define CU_INPUT0_SIZE … #define CU_INPUT0_OFFSET … #define CU_INPUT0_CONTROL … #define CU_INPUT1_SIZE … #define CU_INPUT1_OFFSET … #define CU_INPUT1_CONTROL … #define CU_INPUT2_SIZE … #define CU_INPUT2_OFFSET … #define CU_INPUT2_CONTROL … #define CU_INPUT3_SIZE … #define CU_INPUT3_OFFSET … #define CU_INPUT3_CONTROL … #define CU_INPUT4_SIZE … #define CU_INPUT4_OFFSET … #define CU_INPUT4_CONTROL … #define CU_PER_INPUT_REGS … #define CU_NUM_INPUT_IDS … #define CU_NUM_OUTPUT_IDS … /* CU control register bits */ #define CU_CTRL_COPROC … /* CU_IRQ_BITS */ #define CU_IRQ_OVR … #define CU_IRQ_ERR … /* CU_STATUS_BITS */ #define CU_STATUS_CPE … #define CU_STATUS_ZME … #define CU_STATUS_CFGE … #define CU_STATUS_ACTIVE … /* CU input control register bits */ #define CU_INPUT_CTRL_EN … #define CU_INPUT_CTRL_PAD … #define CU_INPUT_CTRL_PMUL … #define CU_INPUT_CTRL_ALPHA(x) … /* DOU register */ /* DOU_IRQ_BITS */ #define DOU_IRQ_UND … #define DOU_IRQ_ERR … #define DOU_IRQ_PL0 … #define DOU_IRQ_PL1 … /* DOU_STATUS_BITS */ #define DOU_STATUS_DRIFTTO … #define DOU_STATUS_FRAMETO … #define DOU_STATUS_TETO … #define DOU_STATUS_CSCE … #define DOU_STATUS_ACTIVE … /* Layer registers */ #define LAYER_INFO … #define LAYER_R_CONTROL … #define LAYER_FMT … #define LAYER_LT_COEFFTAB … #define LAYER_PALPHA … #define LAYER_YUV_RGB_COEFF0 … #define LAYER_AD_H_CROP … #define LAYER_AD_V_CROP … #define LAYER_RGB_RGB_COEFF0 … /* L_CONTROL_BITS */ #define L_EN … #define L_IT … #define L_R2R … #define L_FT … #define L_ROT(x) … #define L_HFLIP … #define L_VFLIP … #define L_TBU_EN … #define L_A_RCACHE(x) … #define L_ROT_R0 … #define L_ROT_R90 … #define L_ROT_R180 … #define L_ROT_R270 … /* LAYER_R_CONTROL BITS */ #define LR_CHI422_BILINEAR … #define LR_CHI422_REPLICATION … #define LR_CHI420_JPEG … #define LR_CHI420_MPEG … #define L_ITSEL(x) … #define L_FTSEL(x) … #define LAYER_PER_PLANE_REGS … /* Layer_WR registers */ #define LAYER_WR_PROG_LINE … #define LAYER_WR_FORMAT … /* Layer_WR control bits */ #define LW_OFM … #define LW_LALPHA(x) … #define LW_A_WCACHE(x) … #define LW_TBU_EN … #define AxCACHE_MASK … /* Layer AXI R/W cache setting */ #define AxCACHE_B … #define AxCACHE_M … #define AxCACHE_RA … #define AxCACHE_WA … /* Layer info bits */ #define L_INFO_RF … #define L_INFO_CM … #define L_INFO_ABUF_SIZE(x) … #define L_INFO_YUV_MAX_LINESZ(x) … /* Scaler registers */ #define SC_COEFFTAB … #define SC_OUT_SIZE … #define SC_H_CROP … #define SC_V_CROP … #define SC_H_INIT_PH … #define SC_H_DELTA_PH … #define SC_V_INIT_PH … #define SC_V_DELTA_PH … #define SC_ENH_LIMITS … #define SC_ENH_COEFF0 … #define SC_MAX_ENH_COEFF … /* SC_CTRL_BITS */ #define SC_CTRL_SCL … #define SC_CTRL_LS … #define SC_CTRL_AP … #define SC_CTRL_IENH … #define SC_CTRL_RGBSM … #define SC_CTRL_ASM … #define SC_VTSEL(vtal) … #define SC_NUM_INPUTS_IDS … #define SC_NUM_OUTPUTS_IDS … #define MG_NUM_INPUTS_IDS … #define MG_NUM_OUTPUTS_IDS … /* Merger registers */ #define MG_INPUT_ID0 … #define MG_INPUT_ID1 … #define MG_SIZE … /* Splitter registers */ #define SP_OVERLAP_SIZE … /* Backend registers */ #define BS_INFO … #define BS_PROG_LINE … #define BS_PREFETCH_LINE … #define BS_BG_COLOR … #define BS_ACTIVESIZE … #define BS_HINTERVALS … #define BS_VINTERVALS … #define BS_SYNC … #define BS_DRIFT_TO … #define BS_FRAME_TO … #define BS_TE_TO … #define BS_T0_INTERVAL … #define BS_T1_INTERVAL … #define BS_T2_INTERVAL … #define BS_CRC0_LOW … #define BS_CRC0_HIGH … #define BS_CRC1_LOW … #define BS_CRC1_HIGH … #define BS_USER … /* BS control register bits */ #define BS_CTRL_EN … #define BS_CTRL_VM … #define BS_CTRL_BM … #define BS_CTRL_HMASK … #define BS_CTRL_VD … #define BS_CTRL_TE … #define BS_CTRL_TS … #define BS_CTRL_TM … #define BS_CTRL_DL … #define BS_CTRL_SBS … #define BS_CTRL_CRC … #define BS_CTRL_PM … /* BS active size/intervals */ #define BS_H_INTVALS(hfp, hbp) … #define BS_V_INTVALS(vfp, vbp) … /* BS_SYNC bits */ #define BS_SYNC_HSW(x) … #define BS_SYNC_HSP … #define BS_SYNC_VSW(x) … #define BS_SYNC_VSP … #define BS_NUM_INPUT_IDS … #define BS_NUM_OUTPUT_IDS … /* Image process registers */ #define IPS_DEPTH … #define IPS_RGB_RGB_COEFF0 … #define IPS_RGB_YUV_COEFF0 … #define IPS_DEPTH_MARK … /* IPS control register bits */ #define IPS_CTRL_RGB … #define IPS_CTRL_FT … #define IPS_CTRL_YUV … #define IPS_CTRL_CHD422 … #define IPS_CTRL_CHD420 … #define IPS_CTRL_LPF … #define IPS_CTRL_DITH … #define IPS_CTRL_CLAMP … #define IPS_CTRL_SBS … /* IPS info register bits */ #define IPS_INFO_CHD420 … #define IPS_NUM_INPUT_IDS … #define IPS_NUM_OUTPUT_IDS … /* FT_COEFF block registers */ #define FT_COEFF0 … #define GLB_IT_COEFF … /* GLB_SC_COEFF registers */ #define GLB_SC_COEFF_ADDR … #define GLB_SC_COEFF_DATA … #define GLB_LT_COEFF_DATA … #define GLB_SC_COEFF_MAX_NUM … #define GLB_LT_COEFF_NUM … /* GLB_SC_ADDR */ #define SC_COEFF_R_ADDR … #define SC_COEFF_G_ADDR … #define SC_COEFF_B_ADDR … #define SC_COEFF_DATA(x, y) … enum d71_blk_type { … }; /* Constant of components */ #define D71_MAX_PIPELINE … #define D71_PIPELINE_MAX_SCALERS … #define D71_PIPELINE_MAX_LAYERS … #define D71_MAX_GLB_IT_COEFF … #define D71_MAX_GLB_SCL_COEFF … #define D71_MAX_LAYERS_PER_LPU … #define D71_BLOCK_MAX_INPUT … #define D71_BLOCK_MAX_OUTPUT … #define D71_MAX_SC_PER_CU … #define D71_BLOCK_OFFSET_PERIPH … #define D71_BLOCK_SIZE … #define D71_DEFAULT_PREPRETCH_LINE … #define D71_BUS_WIDTH_16_BYTES … #define D71_SC_MAX_UPSCALING … #define D71_SC_MAX_DOWNSCALING … #define D71_SC_SPLIT_OVERLAP … #define D71_SC_ENH_SPLIT_OVERLAP … #define D71_MG_MIN_MERGED_SIZE … #define D71_MG_MAX_MERGED_HSIZE … #define D71_MG_MAX_MERGED_VSIZE … #define D71_PALPHA_DEF_MAP … #define D71_LAYER_CONTROL_DEFAULT … #define D71_WB_LAYER_CONTROL_DEFAULT … #define D71_BS_CONTROL_DEFAULT … struct block_header { … }; static inline u32 get_block_type(struct block_header *blk) { … } #endif /* !_D71_REG_H_ */
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