/* SPDX-License-Identifier: GPL-2.0 */ /* * ARM HDLCD Controller register definition */ #ifndef __HDLCD_DRV_H__ #define __HDLCD_DRV_H__ struct hdlcd_drm_private { … }; #define drm_to_hdlcd_priv(x) … #define crtc_to_hdlcd_priv(x) … static inline void hdlcd_write(struct hdlcd_drm_private *hdlcd, unsigned int reg, u32 value) { … } static inline u32 hdlcd_read(struct hdlcd_drm_private *hdlcd, unsigned int reg) { … } int hdlcd_setup_crtc(struct drm_device *dev); void hdlcd_set_scanout(struct hdlcd_drm_private *hdlcd); #endif /* __HDLCD_DRV_H__ */