/* * Copyright (C) 2013,2014 ARM Limited * * This file is subject to the terms and conditions of the GNU General Public * License. See the file COPYING in the main directory of this archive * for more details. * * ARM HDLCD Controller register definition */ #ifndef __HDLCD_REGS_H__ #define __HDLCD_REGS_H__ /* register offsets */ #define HDLCD_REG_VERSION … #define HDLCD_REG_INT_RAWSTAT … #define HDLCD_REG_INT_CLEAR … #define HDLCD_REG_INT_MASK … #define HDLCD_REG_INT_STATUS … #define HDLCD_REG_FB_BASE … #define HDLCD_REG_FB_LINE_LENGTH … #define HDLCD_REG_FB_LINE_COUNT … #define HDLCD_REG_FB_LINE_PITCH … #define HDLCD_REG_BUS_OPTIONS … #define HDLCD_REG_V_SYNC … #define HDLCD_REG_V_BACK_PORCH … #define HDLCD_REG_V_DATA … #define HDLCD_REG_V_FRONT_PORCH … #define HDLCD_REG_H_SYNC … #define HDLCD_REG_H_BACK_PORCH … #define HDLCD_REG_H_DATA … #define HDLCD_REG_H_FRONT_PORCH … #define HDLCD_REG_POLARITIES … #define HDLCD_REG_COMMAND … #define HDLCD_REG_PIXEL_FORMAT … #define HDLCD_REG_RED_SELECT … #define HDLCD_REG_GREEN_SELECT … #define HDLCD_REG_BLUE_SELECT … /* version */ #define HDLCD_PRODUCT_ID … #define HDLCD_PRODUCT_MASK … #define HDLCD_VERSION_MAJOR_MASK … #define HDLCD_VERSION_MINOR_MASK … /* interrupts */ #define HDLCD_INTERRUPT_DMA_END … #define HDLCD_INTERRUPT_BUS_ERROR … #define HDLCD_INTERRUPT_VSYNC … #define HDLCD_INTERRUPT_UNDERRUN … #define HDLCD_DEBUG_INT_MASK … /* polarities */ #define HDLCD_POLARITY_VSYNC … #define HDLCD_POLARITY_HSYNC … #define HDLCD_POLARITY_DATAEN … #define HDLCD_POLARITY_DATA … #define HDLCD_POLARITY_PIXELCLK … /* commands */ #define HDLCD_COMMAND_DISABLE … #define HDLCD_COMMAND_ENABLE … /* pixel format */ #define HDLCD_PIXEL_FMT_LITTLE_ENDIAN … #define HDLCD_PIXEL_FMT_BIG_ENDIAN … #define HDLCD_BYTES_PER_PIXEL_MASK … /* bus options */ #define HDLCD_BUS_BURST_MASK … #define HDLCD_BUS_MAX_OUTSTAND … #define HDLCD_BUS_BURST_NONE … #define HDLCD_BUS_BURST_1 … #define HDLCD_BUS_BURST_2 … #define HDLCD_BUS_BURST_4 … #define HDLCD_BUS_BURST_8 … #define HDLCD_BUS_BURST_16 … /* Max resolution supported is 4096x4096, 32bpp */ #define HDLCD_MAX_XRES … #define HDLCD_MAX_YRES … #define NR_PALETTE … #endif /* __HDLCD_REGS_H__ */
Codebase Browser
linux