/* SPDX-License-Identifier: GPL-2.0-only */ /* * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. * Author: Liviu Dudau <[email protected]> * * ARM Mali DP500/DP550/DP650 registers definition. */ #ifndef __MALIDP_REGS_H__ #define __MALIDP_REGS_H__ /* * abbreviations used: * - DC - display core (general settings) * - DE - display engine * - SE - scaling engine */ /* interrupt bit masks */ #define MALIDP_DE_IRQ_UNDERRUN … #define MALIDP500_DE_IRQ_AXI_ERR … #define MALIDP500_DE_IRQ_VSYNC … #define MALIDP500_DE_IRQ_PROG_LINE … #define MALIDP500_DE_IRQ_SATURATION … #define MALIDP500_DE_IRQ_CONF_VALID … #define MALIDP500_DE_IRQ_CONF_MODE … #define MALIDP500_DE_IRQ_CONF_ACTIVE … #define MALIDP500_DE_IRQ_PM_ACTIVE … #define MALIDP500_DE_IRQ_TESTMODE_ACTIVE … #define MALIDP500_DE_IRQ_FORCE_BLNK_ACTIVE … #define MALIDP500_DE_IRQ_AXI_BUSY … #define MALIDP500_DE_IRQ_GLOBAL … #define MALIDP500_SE_IRQ_CONF_MODE … #define MALIDP500_SE_IRQ_CONF_VALID … #define MALIDP500_SE_IRQ_INIT_BUSY … #define MALIDP500_SE_IRQ_AXI_ERROR … #define MALIDP500_SE_IRQ_OVERRUN … #define MALIDP500_SE_IRQ_PROG_LINE1 … #define MALIDP500_SE_IRQ_PROG_LINE2 … #define MALIDP500_SE_IRQ_CONF_ACTIVE … #define MALIDP500_SE_IRQ_PM_ACTIVE … #define MALIDP500_SE_IRQ_AXI_BUSY … #define MALIDP500_SE_IRQ_GLOBAL … #define MALIDP550_DE_IRQ_SATURATION … #define MALIDP550_DE_IRQ_VSYNC … #define MALIDP550_DE_IRQ_PROG_LINE … #define MALIDP550_DE_IRQ_AXI_ERR … #define MALIDP550_SE_IRQ_EOW … #define MALIDP550_SE_IRQ_AXI_ERR … #define MALIDP550_SE_IRQ_OVR … #define MALIDP550_SE_IRQ_IBSY … #define MALIDP550_DC_IRQ_CONF_VALID … #define MALIDP550_DC_IRQ_CONF_MODE … #define MALIDP550_DC_IRQ_CONF_ACTIVE … #define MALIDP550_DC_IRQ_DE … #define MALIDP550_DC_IRQ_SE … #define MALIDP650_DE_IRQ_DRIFT … #define MALIDP650_DE_IRQ_ACEV1 … #define MALIDP650_DE_IRQ_ACEV2 … #define MALIDP650_DE_IRQ_ACEG … #define MALIDP650_DE_IRQ_AXIEP … /* bit masks that are common between products */ #define MALIDP_CFG_VALID … #define MALIDP_DISP_FUNC_GAMMA … #define MALIDP_DISP_FUNC_CADJ … #define MALIDP_DISP_FUNC_ILACED … #define MALIDP_SCALE_ENGINE_EN … #define MALIDP_SE_MEMWRITE_EN … /* register offsets for IRQ management */ #define MALIDP_REG_STATUS … #define MALIDP_REG_SETIRQ … #define MALIDP_REG_MASKIRQ … #define MALIDP_REG_CLEARIRQ … /* register offsets */ #define MALIDP_DE_CORE_ID … #define MALIDP_DE_DISPLAY_FUNC … /* these offsets are relative to MALIDP5x0_TIMINGS_BASE */ #define MALIDP_DE_H_TIMINGS … #define MALIDP_DE_V_TIMINGS … #define MALIDP_DE_SYNC_WIDTH … #define MALIDP_DE_HV_ACTIVE … /* Stride register offsets relative to Lx_BASE */ #define MALIDP_DE_LG_STRIDE … #define MALIDP_DE_LV_STRIDE0 … #define MALIDP550_DE_LS_R1_STRIDE … /* macros to set values into registers */ #define MALIDP_DE_H_FRONTPORCH(x) … #define MALIDP_DE_H_BACKPORCH(x) … #define MALIDP500_DE_V_FRONTPORCH(x) … #define MALIDP550_DE_V_FRONTPORCH(x) … #define MALIDP_DE_V_BACKPORCH(x) … #define MALIDP_DE_H_SYNCWIDTH(x) … #define MALIDP_DE_V_SYNCWIDTH(x) … #define MALIDP_DE_H_ACTIVE(x) … #define MALIDP_DE_V_ACTIVE(x) … #define MALIDP_PRODUCT_ID(__core_id) … /* register offsets relative to MALIDP5x0_COEFFS_BASE */ #define MALIDP_COLOR_ADJ_COEF … #define MALIDP_COEF_TABLE_ADDR … #define MALIDP_COEF_TABLE_DATA … /* Scaling engine registers and masks. */ #define MALIDP_SE_SCALING_EN … #define MALIDP_SE_ALPHA_EN … #define MALIDP_SE_ENH_MASK … #define MALIDP_SE_ENH(x) … #define MALIDP_SE_RGBO_IF_EN … #define MALIDP550_SE_CTL_SEL_MASK … #define MALIDP550_SE_CTL_VCSEL(x) … #define MALIDP550_SE_CTL_HCSEL(x) … /* Blocks with offsets from SE_CONTROL register. */ #define MALIDP_SE_LAYER_CONTROL … #define MALIDP_SE_L0_IN_SIZE … #define MALIDP_SE_L0_OUT_SIZE … #define MALIDP_SE_SET_V_SIZE(x) … #define MALIDP_SE_SET_H_SIZE(x) … #define MALIDP_SE_SCALING_CONTROL … #define MALIDP_SE_H_INIT_PH … #define MALIDP_SE_H_DELTA_PH … #define MALIDP_SE_V_INIT_PH … #define MALIDP_SE_V_DELTA_PH … #define MALIDP_SE_COEFFTAB_ADDR … #define MALIDP_SE_COEFFTAB_ADDR_MASK … #define MALIDP_SE_V_COEFFTAB … #define MALIDP_SE_H_COEFFTAB … #define MALIDP_SE_SET_V_COEFFTAB_ADDR(x) … #define MALIDP_SE_SET_H_COEFFTAB_ADDR(x) … #define MALIDP_SE_COEFFTAB_DATA … #define MALIDP_SE_COEFFTAB_DATA_MASK … #define MALIDP_SE_SET_COEFFTAB_DATA(x) … /* Enhance coefficients register offset */ #define MALIDP_SE_IMAGE_ENH … /* ENH_LIMITS offset 0x0 */ #define MALIDP_SE_ENH_LOW_LEVEL … #define MALIDP_SE_ENH_HIGH_LEVEL … #define MALIDP_SE_ENH_LIMIT_MASK … #define MALIDP_SE_SET_ENH_LIMIT_LOW(x) … #define MALIDP_SE_SET_ENH_LIMIT_HIGH(x) … #define MALIDP_SE_ENH_COEFF0 … /* register offsets relative to MALIDP5x0_SE_MEMWRITE_BASE */ #define MALIDP_MW_FORMAT … #define MALIDP_MW_P1_STRIDE … #define MALIDP_MW_P2_STRIDE … #define MALIDP_MW_P1_PTR_LOW … #define MALIDP_MW_P1_PTR_HIGH … #define MALIDP_MW_P2_PTR_LOW … #define MALIDP_MW_P2_PTR_HIGH … /* register offsets and bits specific to DP500 */ #define MALIDP500_ADDR_SPACE_SIZE … #define MALIDP500_DC_BASE … #define MALIDP500_DC_CONTROL … #define MALIDP500_DC_CONFIG_REQ … #define MALIDP500_HSYNCPOL … #define MALIDP500_VSYNCPOL … #define MALIDP500_DC_CLEAR_MASK … #define MALIDP500_DE_LINE_COUNTER … #define MALIDP500_DE_AXI_CONTROL … #define MALIDP500_DE_SECURE_CTRL … #define MALIDP500_DE_CHROMA_KEY … #define MALIDP500_TIMINGS_BASE … #define MALIDP500_CONFIG_3D … #define MALIDP500_BGND_COLOR … #define MALIDP500_OUTPUT_DEPTH … #define MALIDP500_COEFFS_BASE … /* * The YUV2RGB coefficients on the DP500 are not in the video layer's register * block. They belong in a separate block above the layer's registers, hence * the negative offset. */ #define MALIDP500_LV_YUV2RGB … #define MALIDP500_DE_LV_BASE … #define MALIDP500_DE_LV_PTR_BASE … #define MALIDP500_DE_LV_AD_CTRL … #define MALIDP500_DE_LG1_BASE … #define MALIDP500_DE_LG1_PTR_BASE … #define MALIDP500_DE_LG1_AD_CTRL … #define MALIDP500_DE_LG2_BASE … #define MALIDP500_DE_LG2_PTR_BASE … #define MALIDP500_DE_LG2_AD_CTRL … #define MALIDP500_SE_BASE … #define MALIDP500_SE_CONTROL … #define MALIDP500_SE_MEMWRITE_OUT_SIZE … #define MALIDP500_SE_RGB_YUV_COEFFS … #define MALIDP500_SE_MEMWRITE_BASE … #define MALIDP500_DC_IRQ_BASE … #define MALIDP500_CONFIG_VALID … #define MALIDP500_CONFIG_ID … /* * The quality of service (QoS) register on the DP500. RQOS register values * are driven by the ARQOS signal, using AXI transacations, dependent on the * FIFO input level. * The RQOS register can also set QoS levels for: * - RED_ARQOS @ A 4-bit signal value for close to underflow conditions * - GREEN_ARQOS @ A 4-bit signal value for normal conditions */ #define MALIDP500_RQOS_QUALITY … /* register offsets and bits specific to DP550/DP650 */ #define MALIDP550_ADDR_SPACE_SIZE … #define MALIDP550_DE_CONTROL … #define MALIDP550_DE_LINE_COUNTER … #define MALIDP550_DE_AXI_CONTROL … #define MALIDP550_DE_QOS … #define MALIDP550_TIMINGS_BASE … #define MALIDP550_HSYNCPOL … #define MALIDP550_VSYNCPOL … #define MALIDP550_DE_DISP_SIDEBAND … #define MALIDP550_DE_BGND_COLOR … #define MALIDP550_DE_OUTPUT_DEPTH … #define MALIDP550_COEFFS_BASE … #define MALIDP550_LV_YUV2RGB … #define MALIDP550_DE_LV1_BASE … #define MALIDP550_DE_LV1_PTR_BASE … #define MALIDP550_DE_LV1_AD_CTRL … #define MALIDP550_DE_LV2_BASE … #define MALIDP550_DE_LV2_PTR_BASE … #define MALIDP550_DE_LV2_AD_CTRL … #define MALIDP550_DE_LG_BASE … #define MALIDP550_DE_LG_PTR_BASE … #define MALIDP550_DE_LG_AD_CTRL … #define MALIDP550_DE_LS_BASE … #define MALIDP550_DE_LS_PTR_BASE … #define MALIDP550_DE_PERF_BASE … #define MALIDP550_SE_BASE … #define MALIDP550_SE_CONTROL … #define MALIDP550_SE_MEMWRITE_ONESHOT … #define MALIDP550_SE_MEMWRITE_OUT_SIZE … #define MALIDP550_SE_RGB_YUV_COEFFS … #define MALIDP550_SE_MEMWRITE_BASE … #define MALIDP550_DC_BASE … #define MALIDP550_DC_CONTROL … #define MALIDP550_DC_CONFIG_REQ … #define MALIDP550_CONFIG_VALID … #define MALIDP550_CONFIG_ID … /* register offsets specific to DP650 */ #define MALIDP650_DE_LV_MMU_CTRL … #define MALIDP650_DE_LG_MMU_CTRL … #define MALIDP650_DE_LS_MMU_CTRL … /* bit masks to set the MMU control register */ #define MALIDP_MMU_CTRL_EN … #define MALIDP_MMU_CTRL_MODE … #define MALIDP_MMU_CTRL_PX_PS(x) … #define MALIDP_MMU_CTRL_PP_NUM_REQ(x) … /* AFBC register offsets relative to MALIDPXXX_DE_LX_AD_CTRL */ /* The following register offsets are common for DP500, DP550 and DP650 */ #define MALIDP_AD_CROP_H … #define MALIDP_AD_CROP_V … #define MALIDP_AD_END_PTR_LOW … #define MALIDP_AD_END_PTR_HIGH … /* AFBC decoder Registers */ #define MALIDP_AD_EN … #define MALIDP_AD_YTR … #define MALIDP_AD_BS … #define MALIDP_AD_CROP_RIGHT_OFFSET … #define MALIDP_AD_CROP_BOTTOM_OFFSET … /* * Starting with DP550 the register map blocks has been standardised to the * following layout: * * Offset Block registers * 0x00000 Display Engine * 0x08000 Scaling Engine * 0x0c000 Display Core * 0x10000 Secure control * * The old DP500 IP mixes some DC with the DE registers, hence the need * for a mapping structure. */ #endif /* __MALIDP_REGS_H__ */
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