/* SPDX-License-Identifier: GPL-2.0-only */ /* * * (C) COPYRIGHT 2013-2016 ARM Limited. All rights reserved. * * ARM Mali DP hardware manipulation routines. */ #ifndef __MALIDP_HW_H__ #define __MALIDP_HW_H__ #include <linux/bitops.h> #include "malidp_regs.h" struct videomode; struct clk; /* Mali DP IP blocks */ enum { … }; /* Mali DP layer IDs */ enum { … }; enum rotation_features { … }; struct malidp_format_id { … }; #define MALIDP_INVALID_FORMAT_ID … /* * hide the differences between register maps * by using a common structure to hold the * base register offsets */ struct malidp_irq_map { … }; struct malidp_layer { … }; enum malidp_scaling_coeff_set { … }; struct malidp_se_config { … }; /* regmap features */ #define MALIDP_REGMAP_HAS_CLEARIRQ … #define MALIDP_DEVICE_AFBC_SUPPORT_SPLIT … #define MALIDP_DEVICE_AFBC_YUV_420_10_SUPPORT_SPLIT … #define MALIDP_DEVICE_AFBC_YUYV_USE_422_P2 … struct malidp_hw_regmap { … }; /* device features */ /* Unlike DP550/650, DP500 has 3 stride registers in its video layer. */ #define MALIDP_DEVICE_LV_HAS_3_STRIDES … struct malidp_hw_device; /* * Static structure containing hardware specific data and pointers to * functions that behave differently between various versions of the IP. */ struct malidp_hw { … }; /* Supported variants of the hardware */ enum { … }; extern const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES]; /* * Structure used by the driver during runtime operation. */ struct malidp_hw_device { … }; static inline u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg) { … } static inline void malidp_hw_write(struct malidp_hw_device *hwdev, u32 value, u32 reg) { … } static inline void malidp_hw_setbits(struct malidp_hw_device *hwdev, u32 mask, u32 reg) { … } static inline void malidp_hw_clearbits(struct malidp_hw_device *hwdev, u32 mask, u32 reg) { … } static inline u32 malidp_get_block_base(struct malidp_hw_device *hwdev, u8 block) { … } static inline void malidp_hw_disable_irq(struct malidp_hw_device *hwdev, u8 block, u32 irq) { … } static inline void malidp_hw_enable_irq(struct malidp_hw_device *hwdev, u8 block, u32 irq) { … } int malidp_de_irq_init(struct drm_device *drm, int irq); void malidp_se_irq_hw_init(struct malidp_hw_device *hwdev); void malidp_de_irq_hw_init(struct malidp_hw_device *hwdev); void malidp_de_irq_fini(struct malidp_hw_device *hwdev); int malidp_se_irq_init(struct drm_device *drm, int irq); void malidp_se_irq_fini(struct malidp_hw_device *hwdev); u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map, u8 layer_id, u32 format, bool has_modifier); int malidp_format_get_bpp(u32 fmt); static inline u8 malidp_hw_get_pitch_align(struct malidp_hw_device *hwdev, bool rotated) { … } /* U16.16 */ #define FP_1_00000 … #define FP_0_66667 … #define FP_0_50000 … #define FP_0_36363 … #define FP_0_25000 … static inline enum malidp_scaling_coeff_set malidp_se_select_coeffs(u32 upscale_factor) { … } #undef FP_0_25000 #undef FP_0_36363 #undef FP_0_50000 #undef FP_0_66667 #undef FP_1_00000 static inline void malidp_se_set_enh_coeffs(struct malidp_hw_device *hwdev) { … } /* * background color components are defined as 12bits values, * they will be shifted right when stored on hardware that * supports only 8bits per channel */ #define MALIDP_BGND_COLOR_R … #define MALIDP_BGND_COLOR_G … #define MALIDP_BGND_COLOR_B … #define MALIDP_COLORADJ_NUM_COEFFS … #define MALIDP_COEFFTAB_NUM_COEFFS … #define MALIDP_GAMMA_LUT_SIZE … #define AFBC_SIZE_MASK … #define AFBC_SIZE_16X16 … #define AFBC_YTR … #define AFBC_SPARSE … #define AFBC_CBR … #define AFBC_SPLIT … #define AFBC_TILED … #define AFBC_SC … #define AFBC_MOD_VALID_BITS … extern const u64 malidp_format_modifiers[]; #endif /* __MALIDP_HW_H__ */
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