/* * Copyright © 2009 Keith Packard * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that * the above copyright notice appear in all copies and that both that copyright * notice and this permission notice appear in supporting documentation, and * that the name of the copyright holders not be used in advertising or * publicity pertaining to distribution of the software without specific, * written prior permission. The copyright holders make no representations * about the suitability of this software for any purpose. It is provided "as * is" without express or implied warranty. * * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE * OF THIS SOFTWARE. */ #include <linux/backlight.h> #include <linux/delay.h> #include <linux/errno.h> #include <linux/i2c.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/sched.h> #include <linux/seq_file.h> #include <linux/string_helpers.h> #include <linux/dynamic_debug.h> #include <drm/display/drm_dp_helper.h> #include <drm/display/drm_dp_mst_helper.h> #include <drm/drm_edid.h> #include <drm/drm_fixed.h> #include <drm/drm_print.h> #include <drm/drm_vblank.h> #include <drm/drm_panel.h> #include "drm_dp_helper_internal.h" DECLARE_DYNDBG_CLASSMAP(…); struct dp_aux_backlight { … }; /** * DOC: dp helpers * * These functions contain some common logic and helpers at various abstraction * levels to deal with Display Port sink devices and related things like DP aux * channel transfers, EDID reading over DP aux channels, decoding certain DPCD * blocks, ... */ /* Helpers for DP link training */ static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) { … } static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], int lane) { … } bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], int lane_count) { … } EXPORT_SYMBOL(…); bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], int lane_count) { … } EXPORT_SYMBOL(…); u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], int lane) { … } EXPORT_SYMBOL(…); u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], int lane) { … } EXPORT_SYMBOL(…); /* DP 2.0 128b/132b */ u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], int lane) { … } EXPORT_SYMBOL(…); /* DP 2.0 errata for 128b/132b */ bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE], int lane_count) { … } EXPORT_SYMBOL(…); /* DP 2.0 errata for 128b/132b */ bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE], int lane_count) { … } EXPORT_SYMBOL(…); /* DP 2.0 errata for 128b/132b */ bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]) { … } EXPORT_SYMBOL(…); /* DP 2.0 errata for 128b/132b */ bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]) { … } EXPORT_SYMBOL(…); /* DP 2.0 errata for 128b/132b */ bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]) { … } EXPORT_SYMBOL(…); static int __8b10b_clock_recovery_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) { … } static int __8b10b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) { … } static int __128b132b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) { … } /* * The link training delays are different for: * * - Clock recovery vs. channel equalization * - DPRX vs. LTTPR * - 128b/132b vs. 8b/10b * - DPCD rev 1.3 vs. later * * Get the correct delay in us, reading DPCD if necessary. */ static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], enum drm_dp_phy dp_phy, bool uhbr, bool cr) { … } int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], enum drm_dp_phy dp_phy, bool uhbr) { … } EXPORT_SYMBOL(…); int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], enum drm_dp_phy dp_phy, bool uhbr) { … } EXPORT_SYMBOL(…); /* Per DP 2.0 Errata */ int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux) { … } EXPORT_SYMBOL(…); void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { … } EXPORT_SYMBOL(…); static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, u8 rd_interval) { … } void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { … } EXPORT_SYMBOL(…); /** * drm_dp_phy_name() - Get the name of the given DP PHY * @dp_phy: The DP PHY identifier * * Given the @dp_phy, get a user friendly name of the DP PHY, either "DPRX" or * "LTTPR <N>", or "<INVALID DP PHY>" on errors. The returned string is always * non-NULL and valid. * * Returns: Name of the DP PHY. */ const char *drm_dp_phy_name(enum drm_dp_phy dp_phy) { … } EXPORT_SYMBOL(…); void drm_dp_lttpr_link_train_clock_recovery_delay(void) { … } EXPORT_SYMBOL(…); static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r) { … } void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) { … } EXPORT_SYMBOL(…); u8 drm_dp_link_rate_to_bw_code(int link_rate) { … } EXPORT_SYMBOL(…); int drm_dp_bw_code_to_link_rate(u8 link_bw) { … } EXPORT_SYMBOL(…); #define AUX_RETRY_INTERVAL … static inline void drm_dp_dump_access(const struct drm_dp_aux *aux, u8 request, uint offset, void *buffer, int ret) { … } /** * DOC: dp helpers * * The DisplayPort AUX channel is an abstraction to allow generic, driver- * independent access to AUX functionality. Drivers can take advantage of * this by filling in the fields of the drm_dp_aux structure. * * Transactions are described using a hardware-independent drm_dp_aux_msg * structure, which is passed into a driver's .transfer() implementation. * Both native and I2C-over-AUX transactions are supported. */ static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request, unsigned int offset, void *buffer, size_t size) { … } /** * drm_dp_dpcd_probe() - probe a given DPCD address with a 1-byte read access * @aux: DisplayPort AUX channel (SST) * @offset: address of the register to probe * * Probe the provided DPCD address by reading 1 byte from it. The function can * be used to trigger some side-effect the read access has, like waking up the * sink, without the need for the read-out value. * * Returns 0 if the read access suceeded, or a negative error code on failure. */ int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset) { … } EXPORT_SYMBOL(…); /** * drm_dp_dpcd_set_powered() - Set whether the DP device is powered * @aux: DisplayPort AUX channel; for convenience it's OK to pass NULL here * and the function will be a no-op. * @powered: true if powered; false if not * * If the endpoint device on the DP AUX bus is known to be powered down * then this function can be called to make future transfers fail immediately * instead of needing to time out. * * If this function is never called then a device defaults to being powered. */ void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered) { … } EXPORT_SYMBOL(…); /** * drm_dp_dpcd_read() - read a series of bytes from the DPCD * @aux: DisplayPort AUX channel (SST or MST) * @offset: address of the (first) register to read * @buffer: buffer to store the register values * @size: number of bytes in @buffer * * Returns the number of bytes transferred on success, or a negative error * code on failure. -EIO is returned if the request was NAKed by the sink or * if the retry count was exceeded. If not all bytes were transferred, this * function returns -EPROTO. Errors from the underlying AUX channel transfer * function, with the exception of -EBUSY (which causes the transaction to * be retried), are propagated to the caller. */ ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, void *buffer, size_t size) { … } EXPORT_SYMBOL(…); /** * drm_dp_dpcd_write() - write a series of bytes to the DPCD * @aux: DisplayPort AUX channel (SST or MST) * @offset: address of the (first) register to write * @buffer: buffer containing the values to write * @size: number of bytes in @buffer * * Returns the number of bytes transferred on success, or a negative error * code on failure. -EIO is returned if the request was NAKed by the sink or * if the retry count was exceeded. If not all bytes were transferred, this * function returns -EPROTO. Errors from the underlying AUX channel transfer * function, with the exception of -EBUSY (which causes the transaction to * be retried), are propagated to the caller. */ ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, void *buffer, size_t size) { … } EXPORT_SYMBOL(…); /** * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207) * @aux: DisplayPort AUX channel * @status: buffer to store the link status in (must be at least 6 bytes) * * Returns the number of bytes transferred on success or a negative error * code on failure. */ int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, u8 status[DP_LINK_STATUS_SIZE]) { … } EXPORT_SYMBOL(…); /** * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY * @aux: DisplayPort AUX channel * @dp_phy: the DP PHY to get the link status for * @link_status: buffer to return the status in * * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The * layout of the returned @link_status matches the DPCD register layout of the * DPRX PHY link status. * * Returns 0 if the information was read successfully or a negative error code * on failure. */ int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, enum drm_dp_phy dp_phy, u8 link_status[DP_LINK_STATUS_SIZE]) { … } EXPORT_SYMBOL(…); static bool is_edid_digital_input_dp(const struct drm_edid *drm_edid) { … } /** * drm_dp_downstream_is_type() - is the downstream facing port of certain type? * @dpcd: DisplayPort configuration data * @port_cap: port capabilities * @type: port type to be checked. Can be: * %DP_DS_PORT_TYPE_DP, %DP_DS_PORT_TYPE_VGA, %DP_DS_PORT_TYPE_DVI, * %DP_DS_PORT_TYPE_HDMI, %DP_DS_PORT_TYPE_NON_EDID, * %DP_DS_PORT_TYPE_DP_DUALMODE or %DP_DS_PORT_TYPE_WIRELESS. * * Caveat: Only works with DPCD 1.1+ port caps. * * Returns: whether the downstream facing port matches the type. */ bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], u8 type) { … } EXPORT_SYMBOL(…); /** * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS? * @dpcd: DisplayPort configuration data * @port_cap: port capabilities * @drm_edid: EDID * * Returns: whether the downstream facing port is TMDS (HDMI/DVI). */ bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], const struct drm_edid *drm_edid) { … } EXPORT_SYMBOL(…); /** * drm_dp_send_real_edid_checksum() - send back real edid checksum value * @aux: DisplayPort AUX channel * @real_edid_checksum: real edid checksum for the last block * * Returns: * True on success */ bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, u8 real_edid_checksum) { … } EXPORT_SYMBOL(…); static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { … } static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, u8 dpcd[DP_RECEIVER_CAP_SIZE]) { … } /** * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if * available * @aux: DisplayPort AUX channel * @dpcd: Buffer to store the resulting DPCD in * * Attempts to read the base DPCD caps for @aux. Additionally, this function * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if * present. * * Returns: %0 if the DPCD was read successfully, negative error code * otherwise. */ int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, u8 dpcd[DP_RECEIVER_CAP_SIZE]) { … } EXPORT_SYMBOL(…); /** * drm_dp_read_downstream_info() - read DPCD downstream port info if available * @aux: DisplayPort AUX channel * @dpcd: A cached copy of the port's DPCD * @downstream_ports: buffer to store the downstream port info in * * See also: * drm_dp_downstream_max_clock() * drm_dp_downstream_max_bpc() * * Returns: 0 if either the downstream port info was read successfully or * there was no downstream info to read, or a negative error code otherwise. */ int drm_dp_read_downstream_info(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]) { … } EXPORT_SYMBOL(…); /** * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock * @dpcd: DisplayPort configuration data * @port_cap: port capabilities * * Returns: Downstream facing port max dot clock in kHz on success, * or 0 if max clock not defined */ int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4]) { … } EXPORT_SYMBOL(…); /** * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock * @dpcd: DisplayPort configuration data * @port_cap: port capabilities * @drm_edid: EDID * * Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success, * or 0 if max TMDS clock not defined */ int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], const struct drm_edid *drm_edid) { … } EXPORT_SYMBOL(…); /** * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock * @dpcd: DisplayPort configuration data * @port_cap: port capabilities * @drm_edid: EDID * * Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success, * or 0 if max TMDS clock not defined */ int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], const struct drm_edid *drm_edid) { … } EXPORT_SYMBOL(…); /** * drm_dp_downstream_max_bpc() - extract downstream facing port max * bits per component * @dpcd: DisplayPort configuration data * @port_cap: downstream facing port capabilities * @drm_edid: EDID * * Returns: Max bpc on success or 0 if max bpc not defined */ int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], const struct drm_edid *drm_edid) { … } EXPORT_SYMBOL(…); /** * drm_dp_downstream_420_passthrough() - determine downstream facing port * YCbCr 4:2:0 pass-through capability * @dpcd: DisplayPort configuration data * @port_cap: downstream facing port capabilities * * Returns: whether the downstream facing port can pass through YCbCr 4:2:0 */ bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4]) { … } EXPORT_SYMBOL(…); /** * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port * YCbCr 4:4:4->4:2:0 conversion capability * @dpcd: DisplayPort configuration data * @port_cap: downstream facing port capabilities * * Returns: whether the downstream facing port can convert YCbCr 4:4:4 to 4:2:0 */ bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4]) { … } EXPORT_SYMBOL(…); /** * drm_dp_downstream_rgb_to_ycbcr_conversion() - determine downstream facing port * RGB->YCbCr conversion capability * @dpcd: DisplayPort configuration data * @port_cap: downstream facing port capabilities * @color_spc: Colorspace for which conversion cap is sought * * Returns: whether the downstream facing port can convert RGB->YCbCr for a given * colorspace. */ bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], u8 color_spc) { … } EXPORT_SYMBOL(…); /** * drm_dp_downstream_mode() - return a mode for downstream facing port * @dev: DRM device * @dpcd: DisplayPort configuration data * @port_cap: port capabilities * * Provides a suitable mode for downstream facing ports without EDID. * * Returns: A new drm_display_mode on success or NULL on failure */ struct drm_display_mode * drm_dp_downstream_mode(struct drm_device *dev, const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4]) { … } EXPORT_SYMBOL(…); /** * drm_dp_downstream_id() - identify branch device * @aux: DisplayPort AUX channel * @id: DisplayPort branch device id * * Returns branch device id on success or NULL on failure */ int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]) { … } EXPORT_SYMBOL(…); /** * drm_dp_downstream_debug() - debug DP branch devices * @m: pointer for debugfs file * @dpcd: DisplayPort configuration data * @port_cap: port capabilities * @drm_edid: EDID * @aux: DisplayPort AUX channel * */ void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], const struct drm_edid *drm_edid, struct drm_dp_aux *aux) { … } EXPORT_SYMBOL(…); /** * drm_dp_subconnector_type() - get DP branch device type * @dpcd: DisplayPort configuration data * @port_cap: port capabilities */ enum drm_mode_subconnector drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4]) { … } EXPORT_SYMBOL(…); /** * drm_dp_set_subconnector_property - set subconnector for DP connector * @connector: connector to set property on * @status: connector status * @dpcd: DisplayPort configuration data * @port_cap: port capabilities * * Called by a driver on every detect event. */ void drm_dp_set_subconnector_property(struct drm_connector *connector, enum drm_connector_status status, const u8 *dpcd, const u8 port_cap[4]) { … } EXPORT_SYMBOL(…); /** * drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink * count * @connector: The DRM connector to check * @dpcd: A cached copy of the connector's DPCD RX capabilities * @desc: A cached copy of the connector's DP descriptor * * See also: drm_dp_read_sink_count() * * Returns: %True if the (e)DP connector has a valid sink count that should * be probed, %false otherwise. */ bool drm_dp_read_sink_count_cap(struct drm_connector *connector, const u8 dpcd[DP_RECEIVER_CAP_SIZE], const struct drm_dp_desc *desc) { … } EXPORT_SYMBOL(…); /** * drm_dp_read_sink_count() - Retrieve the sink count for a given sink * @aux: The DP AUX channel to use * * See also: drm_dp_read_sink_count_cap() * * Returns: The current sink count reported by @aux, or a negative error code * otherwise. */ int drm_dp_read_sink_count(struct drm_dp_aux *aux) { … } EXPORT_SYMBOL(…); /* * I2C-over-AUX implementation */ static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter) { … } static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg) { … } #define AUX_PRECHARGE_LEN … #define AUX_SYNC_LEN … #define AUX_STOP_LEN … #define AUX_CMD_LEN … #define AUX_ADDRESS_LEN … #define AUX_REPLY_PAD_LEN … #define AUX_LENGTH_LEN … /* * Calculate the duration of the AUX request/reply in usec. Gives the * "best" case estimate, ie. successful while as short as possible. */ static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg) { … } static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg) { … } #define I2C_START_LEN … #define I2C_STOP_LEN … #define I2C_ADDR_LEN … #define I2C_DATA_LEN … /* * Calculate the length of the i2c transfer in usec, assuming * the i2c bus speed is as specified. Gives the "worst" * case estimate, ie. successful while as long as possible. * Doesn't account the "MOT" bit, and instead assumes each * message includes a START, ADDRESS and STOP. Neither does it * account for additional random variables such as clock stretching. */ static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg, int i2c_speed_khz) { … } /* * Determine how many retries should be attempted to successfully transfer * the specified message, based on the estimated durations of the * i2c and AUX transfers. */ static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg, int i2c_speed_khz) { … } /* * FIXME currently assumes 10 kHz as some real world devices seem * to require it. We should query/set the speed via DPCD if supported. */ static int dp_aux_i2c_speed_khz __read_mostly = …; module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644); MODULE_PARM_DESC(…) …; /* * Transfer a single I2C-over-AUX message and handle various error conditions, * retrying the transaction as appropriate. It is assumed that the * &drm_dp_aux.transfer function does not modify anything in the msg other than the * reply field. * * Returns bytes transferred on success, or a negative error code on failure. */ static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) { … } static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg, const struct i2c_msg *i2c_msg) { … } /* * Keep retrying drm_dp_i2c_do_msg until all data has been transferred. * * Returns an error code on failure, or a recommended transfer size on success. */ static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg) { … } /* * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX * packets to be as large as possible. If not, the I2C transactions never * succeed. Hence the default is maximum. */ static int dp_aux_i2c_transfer_size __read_mostly = …; module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644); MODULE_PARM_DESC(…) …; static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) { … } static const struct i2c_algorithm drm_dp_i2c_algo = …; static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c) { … } static void lock_bus(struct i2c_adapter *i2c, unsigned int flags) { … } static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags) { … } static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags) { … } static const struct i2c_lock_operations drm_dp_i2c_lock_ops = …; static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc) { … } static void drm_dp_aux_crc_work(struct work_struct *work) { … } /** * drm_dp_remote_aux_init() - minimally initialise a remote aux channel * @aux: DisplayPort AUX channel * * Used for remote aux channel in general. Merely initialize the crc work * struct. */ void drm_dp_remote_aux_init(struct drm_dp_aux *aux) { … } EXPORT_SYMBOL(…); /** * drm_dp_aux_init() - minimally initialise an aux channel * @aux: DisplayPort AUX channel * * If you need to use the drm_dp_aux's i2c adapter prior to registering it with * the outside world, call drm_dp_aux_init() first. For drivers which are * grandparents to their AUX adapters (e.g. the AUX adapter is parented by a * &drm_connector), you must still call drm_dp_aux_register() once the connector * has been registered to allow userspace access to the auxiliary DP channel. * Likewise, for such drivers you should also assign &drm_dp_aux.drm_dev as * early as possible so that the &drm_device that corresponds to the AUX adapter * may be mentioned in debugging output from the DRM DP helpers. * * For devices which use a separate platform device for their AUX adapters, this * may be called as early as required by the driver. * */ void drm_dp_aux_init(struct drm_dp_aux *aux) { … } EXPORT_SYMBOL(…); /** * drm_dp_aux_register() - initialise and register aux channel * @aux: DisplayPort AUX channel * * Automatically calls drm_dp_aux_init() if this hasn't been done yet. This * should only be called once the parent of @aux, &drm_dp_aux.dev, is * initialized. For devices which are grandparents of their AUX channels, * &drm_dp_aux.dev will typically be the &drm_connector &device which * corresponds to @aux. For these devices, it's advised to call * drm_dp_aux_register() in &drm_connector_funcs.late_register, and likewise to * call drm_dp_aux_unregister() in &drm_connector_funcs.early_unregister. * Functions which don't follow this will likely Oops when * %CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is enabled. * * For devices where the AUX channel is a device that exists independently of * the &drm_device that uses it, such as SoCs and bridge devices, it is * recommended to call drm_dp_aux_register() after a &drm_device has been * assigned to &drm_dp_aux.drm_dev, and likewise to call * drm_dp_aux_unregister() once the &drm_device should no longer be associated * with the AUX channel (e.g. on bridge detach). * * Drivers which need to use the aux channel before either of the two points * mentioned above need to call drm_dp_aux_init() in order to use the AUX * channel before registration. * * Returns 0 on success or a negative error code on failure. */ int drm_dp_aux_register(struct drm_dp_aux *aux) { … } EXPORT_SYMBOL(…); /** * drm_dp_aux_unregister() - unregister an AUX adapter * @aux: DisplayPort AUX channel */ void drm_dp_aux_unregister(struct drm_dp_aux *aux) { … } EXPORT_SYMBOL(…); #define PSR_SETUP_TIME … /** * drm_dp_psr_setup_time() - PSR setup in time usec * @psr_cap: PSR capabilities from DPCD * * Returns: * PSR setup time for the panel in microseconds, negative * error code on failure. */ int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]) { … } EXPORT_SYMBOL(…); #undef PSR_SETUP_TIME /** * drm_dp_start_crc() - start capture of frame CRCs * @aux: DisplayPort AUX channel * @crtc: CRTC displaying the frames whose CRCs are to be captured * * Returns 0 on success or a negative error code on failure. */ int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc) { … } EXPORT_SYMBOL(…); /** * drm_dp_stop_crc() - stop capture of frame CRCs * @aux: DisplayPort AUX channel * * Returns 0 on success or a negative error code on failure. */ int drm_dp_stop_crc(struct drm_dp_aux *aux) { … } EXPORT_SYMBOL(…); struct dpcd_quirk { … }; #define OUI … #define DEVICE_ID … #define DEVICE_ID_ANY … static const struct dpcd_quirk dpcd_quirk_list[] = …; #undef OUI /* * Get a bit mask of DPCD quirks for the sink/branch device identified by * ident. The quirk data is shared but it's up to the drivers to act on the * data. * * For now, only the OUI (first three bytes) is used, but this may be extended * to device identification string and hardware/firmware revisions later. */ static u32 drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch) { … } #undef DEVICE_ID_ANY #undef DEVICE_ID /** * drm_dp_read_desc - read sink/branch descriptor from DPCD * @aux: DisplayPort AUX channel * @desc: Device descriptor to fill from DPCD * @is_branch: true for branch devices, false for sink devices * * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the * identification. * * Returns 0 on success or a negative error code on failure. */ int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, bool is_branch) { … } EXPORT_SYMBOL(…); /** * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment * @dsc_dpcd: DSC capabilities from DPCD * * Returns the bpp precision supported by the DP sink. */ u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) { … } EXPORT_SYMBOL(…); /** * drm_dp_dsc_sink_max_slice_count() - Get the max slice count * supported by the DSC sink. * @dsc_dpcd: DSC capabilities from DPCD * @is_edp: true if its eDP, false for DP * * Read the slice capabilities DPCD register from DSC sink to get * the maximum slice count supported. This is used to populate * the DSC parameters in the &struct drm_dsc_config by the driver. * Driver creates an infoframe using these parameters to populate * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC * infoframe using the helper function drm_dsc_pps_infoframe_pack() * * Returns: * Maximum slice count supported by DSC sink or 0 its invalid */ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], bool is_edp) { … } EXPORT_SYMBOL(…); /** * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits * @dsc_dpcd: DSC capabilities from DPCD * * Read the DSC DPCD register to parse the line buffer depth in bits which is * number of bits of precision within the decoder line buffer supported by * the DSC sink. This is used to populate the DSC parameters in the * &struct drm_dsc_config by the driver. * Driver creates an infoframe using these parameters to populate * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC * infoframe using the helper function drm_dsc_pps_infoframe_pack() * * Returns: * Line buffer depth supported by DSC panel or 0 its invalid */ u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) { … } EXPORT_SYMBOL(…); /** * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component * values supported by the DSC sink. * @dsc_dpcd: DSC capabilities from DPCD * @dsc_bpc: An array to be filled by this helper with supported * input bpcs. * * Read the DSC DPCD from the sink device to parse the supported bits per * component values. This is used to populate the DSC parameters * in the &struct drm_dsc_config by the driver. * Driver creates an infoframe using these parameters to populate * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC * infoframe using the helper function drm_dsc_pps_infoframe_pack() * * Returns: * Number of input BPC values parsed from the DPCD */ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 dsc_bpc[3]) { … } EXPORT_SYMBOL(…); static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address, u8 *buf, int buf_size) { … } /** * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities * @aux: DisplayPort AUX channel * @dpcd: DisplayPort configuration data * @caps: buffer to return the capability info in * * Read capabilities common to all LTTPRs. * * Returns 0 on success or a negative error code on failure. */ int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) { … } EXPORT_SYMBOL(…); /** * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY * @aux: DisplayPort AUX channel * @dpcd: DisplayPort configuration data * @dp_phy: LTTPR PHY to read the capabilities for * @caps: buffer to return the capability info in * * Read the capabilities for the given LTTPR PHY. * * Returns 0 on success or a negative error code on failure. */ int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], enum drm_dp_phy dp_phy, u8 caps[DP_LTTPR_PHY_CAP_SIZE]) { … } EXPORT_SYMBOL(…); static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r) { … } /** * drm_dp_lttpr_count - get the number of detected LTTPRs * @caps: LTTPR common capabilities * * Get the number of detected LTTPRs from the LTTPR common capabilities info. * * Returns: * -ERANGE if more than supported number (8) of LTTPRs are detected * -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value * otherwise the number of detected LTTPRs */ int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) { … } EXPORT_SYMBOL(…); /** * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs * @caps: LTTPR common capabilities * * Returns the maximum link rate supported by all detected LTTPRs. */ int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) { … } EXPORT_SYMBOL(…); /** * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs * @caps: LTTPR common capabilities * * Returns the maximum lane count supported by all detected LTTPRs. */ int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) { … } EXPORT_SYMBOL(…); /** * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support * @caps: LTTPR PHY capabilities * * Returns true if the @caps for an LTTPR TX PHY indicate support for * voltage swing level 3. */ bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]) { … } EXPORT_SYMBOL(…); /** * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support * @caps: LTTPR PHY capabilities * * Returns true if the @caps for an LTTPR TX PHY indicate support for * pre-emphasis level 3. */ bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]) { … } EXPORT_SYMBOL(…); /** * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink. * @aux: DisplayPort AUX channel * @data: DP phy compliance test parameters. * * Returns 0 on success or a negative error code on failure. */ int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, struct drm_dp_phy_test_params *data) { … } EXPORT_SYMBOL(…); /** * drm_dp_set_phy_test_pattern() - set the pattern to the sink. * @aux: DisplayPort AUX channel * @data: DP phy compliance test parameters. * @dp_rev: DP revision to use for compliance testing * * Returns 0 on success or a negative error code on failure. */ int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, struct drm_dp_phy_test_params *data, u8 dp_rev) { … } EXPORT_SYMBOL(…); static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat) { … } static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat, enum dp_colorimetry colorimetry) { … } static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range) { … } static const char *dp_content_type_get_name(enum dp_content_type content_type) { … } void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc) { … } EXPORT_SYMBOL(…); void drm_dp_as_sdp_log(struct drm_printer *p, const struct drm_dp_as_sdp *as_sdp) { … } EXPORT_SYMBOL(…); /** * drm_dp_as_sdp_supported() - check if adaptive sync sdp is supported * @aux: DisplayPort AUX channel * @dpcd: DisplayPort configuration data * * Returns true if adaptive sync sdp is supported, else returns false */ bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { … } EXPORT_SYMBOL(…); /** * drm_dp_vsc_sdp_supported() - check if vsc sdp is supported * @aux: DisplayPort AUX channel * @dpcd: DisplayPort configuration data * * Returns true if vsc sdp is supported, else returns false */ bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { … } EXPORT_SYMBOL(…); /** * drm_dp_vsc_sdp_pack() - pack a given vsc sdp into generic dp_sdp * @vsc: vsc sdp initialized according to its purpose as defined in * table 2-118 - table 2-120 in DP 1.4a specification * @sdp: valid handle to the generic dp_sdp which will be packed * * Returns length of sdp on success and error code on failure */ ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, struct dp_sdp *sdp) { … } EXPORT_SYMBOL(…); /** * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON * @dpcd: DisplayPort configuration data * @port_cap: port capabilities * * Returns maximum frl bandwidth supported by PCON in GBPS, * returns 0 if not supported. */ int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4]) { … } EXPORT_SYMBOL(…); /** * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL. * @aux: DisplayPort AUX channel * @enable_frl_ready_hpd: Configure DP_PCON_ENABLE_HPD_READY. * * Returns 0 if success, else returns negative error code. */ int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd) { … } EXPORT_SYMBOL(…); /** * drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL * @aux: DisplayPort AUX channel * * Returns true if success, else returns false. */ bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux) { … } EXPORT_SYMBOL(…); /** * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1 * @aux: DisplayPort AUX channel * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential. * In Concurrent Mode, the FRL link bring up can be done along with * DP Link training. In Sequential mode, the FRL link bring up is done prior to * the DP Link training. * * Returns 0 if success, else returns negative error code. */ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, u8 frl_mode) { … } EXPORT_SYMBOL(…); /** * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2 * @aux: DisplayPort AUX channel * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink * @frl_type : FRL training type, can be Extended, or Normal. * In Normal FRL training, the PCON tries each frl bw from the max_frl_mask * starting from min, and stops when link training is successful. In Extended * FRL training, all frl bw selected in the mask are trained by the PCON. * * Returns 0 if success, else returns negative error code. */ int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, u8 frl_type) { … } EXPORT_SYMBOL(…); /** * drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration. * @aux: DisplayPort AUX channel * * Returns 0 if success, else returns negative error code. */ int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux) { … } EXPORT_SYMBOL(…); /** * drm_dp_pcon_frl_enable() - Enable HDMI link through FRL * @aux: DisplayPort AUX channel * * Returns 0 if success, else returns negative error code. */ int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux) { … } EXPORT_SYMBOL(…); /** * drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is active. * @aux: DisplayPort AUX channel * * Returns true if link is active else returns false. */ bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux) { … } EXPORT_SYMBOL(…); /** * drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE * @aux: DisplayPort AUX channel * @frl_trained_mask: pointer to store bitmask of the trained bw configuration. * Valid only if the MODE returned is FRL. For Normal Link training mode * only 1 of the bits will be set, but in case of Extended mode, more than * one bits can be set. * * Returns the link mode : TMDS or FRL on success, else returns negative error * code. */ int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask) { … } EXPORT_SYMBOL(…); /** * drm_dp_pcon_hdmi_frl_link_error_count() - print the error count per lane * during link failure between PCON and HDMI sink * @aux: DisplayPort AUX channel * @connector: DRM connector * code. **/ void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, struct drm_connector *connector) { … } EXPORT_SYMBOL(…); /* * drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder * * Returns true is PCON encoder is DSC 1.2 else returns false. */ bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) { … } EXPORT_SYMBOL(…); /* * drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC Encoder * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder * * Returns maximum no. of slices supported by the PCON DSC Encoder. */ int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) { … } EXPORT_SYMBOL(…); /* * drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC encoder * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder * * Returns maximum width of the slices in pixel width i.e. no. of pixels x 320. */ int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) { … } EXPORT_SYMBOL(…); /* * drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON DSC encoder * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder * * Returns the bpp precision supported by the PCON encoder. */ int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) { … } EXPORT_SYMBOL(…); static int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config) { … } /** * drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters * for DSC1.2 between PCON & HDMI2.1 sink * @aux: DisplayPort AUX channel * * Returns 0 on success, else returns negative error code. */ int drm_dp_pcon_pps_default(struct drm_dp_aux *aux) { … } EXPORT_SYMBOL(…); /** * drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for * HDMI sink * @aux: DisplayPort AUX channel * @pps_buf: 128 bytes to be written into PPS buffer for HDMI sink by PCON. * * Returns 0 on success, else returns negative error code. */ int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]) { … } EXPORT_SYMBOL(…); /* * drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder * override registers * @aux: DisplayPort AUX channel * @pps_param: 3 Parameters (2 Bytes each) : Slice Width, Slice Height, * bits_per_pixel. * * Returns 0 on success, else returns negative error code. */ int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]) { … } EXPORT_SYMBOL(…); /* * drm_dp_pcon_convert_rgb_to_ycbcr() - Configure the PCon to convert RGB to Ycbcr * @aux: displayPort AUX channel * @color_spc: Color-space/s for which conversion is to be enabled, 0 for disable. * * Returns 0 on success, else returns negative error code. */ int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc) { … } EXPORT_SYMBOL(…); /** * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX * @aux: The DP AUX channel to use * @bl: Backlight capability info from drm_edp_backlight_init() * @level: The brightness level to set * * Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must * already have been enabled by the driver by calling drm_edp_backlight_enable(). * * Returns: %0 on success, negative error code on failure */ int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, u16 level) { … } EXPORT_SYMBOL(…); static int drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, bool enable) { … } /** * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD * @aux: The DP AUX channel to use * @bl: Backlight capability info from drm_edp_backlight_init() * @level: The initial backlight level to set via AUX, if there is one * * This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally * restoring any important backlight state such as the given backlight level, the brightness byte * count, backlight frequency, etc. * * Note that certain panels do not support being enabled or disabled via DPCD, but instead require * that the driver handle enabling/disabling the panel through implementation-specific means using * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false, * this function becomes a no-op, and the driver is expected to handle powering the panel on using * the EDP_BL_PWR GPIO. * * Returns: %0 on success, negative error code on failure. */ int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, const u16 level) { … } EXPORT_SYMBOL(…); /** * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported * @aux: The DP AUX channel to use * @bl: Backlight capability info from drm_edp_backlight_init() * * This function handles disabling DPCD backlight controls on a panel over AUX. * * Note that certain panels do not support being enabled or disabled via DPCD, but instead require * that the driver handle enabling/disabling the panel through implementation-specific means using * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false, * this function becomes a no-op, and the driver is expected to handle powering the panel off using * the EDP_BL_PWR GPIO. * * Returns: %0 on success or no-op, negative error code on failure. */ int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl) { … } EXPORT_SYMBOL(…); static inline int drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) { … } static inline int drm_edp_backlight_probe_state(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, u8 *current_mode) { … } /** * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight * interface. * @aux: The DP aux device to use for probing * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz * @edp_dpcd: A cached copy of the eDP DPCD * @current_level: Where to store the probed brightness level, if any * @current_mode: Where to store the currently set backlight control mode * * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities, * along with also probing the current and maximum supported brightness levels. * * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the * default frequency from the panel is used. * * Returns: %0 on success, negative error code on failure. */ int drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE], u16 *current_level, u8 *current_mode) { … } EXPORT_SYMBOL(…); #if IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)) static int dp_aux_backlight_update_status(struct backlight_device *bd) { … } static const struct backlight_ops dp_aux_bl_ops = …; /** * drm_panel_dp_aux_backlight - create and use DP AUX backlight * @panel: DRM panel * @aux: The DP AUX channel to use * * Use this function to create and handle backlight if your panel * supports backlight control over DP AUX channel using DPCD * registers as per VESA's standard backlight control interface. * * When the panel is enabled backlight will be enabled after a * successful call to &drm_panel_funcs.enable() * * When the panel is disabled backlight will be disabled before the * call to &drm_panel_funcs.disable(). * * A typical implementation for a panel driver supporting backlight * control over DP AUX will call this function at probe time. * Backlight will then be handled transparently without requiring * any intervention from the driver. * * drm_panel_dp_aux_backlight() must be called after the call to drm_panel_init(). * * Return: 0 on success or a negative error code on failure. */ int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux) { … } EXPORT_SYMBOL(…); #endif /* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */ static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16, int symbol_size, bool is_mst) { … } static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count, int bpp_x16, int symbol_size, bool is_mst) { … } /** * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream * @lane_count: DP link lane count * @hactive: pixel count of the active period in one scanline of the stream * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set * @bpp_x16: bits per pixel in .4 binary fixed point * @flags: DRM_DP_OVERHEAD_x flags * * Calculate the BW allocation overhead of a DP link stream, depending * on the link's * - @lane_count * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST) * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR) * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC) * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK) * as well as the stream's * - @hactive timing * - @bpp_x16 color depth * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC). * Note that this overhead doesn't account for the 8b/10b, 128b/132b * channel coding efficiency, for that see * @drm_dp_link_bw_channel_coding_efficiency(). * * Returns the overhead as 100% + overhead% in 1ppm units. */ int drm_dp_bw_overhead(int lane_count, int hactive, int dsc_slice_count, int bpp_x16, unsigned long flags) { … } EXPORT_SYMBOL(…); /** * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency * @is_uhbr: Whether the link has a 128b/132b channel coding * * Return the channel coding efficiency of the given DP link type, which is * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead * and for 128b/132b any link or PHY level control symbol insertion overhead * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the * corresponding FEC overhead is BW allocation specific, included in the value * returned by drm_dp_bw_overhead(). * * Returns the efficiency in the 100%/coding-overhead% ratio in * 1ppm units. */ int drm_dp_bw_channel_coding_efficiency(bool is_uhbr) { … } EXPORT_SYMBOL(…); /** * drm_dp_max_dprx_data_rate - Get the max data bandwidth of a DPRX sink * @max_link_rate: max DPRX link rate in 10kbps units * @max_lanes: max DPRX lane count * * Given a link rate and lanes, get the data bandwidth. * * Data bandwidth is the actual payload rate, which depends on the data * bandwidth efficiency and the link rate. * * Note that protocol layers above the DPRX link level considered here can * further limit the maximum data rate. Such layers are the MST topology (with * limits on the link between the source and first branch device as well as on * the whole MST path until the DPRX link) and (Thunderbolt) DP tunnels - * which in turn can encapsulate an MST link with its own limit - with each * SST or MST encapsulated tunnel sharing the BW of a tunnel group. * * Returns the maximum data rate in kBps units. */ int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes) { … } EXPORT_SYMBOL(…);
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