/* * Copyright 2005 Nicolai Haehnle et al. * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Nicolai Haehnle * Jerome Glisse */ #ifndef _R300_REG_H_ #define _R300_REG_H_ #define R300_SURF_TILE_MACRO … #define R300_SURF_TILE_MICRO … #define R300_SURF_TILE_BOTH … #define R300_MC_INIT_MISC_LAT_TIMER … #define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT … #define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT … #define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT … #define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT … #define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT … #define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT … #define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT … #define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT … #define R300_MC_INIT_GFX_LAT_TIMER … #define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT … #define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT … #define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT … #define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT … #define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT … #define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT … #define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT … #define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT … /* * This file contains registers and constants for the R300. They have been * found mostly by examining command buffers captured using glxtest, as well * as by extrapolating some known registers and constants from the R200. * I am fairly certain that they are correct unless stated otherwise * in comments. */ #define R300_SE_VPORT_XSCALE … #define R300_SE_VPORT_XOFFSET … #define R300_SE_VPORT_YSCALE … #define R300_SE_VPORT_YOFFSET … #define R300_SE_VPORT_ZSCALE … #define R300_SE_VPORT_ZOFFSET … /* * Vertex Array Processing (VAP) Control * Stolen from r200 code from Christoph Brill (It's a guess!) */ #define R300_VAP_CNTL … /* This register is written directly and also starts data section * in many 3d CP_PACKET3's */ #define R300_VAP_VF_CNTL … #define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT … #define R300_VAP_VF_CNTL__PRIM_NONE … #define R300_VAP_VF_CNTL__PRIM_POINTS … #define R300_VAP_VF_CNTL__PRIM_LINES … #define R300_VAP_VF_CNTL__PRIM_LINE_STRIP … #define R300_VAP_VF_CNTL__PRIM_TRIANGLES … #define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN … #define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP … #define R300_VAP_VF_CNTL__PRIM_LINE_LOOP … #define R300_VAP_VF_CNTL__PRIM_QUADS … #define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP … #define R300_VAP_VF_CNTL__PRIM_POLYGON … #define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT … /* State based - direct writes to registers trigger vertex generation */ #define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED … #define R300_VAP_VF_CNTL__PRIM_WALK_INDICES … #define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST … #define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED … /* I don't think I saw these three used.. */ #define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT … #define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT … #define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT … /* index size - when not set the indices are assumed to be 16 bit */ #define R300_VAP_VF_CNTL__INDEX_SIZE_32bit … /* number of vertices */ #define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT … /* BEGIN: Wild guesses */ #define R300_VAP_OUTPUT_VTX_FMT_0 … #define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT … #define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT … #define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT … #define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT … #define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT … #define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT … #define R300_VAP_OUTPUT_VTX_FMT_1 … /* each of the following is 3 bits wide, specifies number of components */ #define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT … #define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT … #define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT … #define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT … #define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT … #define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT … #define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT … #define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT … /* END: Wild guesses */ #define R300_SE_VTE_CNTL … #define R300_VPORT_X_SCALE_ENA … #define R300_VPORT_X_OFFSET_ENA … #define R300_VPORT_Y_SCALE_ENA … #define R300_VPORT_Y_OFFSET_ENA … #define R300_VPORT_Z_SCALE_ENA … #define R300_VPORT_Z_OFFSET_ENA … #define R300_VTX_XY_FMT … #define R300_VTX_Z_FMT … #define R300_VTX_W0_FMT … #define R300_VTX_W0_NORMALIZE … #define R300_VTX_ST_DENORMALIZED … /* BEGIN: Vertex data assembly - lots of uncertainties */ /* gap */ #define R300_VAP_CNTL_STATUS … #define R300_VC_NO_SWAP … #define R300_VC_16BIT_SWAP … #define R300_VC_32BIT_SWAP … #define R300_VAP_TCL_BYPASS … /* gap */ /* Where do we get our vertex data? * * Vertex data either comes either from immediate mode registers or from * vertex arrays. * There appears to be no mixed mode (though we can force the pitch of * vertex arrays to 0, effectively reusing the same element over and over * again). * * Immediate mode is controlled by the INPUT_CNTL registers. I am not sure * if these registers influence vertex array processing. * * Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3. * * In both cases, vertex attributes are then passed through INPUT_ROUTE. * * Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data * into the vertex processor's input registers. * The first word routes the first input, the second word the second, etc. * The corresponding input is routed into the register with the given index. * The list is ended by a word with INPUT_ROUTE_END set. * * Always set COMPONENTS_4 in immediate mode. */ #define R300_VAP_INPUT_ROUTE_0_0 … #define R300_INPUT_ROUTE_COMPONENTS_1 … #define R300_INPUT_ROUTE_COMPONENTS_2 … #define R300_INPUT_ROUTE_COMPONENTS_3 … #define R300_INPUT_ROUTE_COMPONENTS_4 … #define R300_INPUT_ROUTE_COMPONENTS_RGBA … #define R300_VAP_INPUT_ROUTE_IDX_SHIFT … #define R300_VAP_INPUT_ROUTE_IDX_MASK … #define R300_VAP_INPUT_ROUTE_END … #define R300_INPUT_ROUTE_IMMEDIATE_MODE … #define R300_INPUT_ROUTE_FLOAT … #define R300_INPUT_ROUTE_UNSIGNED_BYTE … #define R300_INPUT_ROUTE_FLOAT_COLOR … #define R300_VAP_INPUT_ROUTE_0_1 … #define R300_VAP_INPUT_ROUTE_0_2 … #define R300_VAP_INPUT_ROUTE_0_3 … #define R300_VAP_INPUT_ROUTE_0_4 … #define R300_VAP_INPUT_ROUTE_0_5 … #define R300_VAP_INPUT_ROUTE_0_6 … #define R300_VAP_INPUT_ROUTE_0_7 … /* gap */ /* Notes: * - always set up to produce at least two attributes: * if vertex program uses only position, fglrx will set normal, too * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal. */ #define R300_VAP_INPUT_CNTL_0 … #define R300_INPUT_CNTL_0_COLOR … #define R300_VAP_INPUT_CNTL_1 … #define R300_INPUT_CNTL_POS … #define R300_INPUT_CNTL_NORMAL … #define R300_INPUT_CNTL_COLOR … #define R300_INPUT_CNTL_TC0 … #define R300_INPUT_CNTL_TC1 … #define R300_INPUT_CNTL_TC2 … #define R300_INPUT_CNTL_TC3 … #define R300_INPUT_CNTL_TC4 … #define R300_INPUT_CNTL_TC5 … #define R300_INPUT_CNTL_TC6 … #define R300_INPUT_CNTL_TC7 … /* gap */ /* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0 * are set to a swizzling bit pattern, other words are 0. * * In immediate mode, the pattern is always set to xyzw. In vertex array * mode, the swizzling pattern is e.g. used to set zw components in texture * coordinates with only tweo components. */ #define R300_VAP_INPUT_ROUTE_1_0 … #define R300_INPUT_ROUTE_SELECT_X … #define R300_INPUT_ROUTE_SELECT_Y … #define R300_INPUT_ROUTE_SELECT_Z … #define R300_INPUT_ROUTE_SELECT_W … #define R300_INPUT_ROUTE_SELECT_ZERO … #define R300_INPUT_ROUTE_SELECT_ONE … #define R300_INPUT_ROUTE_SELECT_MASK … #define R300_INPUT_ROUTE_X_SHIFT … #define R300_INPUT_ROUTE_Y_SHIFT … #define R300_INPUT_ROUTE_Z_SHIFT … #define R300_INPUT_ROUTE_W_SHIFT … #define R300_INPUT_ROUTE_ENABLE … #define R300_VAP_INPUT_ROUTE_1_1 … #define R300_VAP_INPUT_ROUTE_1_2 … #define R300_VAP_INPUT_ROUTE_1_3 … #define R300_VAP_INPUT_ROUTE_1_4 … #define R300_VAP_INPUT_ROUTE_1_5 … #define R300_VAP_INPUT_ROUTE_1_6 … #define R300_VAP_INPUT_ROUTE_1_7 … /* END: Vertex data assembly */ /* gap */ /* BEGIN: Upload vertex program and data */ /* * The programmable vertex shader unit has a memory bank of unknown size * that can be written to in 16 byte units by writing the address into * UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs). * * Pointers into the memory bank are always in multiples of 16 bytes. * * The memory bank is divided into areas with fixed meaning. * * Starting at address UPLOAD_PROGRAM: Vertex program instructions. * Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB), * whereas the difference between known addresses suggests size 512. * * Starting at address UPLOAD_PARAMETERS: Vertex program parameters. * Native reported limits and the VPI layout suggest size 256, whereas * difference between known addresses suggests size 512. * * At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the * floating point pointsize. The exact purpose of this state is uncertain, * as there is also the R300_RE_POINTSIZE register. * * Multiple vertex programs and parameter sets can be loaded at once, * which could explain the size discrepancy. */ #define R300_VAP_PVS_UPLOAD_ADDRESS … #define R300_PVS_UPLOAD_PROGRAM … #define R300_PVS_UPLOAD_PARAMETERS … #define R300_PVS_UPLOAD_POINTSIZE … /* gap */ #define R300_VAP_PVS_UPLOAD_DATA … /* END: Upload vertex program and data */ /* gap */ /* I do not know the purpose of this register. However, I do know that * it is set to 221C_CLEAR for clear operations and to 221C_NORMAL * for normal rendering. */ #define R300_VAP_UNKNOWN_221C … #define R300_221C_NORMAL … #define R300_221C_CLEAR … /* These seem to be per-pixel and per-vertex X and Y clipping planes. The first * plane is per-pixel and the second plane is per-vertex. * * This was determined by experimentation alone but I believe it is correct. * * These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest. */ #define R300_VAP_CLIP_X_0 … #define R300_VAP_CLIP_X_1 … #define R300_VAP_CLIP_Y_0 … #define R300_VAP_CLIP_Y_1 … /* gap */ /* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between * rendering commands and overwriting vertex program parameters. * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and * avoids bugs caused by still running shaders reading bad data from memory. */ #define R300_VAP_PVS_STATE_FLUSH_REG … /* Absolutely no clue what this register is about. */ #define R300_VAP_UNKNOWN_2288 … #define R300_2288_R300 … #define R300_2288_RV350 … /* gap */ /* Addresses are relative to the vertex program instruction area of the * memory bank. PROGRAM_END points to the last instruction of the active * program * * The meaning of the two UNKNOWN fields is obviously not known. However, * experiments so far have shown that both *must* point to an instruction * inside the vertex program, otherwise the GPU locks up. * * fglrx usually sets CNTL_3_UNKNOWN to the end of the program and * R300_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to * position takes place. * * Most likely this is used to ignore rest of the program in cases * where group of verts arent visible. For some reason this "section" * is sometimes accepted other instruction that have no relationship with * position calculations. */ #define R300_VAP_PVS_CNTL_1 … #define R300_PVS_CNTL_1_PROGRAM_START_SHIFT … #define R300_PVS_CNTL_1_POS_END_SHIFT … #define R300_PVS_CNTL_1_PROGRAM_END_SHIFT … /* Addresses are relative the vertex program parameters area. */ #define R300_VAP_PVS_CNTL_2 … #define R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT … #define R300_PVS_CNTL_2_PARAM_COUNT_SHIFT … #define R300_VAP_PVS_CNTL_3 … #define R300_PVS_CNTL_3_PROGRAM_UNKNOWN_SHIFT … #define R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT … /* The entire range from 0x2300 to 0x2AC inclusive seems to be used for * immediate vertices */ #define R300_VAP_VTX_COLOR_R … #define R300_VAP_VTX_COLOR_G … #define R300_VAP_VTX_COLOR_B … #define R300_VAP_VTX_POS_0_X_1 … #define R300_VAP_VTX_POS_0_Y_1 … #define R300_VAP_VTX_COLOR_PKD … #define R300_VAP_VTX_POS_0_X_2 … #define R300_VAP_VTX_POS_0_Y_2 … #define R300_VAP_VTX_POS_0_Z_2 … /* write 0 to indicate end of packet? */ #define R300_VAP_VTX_END_OF_PKT … /* gap */ /* These are values from r300_reg/r300_reg.h - they are known to be correct * and are here so we can use one register file instead of several * - Vladimir */ #define R300_GB_VAP_RASTER_VTX_FMT_0 … #define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT … #define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT … #define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT … #define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT … #define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT … #define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE … #define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT … #define R300_GB_VAP_RASTER_VTX_FMT_1 … /* each of the following is 3 bits wide, specifies number of components */ #define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT … #define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT … #define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT … #define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT … #define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT … #define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT … #define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT … #define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT … /* UNK30 seems to enables point to quad transformation on textures * (or something closely related to that). * This bit is rather fatal at the time being due to lackings at pixel * shader side */ #define R300_GB_ENABLE … #define R300_GB_POINT_STUFF_ENABLE … #define R300_GB_LINE_STUFF_ENABLE … #define R300_GB_TRIANGLE_STUFF_ENABLE … #define R300_GB_STENCIL_AUTO_ENABLE … #define R300_GB_UNK31 … /* each of the following is 2 bits wide */ #define R300_GB_TEX_REPLICATE … #define R300_GB_TEX_ST … #define R300_GB_TEX_STR … #define R300_GB_TEX0_SOURCE_SHIFT … #define R300_GB_TEX1_SOURCE_SHIFT … #define R300_GB_TEX2_SOURCE_SHIFT … #define R300_GB_TEX3_SOURCE_SHIFT … #define R300_GB_TEX4_SOURCE_SHIFT … #define R300_GB_TEX5_SOURCE_SHIFT … #define R300_GB_TEX6_SOURCE_SHIFT … #define R300_GB_TEX7_SOURCE_SHIFT … /* MSPOS - positions for multisample antialiasing (?) */ #define R300_GB_MSPOS0 … /* shifts - each of the fields is 4 bits */ #define R300_GB_MSPOS0__MS_X0_SHIFT … #define R300_GB_MSPOS0__MS_Y0_SHIFT … #define R300_GB_MSPOS0__MS_X1_SHIFT … #define R300_GB_MSPOS0__MS_Y1_SHIFT … #define R300_GB_MSPOS0__MS_X2_SHIFT … #define R300_GB_MSPOS0__MS_Y2_SHIFT … #define R300_GB_MSPOS0__MSBD0_Y … #define R300_GB_MSPOS0__MSBD0_X … #define R300_GB_MSPOS1 … #define R300_GB_MSPOS1__MS_X3_SHIFT … #define R300_GB_MSPOS1__MS_Y3_SHIFT … #define R300_GB_MSPOS1__MS_X4_SHIFT … #define R300_GB_MSPOS1__MS_Y4_SHIFT … #define R300_GB_MSPOS1__MS_X5_SHIFT … #define R300_GB_MSPOS1__MS_Y5_SHIFT … #define R300_GB_MSPOS1__MSBD1 … #define R300_GB_TILE_CONFIG … #define R300_GB_TILE_ENABLE … #define R300_GB_TILE_PIPE_COUNT_RV300 … #define R300_GB_TILE_PIPE_COUNT_R300 … #define R300_GB_TILE_PIPE_COUNT_R420 … #define R300_GB_TILE_PIPE_COUNT_RV410 … #define R300_GB_TILE_SIZE_8 … #define R300_GB_TILE_SIZE_16 … #define R300_GB_TILE_SIZE_32 … #define R300_GB_SUPER_SIZE_1 … #define R300_GB_SUPER_SIZE_2 … #define R300_GB_SUPER_SIZE_4 … #define R300_GB_SUPER_SIZE_8 … #define R300_GB_SUPER_SIZE_16 … #define R300_GB_SUPER_SIZE_32 … #define R300_GB_SUPER_SIZE_64 … #define R300_GB_SUPER_SIZE_128 … #define R300_GB_SUPER_X_SHIFT … #define R300_GB_SUPER_Y_SHIFT … #define R300_GB_SUPER_TILE_A … #define R300_GB_SUPER_TILE_B … #define R300_GB_SUBPIXEL_1_12 … #define R300_GB_SUBPIXEL_1_16 … #define R300_GB_FIFO_SIZE … /* each of the following is 2 bits wide */ #define R300_GB_FIFO_SIZE_32 … #define R300_GB_FIFO_SIZE_64 … #define R300_GB_FIFO_SIZE_128 … #define R300_GB_FIFO_SIZE_256 … #define R300_SC_IFIFO_SIZE_SHIFT … #define R300_SC_TZFIFO_SIZE_SHIFT … #define R300_SC_BFIFO_SIZE_SHIFT … #define R300_US_OFIFO_SIZE_SHIFT … #define R300_US_WFIFO_SIZE_SHIFT … /* the following use the same constants as above, but meaning is is times 2 (i.e. instead of 32 words it means 64 */ #define R300_RS_TFIFO_SIZE_SHIFT … #define R300_RS_CFIFO_SIZE_SHIFT … #define R300_US_RAM_SIZE_SHIFT … /* watermarks, 3 bits wide */ #define R300_RS_HIGHWATER_COL_SHIFT … #define R300_RS_HIGHWATER_TEX_SHIFT … #define R300_OFIFO_HIGHWATER_SHIFT … #define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT … #define R300_GB_SELECT … #define R300_GB_FOG_SELECT_C0A … #define R300_GB_FOG_SELECT_C1A … #define R300_GB_FOG_SELECT_C2A … #define R300_GB_FOG_SELECT_C3A … #define R300_GB_FOG_SELECT_1_1_W … #define R300_GB_FOG_SELECT_Z … #define R300_GB_DEPTH_SELECT_Z … #define R300_GB_DEPTH_SELECT_1_1_W … #define R300_GB_W_SELECT_1_W … #define R300_GB_W_SELECT_1 … #define R300_GB_AA_CONFIG … #define R300_AA_DISABLE … #define R300_AA_ENABLE … #define R300_AA_SUBSAMPLES_2 … #define R300_AA_SUBSAMPLES_3 … #define R300_AA_SUBSAMPLES_4 … #define R300_AA_SUBSAMPLES_6 … /* gap */ /* Zero to flush caches. */ #define R300_TX_INVALTAGS … #define R300_TX_FLUSH … /* The upper enable bits are guessed, based on fglrx reported limits. */ #define R300_TX_ENABLE … #define R300_TX_ENABLE_0 … #define R300_TX_ENABLE_1 … #define R300_TX_ENABLE_2 … #define R300_TX_ENABLE_3 … #define R300_TX_ENABLE_4 … #define R300_TX_ENABLE_5 … #define R300_TX_ENABLE_6 … #define R300_TX_ENABLE_7 … #define R300_TX_ENABLE_8 … #define R300_TX_ENABLE_9 … #define R300_TX_ENABLE_10 … #define R300_TX_ENABLE_11 … #define R300_TX_ENABLE_12 … #define R300_TX_ENABLE_13 … #define R300_TX_ENABLE_14 … #define R300_TX_ENABLE_15 … /* The pointsize is given in multiples of 6. The pointsize can be * enormous: Clear() renders a single point that fills the entire * framebuffer. */ #define R300_RE_POINTSIZE … #define R300_POINTSIZE_Y_SHIFT … #define R300_POINTSIZE_Y_MASK … #define R300_POINTSIZE_X_SHIFT … #define R300_POINTSIZE_X_MASK … #define R300_POINTSIZE_MAX … /* The line width is given in multiples of 6. * In default mode lines are classified as vertical lines. * HO: horizontal * VE: vertical or horizontal * HO & VE: no classification */ #define R300_RE_LINE_CNT … #define R300_LINESIZE_SHIFT … #define R300_LINESIZE_MASK … #define R300_LINESIZE_MAX … #define R300_LINE_CNT_HO … #define R300_LINE_CNT_VE … /* Some sort of scale or clamp value for texcoordless textures. */ #define R300_RE_UNK4238 … /* Something shade related */ #define R300_RE_SHADE … #define R300_RE_SHADE_MODEL … #define R300_RE_SHADE_MODEL_SMOOTH … #define R300_RE_SHADE_MODEL_FLAT … /* Dangerous */ #define R300_RE_POLYGON_MODE … #define R300_PM_ENABLED … #define R300_PM_FRONT_POINT … #define R300_PM_BACK_POINT … #define R300_PM_FRONT_LINE … #define R300_PM_FRONT_FILL … #define R300_PM_BACK_LINE … #define R300_PM_BACK_FILL … /* Fog parameters */ #define R300_RE_FOG_SCALE … #define R300_RE_FOG_START … /* Not sure why there are duplicate of factor and constant values. * My best guess so far is that there are separate zbiases for test and write. * Ordering might be wrong. * Some of the tests indicate that fgl has a fallback implementation of zbias * via pixel shaders. */ #define R300_RE_ZBIAS_CNTL … #define R300_RE_ZBIAS_T_FACTOR … #define R300_RE_ZBIAS_T_CONSTANT … #define R300_RE_ZBIAS_W_FACTOR … #define R300_RE_ZBIAS_W_CONSTANT … /* This register needs to be set to (1<<1) for RV350 to correctly * perform depth test (see --vb-triangles in r300_demo) * Don't know about other chips. - Vladimir * This is set to 3 when GL_POLYGON_OFFSET_FILL is on. * My guess is that there are two bits for each zbias primitive * (FILL, LINE, POINT). * One to enable depth test and one for depth write. * Yet this doesn't explain why depth writes work ... */ #define R300_RE_OCCLUSION_CNTL … #define R300_OCCLUSION_ON … #define R300_RE_CULL_CNTL … #define R300_CULL_FRONT … #define R300_CULL_BACK … #define R300_FRONT_FACE_CCW … #define R300_FRONT_FACE_CW … /* BEGIN: Rasterization / Interpolators - many guesses */ /* 0_UNKNOWN_18 has always been set except for clear operations. * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends * on the vertex program, *not* the fragment program) */ #define R300_RS_CNTL_0 … #define R300_RS_CNTL_TC_CNT_SHIFT … #define R300_RS_CNTL_TC_CNT_MASK … /* number of color interpolators used */ #define R300_RS_CNTL_CI_CNT_SHIFT … #define R300_RS_CNTL_0_UNKNOWN_18 … /* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n register. */ #define R300_RS_CNTL_1 … /* gap */ /* Only used for texture coordinates. * Use the source field to route texture coordinate input from the * vertex program to the desired interpolator. Note that the source * field is relative to the outputs the vertex program *actually* * writes. If a vertex program only writes texcoord[1], this will * be source index 0. * Set INTERP_USED on all interpolators that produce data used by * the fragment program. INTERP_USED looks like a swizzling mask, * but I haven't seen it used that way. * * Note: The _UNKNOWN constants are always set in their respective * register. I don't know if this is necessary. */ #define R300_RS_INTERP_0 … #define R300_RS_INTERP_1 … #define R300_RS_INTERP_1_UNKNOWN … #define R300_RS_INTERP_2 … #define R300_RS_INTERP_2_UNKNOWN … #define R300_RS_INTERP_3 … #define R300_RS_INTERP_3_UNKNOWN … #define R300_RS_INTERP_4 … #define R300_RS_INTERP_5 … #define R300_RS_INTERP_6 … #define R300_RS_INTERP_7 … #define R300_RS_INTERP_SRC_SHIFT … #define R300_RS_INTERP_SRC_MASK … #define R300_RS_INTERP_USED … /* These DWORDs control how vertex data is routed into fragment program * registers, after interpolators. */ #define R300_RS_ROUTE_0 … #define R300_RS_ROUTE_1 … #define R300_RS_ROUTE_2 … #define R300_RS_ROUTE_3 … #define R300_RS_ROUTE_4 … #define R300_RS_ROUTE_5 … #define R300_RS_ROUTE_6 … #define R300_RS_ROUTE_7 … #define R300_RS_ROUTE_SOURCE_INTERP_0 … #define R300_RS_ROUTE_SOURCE_INTERP_1 … #define R300_RS_ROUTE_SOURCE_INTERP_2 … #define R300_RS_ROUTE_SOURCE_INTERP_3 … #define R300_RS_ROUTE_SOURCE_INTERP_4 … #define R300_RS_ROUTE_SOURCE_INTERP_5 … #define R300_RS_ROUTE_SOURCE_INTERP_6 … #define R300_RS_ROUTE_SOURCE_INTERP_7 … #define R300_RS_ROUTE_ENABLE … #define R300_RS_ROUTE_DEST_SHIFT … #define R300_RS_ROUTE_DEST_MASK … /* Special handling for color: When the fragment program uses color, * the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the * color register index. * * Apperently you may set the R300_RS_ROUTE_0_COLOR bit, but not provide any * R300_RS_ROUTE_0_COLOR_DEST value; this setup is used for clearing the state. * See r300_ioctl.c:r300EmitClearState. I'm not sure if this setup is strictly * correct or not. - Oliver. */ #define R300_RS_ROUTE_0_COLOR … #define R300_RS_ROUTE_0_COLOR_DEST_SHIFT … #define R300_RS_ROUTE_0_COLOR_DEST_MASK … /* As above, but for secondary color */ #define R300_RS_ROUTE_1_COLOR1 … #define R300_RS_ROUTE_1_COLOR1_DEST_SHIFT … #define R300_RS_ROUTE_1_COLOR1_DEST_MASK … #define R300_RS_ROUTE_1_UNKNOWN11 … /* END: Rasterization / Interpolators - many guesses */ /* Hierarchical Z Enable */ #define R300_SC_HYPERZ … #define R300_SC_HYPERZ_DISABLE … #define R300_SC_HYPERZ_ENABLE … #define R300_SC_HYPERZ_MIN … #define R300_SC_HYPERZ_MAX … #define R300_SC_HYPERZ_ADJ_256 … #define R300_SC_HYPERZ_ADJ_128 … #define R300_SC_HYPERZ_ADJ_64 … #define R300_SC_HYPERZ_ADJ_32 … #define R300_SC_HYPERZ_ADJ_16 … #define R300_SC_HYPERZ_ADJ_8 … #define R300_SC_HYPERZ_ADJ_4 … #define R300_SC_HYPERZ_ADJ_2 … #define R300_SC_HYPERZ_HZ_Z0MIN_NO … #define R300_SC_HYPERZ_HZ_Z0MIN … #define R300_SC_HYPERZ_HZ_Z0MAX_NO … #define R300_SC_HYPERZ_HZ_Z0MAX … #define R300_SC_EDGERULE … /* BEGIN: Scissors and cliprects */ /* There are four clipping rectangles. Their corner coordinates are inclusive. * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending * on whether the pixel is inside cliprects 0-3, respectively. For example, * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned * the number 3 (binary 0011). * Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set, * the pixel is rasterized. * * In addition to this, there is a scissors rectangle. Only pixels inside the * scissors rectangle are drawn. (coordinates are inclusive) * * For some reason, the top-left corner of the framebuffer is at (1440, 1440) * for the purpose of clipping and scissors. */ #define R300_RE_CLIPRECT_TL_0 … #define R300_RE_CLIPRECT_BR_0 … #define R300_RE_CLIPRECT_TL_1 … #define R300_RE_CLIPRECT_BR_1 … #define R300_RE_CLIPRECT_TL_2 … #define R300_RE_CLIPRECT_BR_2 … #define R300_RE_CLIPRECT_TL_3 … #define R300_RE_CLIPRECT_BR_3 … #define R300_CLIPRECT_OFFSET … #define R300_CLIPRECT_MASK … #define R300_CLIPRECT_X_SHIFT … #define R300_CLIPRECT_X_MASK … #define R300_CLIPRECT_Y_SHIFT … #define R300_CLIPRECT_Y_MASK … #define R300_RE_CLIPRECT_CNTL … #define R300_CLIP_OUT … #define R300_CLIP_0 … #define R300_CLIP_1 … #define R300_CLIP_10 … #define R300_CLIP_2 … #define R300_CLIP_20 … #define R300_CLIP_21 … #define R300_CLIP_210 … #define R300_CLIP_3 … #define R300_CLIP_30 … #define R300_CLIP_31 … #define R300_CLIP_310 … #define R300_CLIP_32 … #define R300_CLIP_320 … #define R300_CLIP_321 … #define R300_CLIP_3210 … /* gap */ #define R300_RE_SCISSORS_TL … #define R300_RE_SCISSORS_BR … #define R300_SCISSORS_OFFSET … #define R300_SCISSORS_X_SHIFT … #define R300_SCISSORS_X_MASK … #define R300_SCISSORS_Y_SHIFT … #define R300_SCISSORS_Y_MASK … /* END: Scissors and cliprects */ /* BEGIN: Texture specification */ /* * The texture specification dwords are grouped by meaning and not by texture * unit. This means that e.g. the offset for texture image unit N is found in * register TX_OFFSET_0 + (4*N) */ #define R300_TX_FILTER_0 … #define R300_TX_REPEAT … #define R300_TX_MIRRORED … #define R300_TX_CLAMP … #define R300_TX_CLAMP_TO_EDGE … #define R300_TX_CLAMP_TO_BORDER … #define R300_TX_WRAP_S_SHIFT … #define R300_TX_WRAP_S_MASK … #define R300_TX_WRAP_T_SHIFT … #define R300_TX_WRAP_T_MASK … #define R300_TX_WRAP_Q_SHIFT … #define R300_TX_WRAP_Q_MASK … #define R300_TX_MAG_FILTER_NEAREST … #define R300_TX_MAG_FILTER_LINEAR … #define R300_TX_MAG_FILTER_MASK … #define R300_TX_MIN_FILTER_NEAREST … #define R300_TX_MIN_FILTER_LINEAR … #define R300_TX_MIN_FILTER_NEAREST_MIP_NEAREST … #define R300_TX_MIN_FILTER_NEAREST_MIP_LINEAR … #define R300_TX_MIN_FILTER_LINEAR_MIP_NEAREST … #define R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR … /* NOTE: NEAREST doesn't seem to exist. * Im not seting MAG_FILTER_MASK and (3 << 11) on for all * anisotropy modes because that would void selected mag filter */ #define R300_TX_MIN_FILTER_ANISO_NEAREST … #define R300_TX_MIN_FILTER_ANISO_LINEAR … #define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST … #define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR … #define R300_TX_MIN_FILTER_MASK … #define R300_TX_MAX_ANISO_1_TO_1 … #define R300_TX_MAX_ANISO_2_TO_1 … #define R300_TX_MAX_ANISO_4_TO_1 … #define R300_TX_MAX_ANISO_8_TO_1 … #define R300_TX_MAX_ANISO_16_TO_1 … #define R300_TX_MAX_ANISO_MASK … #define R300_TX_FILTER1_0 … #define R300_CHROMA_KEY_MODE_DISABLE … #define R300_CHROMA_KEY_FORCE … #define R300_CHROMA_KEY_BLEND … #define R300_MC_ROUND_NORMAL … #define R300_MC_ROUND_MPEG4 … #define R300_LOD_BIAS_MASK … #define R300_EDGE_ANISO_EDGE_DIAG … #define R300_EDGE_ANISO_EDGE_ONLY … #define R300_MC_COORD_TRUNCATE_DISABLE … #define R300_MC_COORD_TRUNCATE_MPEG … #define R300_TX_TRI_PERF_0_8 … #define R300_TX_TRI_PERF_1_8 … #define R300_TX_TRI_PERF_1_4 … #define R300_TX_TRI_PERF_3_8 … #define R300_ANISO_THRESHOLD_MASK … #define R300_TX_SIZE_0 … #define R300_TX_WIDTHMASK_SHIFT … #define R300_TX_WIDTHMASK_MASK … #define R300_TX_HEIGHTMASK_SHIFT … #define R300_TX_HEIGHTMASK_MASK … #define R300_TX_UNK23 … #define R300_TX_MAX_MIP_LEVEL_SHIFT … #define R300_TX_MAX_MIP_LEVEL_MASK … #define R300_TX_SIZE_PROJECTED … #define R300_TX_SIZE_TXPITCH_EN … #define R300_TX_FORMAT_0 … /* The interpretation of the format word by Wladimir van der Laan */ /* The X, Y, Z and W refer to the layout of the components. They are given meanings as R, G, B and Alpha by the swizzle specification */ #define R300_TX_FORMAT_X8 … #define R300_TX_FORMAT_X16 … #define R300_TX_FORMAT_Y4X4 … #define R300_TX_FORMAT_Y8X8 … #define R300_TX_FORMAT_Y16X16 … #define R300_TX_FORMAT_Z3Y3X2 … #define R300_TX_FORMAT_Z5Y6X5 … #define R300_TX_FORMAT_Z6Y5X5 … #define R300_TX_FORMAT_Z11Y11X10 … #define R300_TX_FORMAT_Z10Y11X11 … #define R300_TX_FORMAT_W4Z4Y4X4 … #define R300_TX_FORMAT_W1Z5Y5X5 … #define R300_TX_FORMAT_W8Z8Y8X8 … #define R300_TX_FORMAT_W2Z10Y10X10 … #define R300_TX_FORMAT_W16Z16Y16X16 … #define R300_TX_FORMAT_DXT1 … #define R300_TX_FORMAT_DXT3 … #define R300_TX_FORMAT_DXT5 … #define R300_TX_FORMAT_D3DMFT_CxV8U8 … #define R300_TX_FORMAT_A8R8G8B8 … #define R300_TX_FORMAT_B8G8_B8G8 … #define R300_TX_FORMAT_G8R8_G8B8 … /* 0x16 - some 16 bit green format.. ?? */ #define R300_TX_FORMAT_UNK25 … #define R300_TX_FORMAT_CUBIC_MAP … /* gap */ /* Floating point formats */ /* Note - hardware supports both 16 and 32 bit floating point */ #define R300_TX_FORMAT_FL_I16 … #define R300_TX_FORMAT_FL_I16A16 … #define R300_TX_FORMAT_FL_R16G16B16A16 … #define R300_TX_FORMAT_FL_I32 … #define R300_TX_FORMAT_FL_I32A32 … #define R300_TX_FORMAT_FL_R32G32B32A32 … #define R300_TX_FORMAT_ATI2N … /* alpha modes, convenience mostly */ /* if you have alpha, pick constant appropriate to the number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ #define R300_TX_FORMAT_ALPHA_1CH … #define R300_TX_FORMAT_ALPHA_2CH … #define R300_TX_FORMAT_ALPHA_4CH … #define R300_TX_FORMAT_ALPHA_NONE … /* Swizzling */ /* constants */ #define R300_TX_FORMAT_X … #define R300_TX_FORMAT_Y … #define R300_TX_FORMAT_Z … #define R300_TX_FORMAT_W … #define R300_TX_FORMAT_ZERO … #define R300_TX_FORMAT_ONE … /* 2.0*Z, everything above 1.0 is set to 0.0 */ #define R300_TX_FORMAT_CUT_Z … /* 2.0*W, everything above 1.0 is set to 0.0 */ #define R300_TX_FORMAT_CUT_W … #define R300_TX_FORMAT_B_SHIFT … #define R300_TX_FORMAT_G_SHIFT … #define R300_TX_FORMAT_R_SHIFT … #define R300_TX_FORMAT_A_SHIFT … /* Convenience macro to take care of layout and swizzling */ #define R300_EASY_TX_FORMAT(B, G, R, A, FMT) … /* These can be ORed with result of R300_EASY_TX_FORMAT() We don't really know what they do. Take values from a constant color ? */ #define R300_TX_FORMAT_CONST_X … #define R300_TX_FORMAT_CONST_Y … #define R300_TX_FORMAT_CONST_Z … #define R300_TX_FORMAT_CONST_W … #define R300_TX_FORMAT_YUV_MODE … #define R300_TX_PITCH_0 … #define R300_TX_OFFSET_0 … /* BEGIN: Guess from R200 */ #define R300_TXO_ENDIAN_NO_SWAP … #define R300_TXO_ENDIAN_BYTE_SWAP … #define R300_TXO_ENDIAN_WORD_SWAP … #define R300_TXO_ENDIAN_HALFDW_SWAP … #define R300_TXO_MACRO_TILE … #define R300_TXO_MICRO_TILE … #define R300_TXO_MICRO_TILE_SQUARE … #define R300_TXO_OFFSET_MASK … #define R300_TXO_OFFSET_SHIFT … /* END: Guess from R200 */ /* 32 bit chroma key */ #define R300_TX_CHROMA_KEY_0 … /* ff00ff00 == { 0, 1.0, 0, 1.0 } */ #define R300_TX_BORDER_COLOR_0 … /* END: Texture specification */ /* BEGIN: Fragment program instruction set */ /* Fragment programs are written directly into register space. * There are separate instruction streams for texture instructions and ALU * instructions. * In order to synchronize these streams, the program is divided into up * to 4 nodes. Each node begins with a number of TEX operations, followed * by a number of ALU operations. * The first node can have zero TEX ops, all subsequent nodes must have at * least * one TEX ops. * All nodes must have at least one ALU op. * * The index of the last node is stored in PFS_CNTL_0: A value of 0 means * 1 node, a value of 3 means 4 nodes. * The total amount of instructions is defined in PFS_CNTL_2. The offsets are * offsets into the respective instruction streams, while *_END points to the * last instruction relative to this offset. */ #define R300_PFS_CNTL_0 … #define R300_PFS_CNTL_LAST_NODES_SHIFT … #define R300_PFS_CNTL_LAST_NODES_MASK … #define R300_PFS_CNTL_FIRST_NODE_HAS_TEX … #define R300_PFS_CNTL_1 … /* There is an unshifted value here which has so far always been equal to the * index of the highest used temporary register. */ #define R300_PFS_CNTL_2 … #define R300_PFS_CNTL_ALU_OFFSET_SHIFT … #define R300_PFS_CNTL_ALU_OFFSET_MASK … #define R300_PFS_CNTL_ALU_END_SHIFT … #define R300_PFS_CNTL_ALU_END_MASK … #define R300_PFS_CNTL_TEX_OFFSET_SHIFT … #define R300_PFS_CNTL_TEX_OFFSET_MASK … #define R300_PFS_CNTL_TEX_END_SHIFT … #define R300_PFS_CNTL_TEX_END_MASK … /* gap */ /* Nodes are stored backwards. The last active node is always stored in * PFS_NODE_3. * Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The * first node is stored in NODE_2, the second node is stored in NODE_3. * * Offsets are relative to the master offset from PFS_CNTL_2. */ #define R300_PFS_NODE_0 … #define R300_PFS_NODE_1 … #define R300_PFS_NODE_2 … #define R300_PFS_NODE_3 … #define R300_PFS_NODE_ALU_OFFSET_SHIFT … #define R300_PFS_NODE_ALU_OFFSET_MASK … #define R300_PFS_NODE_ALU_END_SHIFT … #define R300_PFS_NODE_ALU_END_MASK … #define R300_PFS_NODE_TEX_OFFSET_SHIFT … #define R300_PFS_NODE_TEX_OFFSET_MASK … #define R300_PFS_NODE_TEX_END_SHIFT … #define R300_PFS_NODE_TEX_END_MASK … #define R300_PFS_NODE_OUTPUT_COLOR … #define R300_PFS_NODE_OUTPUT_DEPTH … /* TEX * As far as I can tell, texture instructions cannot write into output * registers directly. A subsequent ALU instruction is always necessary, * even if it's just MAD o0, r0, 1, 0 */ #define R300_PFS_TEXI_0 … #define R300_FPITX_SRC_SHIFT … #define R300_FPITX_SRC_MASK … /* GUESS */ #define R300_FPITX_SRC_CONST … #define R300_FPITX_DST_SHIFT … #define R300_FPITX_DST_MASK … #define R300_FPITX_IMAGE_SHIFT … /* GUESS based on layout and native limits */ #define R300_FPITX_IMAGE_MASK … /* Unsure if these are opcodes, or some kind of bitfield, but this is how * they were set when I checked */ #define R300_FPITX_OPCODE_SHIFT … #define R300_FPITX_OP_TEX … #define R300_FPITX_OP_KIL … #define R300_FPITX_OP_TXP … #define R300_FPITX_OP_TXB … #define R300_FPITX_OPCODE_MASK … /* ALU * The ALU instructions register blocks are enumerated according to the order * in which fglrx. I assume there is space for 64 instructions, since * each block has space for a maximum of 64 DWORDs, and this matches reported * native limits. * * The basic functional block seems to be one MAD for each color and alpha, * and an adder that adds all components after the MUL. * - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands * - DP4: Use OUTC_DP4, OUTA_DP4 * - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands * - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands * - CMPH: If ARG2 > 0.5, return ARG0, else return ARG1 * - CMP: If ARG2 < 0, return ARG1, else return ARG0 * - FLR: use FRC+MAD * - XPD: use MAD+MAD * - SGE, SLT: use MAD+CMP * - RSQ: use ABS modifier for argument * - Use OUTC_REPL_ALPHA to write results of an alpha-only operation * (e.g. RCP) into color register * - apparently, there's no quick DST operation * - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2" * - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0" * - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1" * * Operand selection * First stage selects three sources from the available registers and * constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha). * fglrx sorts the three source fields: Registers before constants, * lower indices before higher indices; I do not know whether this is * necessary. * * fglrx fills unused sources with "read constant 0" * According to specs, you cannot select more than two different constants. * * Second stage selects the operands from the sources. This is defined in * INSTR0 (color) and INSTR2 (alpha). You can also select the special constants * zero and one. * Swizzling and negation happens in this stage, as well. * * Important: Color and alpha seem to be mostly separate, i.e. their sources * selection appears to be fully independent (the register storage is probably * physically split into a color and an alpha section). * However (because of the apparent physical split), there is some interaction * WRT swizzling. If, for example, you want to load an R component into an * Alpha operand, this R component is taken from a *color* source, not from * an alpha source. The corresponding register doesn't even have to appear in * the alpha sources list. (I hope this all makes sense to you) * * Destination selection * The destination register index is in FPI1 (color) and FPI3 (alpha) * together with enable bits. * There are separate enable bits for writing into temporary registers * (DSTC_REG_* /DSTA_REG) and program output registers (DSTC_OUTPUT_* * /DSTA_OUTPUT). You can write to both at once, or not write at all (the * same index must be used for both). * * Note: There is a special form for LRP * - Argument order is the same as in ARB_fragment_program. * - Operation is MAD * - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP * - Set FPI0/FPI2_SPECIAL_LRP * Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD */ #define R300_PFS_INSTR1_0 … #define R300_FPI1_SRC0C_SHIFT … #define R300_FPI1_SRC0C_MASK … #define R300_FPI1_SRC0C_CONST … #define R300_FPI1_SRC1C_SHIFT … #define R300_FPI1_SRC1C_MASK … #define R300_FPI1_SRC1C_CONST … #define R300_FPI1_SRC2C_SHIFT … #define R300_FPI1_SRC2C_MASK … #define R300_FPI1_SRC2C_CONST … #define R300_FPI1_SRC_MASK … #define R300_FPI1_DSTC_SHIFT … #define R300_FPI1_DSTC_MASK … #define R300_FPI1_DSTC_REG_MASK_SHIFT … #define R300_FPI1_DSTC_REG_X … #define R300_FPI1_DSTC_REG_Y … #define R300_FPI1_DSTC_REG_Z … #define R300_FPI1_DSTC_OUTPUT_MASK_SHIFT … #define R300_FPI1_DSTC_OUTPUT_X … #define R300_FPI1_DSTC_OUTPUT_Y … #define R300_FPI1_DSTC_OUTPUT_Z … #define R300_PFS_INSTR3_0 … #define R300_FPI3_SRC0A_SHIFT … #define R300_FPI3_SRC0A_MASK … #define R300_FPI3_SRC0A_CONST … #define R300_FPI3_SRC1A_SHIFT … #define R300_FPI3_SRC1A_MASK … #define R300_FPI3_SRC1A_CONST … #define R300_FPI3_SRC2A_SHIFT … #define R300_FPI3_SRC2A_MASK … #define R300_FPI3_SRC2A_CONST … #define R300_FPI3_SRC_MASK … #define R300_FPI3_DSTA_SHIFT … #define R300_FPI3_DSTA_MASK … #define R300_FPI3_DSTA_REG … #define R300_FPI3_DSTA_OUTPUT … #define R300_FPI3_DSTA_DEPTH … #define R300_PFS_INSTR0_0 … #define R300_FPI0_ARGC_SRC0C_XYZ … #define R300_FPI0_ARGC_SRC0C_XXX … #define R300_FPI0_ARGC_SRC0C_YYY … #define R300_FPI0_ARGC_SRC0C_ZZZ … #define R300_FPI0_ARGC_SRC1C_XYZ … #define R300_FPI0_ARGC_SRC1C_XXX … #define R300_FPI0_ARGC_SRC1C_YYY … #define R300_FPI0_ARGC_SRC1C_ZZZ … #define R300_FPI0_ARGC_SRC2C_XYZ … #define R300_FPI0_ARGC_SRC2C_XXX … #define R300_FPI0_ARGC_SRC2C_YYY … #define R300_FPI0_ARGC_SRC2C_ZZZ … #define R300_FPI0_ARGC_SRC0A … #define R300_FPI0_ARGC_SRC1A … #define R300_FPI0_ARGC_SRC2A … #define R300_FPI0_ARGC_SRC1C_LRP … #define R300_FPI0_ARGC_ZERO … #define R300_FPI0_ARGC_ONE … /* GUESS */ #define R300_FPI0_ARGC_HALF … #define R300_FPI0_ARGC_SRC0C_YZX … #define R300_FPI0_ARGC_SRC1C_YZX … #define R300_FPI0_ARGC_SRC2C_YZX … #define R300_FPI0_ARGC_SRC0C_ZXY … #define R300_FPI0_ARGC_SRC1C_ZXY … #define R300_FPI0_ARGC_SRC2C_ZXY … #define R300_FPI0_ARGC_SRC0CA_WZY … #define R300_FPI0_ARGC_SRC1CA_WZY … #define R300_FPI0_ARGC_SRC2CA_WZY … #define R300_FPI0_ARG0C_SHIFT … #define R300_FPI0_ARG0C_MASK … #define R300_FPI0_ARG0C_NEG … #define R300_FPI0_ARG0C_ABS … #define R300_FPI0_ARG1C_SHIFT … #define R300_FPI0_ARG1C_MASK … #define R300_FPI0_ARG1C_NEG … #define R300_FPI0_ARG1C_ABS … #define R300_FPI0_ARG2C_SHIFT … #define R300_FPI0_ARG2C_MASK … #define R300_FPI0_ARG2C_NEG … #define R300_FPI0_ARG2C_ABS … #define R300_FPI0_SPECIAL_LRP … #define R300_FPI0_OUTC_MAD … #define R300_FPI0_OUTC_DP3 … #define R300_FPI0_OUTC_DP4 … #define R300_FPI0_OUTC_MIN … #define R300_FPI0_OUTC_MAX … #define R300_FPI0_OUTC_CMPH … #define R300_FPI0_OUTC_CMP … #define R300_FPI0_OUTC_FRC … #define R300_FPI0_OUTC_REPL_ALPHA … #define R300_FPI0_OUTC_SAT … #define R300_FPI0_INSERT_NOP … #define R300_PFS_INSTR2_0 … #define R300_FPI2_ARGA_SRC0C_X … #define R300_FPI2_ARGA_SRC0C_Y … #define R300_FPI2_ARGA_SRC0C_Z … #define R300_FPI2_ARGA_SRC1C_X … #define R300_FPI2_ARGA_SRC1C_Y … #define R300_FPI2_ARGA_SRC1C_Z … #define R300_FPI2_ARGA_SRC2C_X … #define R300_FPI2_ARGA_SRC2C_Y … #define R300_FPI2_ARGA_SRC2C_Z … #define R300_FPI2_ARGA_SRC0A … #define R300_FPI2_ARGA_SRC1A … #define R300_FPI2_ARGA_SRC2A … #define R300_FPI2_ARGA_SRC1A_LRP … #define R300_FPI2_ARGA_ZERO … #define R300_FPI2_ARGA_ONE … /* GUESS */ #define R300_FPI2_ARGA_HALF … #define R300_FPI2_ARG0A_SHIFT … #define R300_FPI2_ARG0A_MASK … #define R300_FPI2_ARG0A_NEG … /* GUESS */ #define R300_FPI2_ARG0A_ABS … #define R300_FPI2_ARG1A_SHIFT … #define R300_FPI2_ARG1A_MASK … #define R300_FPI2_ARG1A_NEG … /* GUESS */ #define R300_FPI2_ARG1A_ABS … #define R300_FPI2_ARG2A_SHIFT … #define R300_FPI2_ARG2A_MASK … #define R300_FPI2_ARG2A_NEG … /* GUESS */ #define R300_FPI2_ARG2A_ABS … #define R300_FPI2_SPECIAL_LRP … #define R300_FPI2_OUTA_MAD … #define R300_FPI2_OUTA_DP4 … #define R300_FPI2_OUTA_MIN … #define R300_FPI2_OUTA_MAX … #define R300_FPI2_OUTA_CMP … #define R300_FPI2_OUTA_FRC … #define R300_FPI2_OUTA_EX2 … #define R300_FPI2_OUTA_LG2 … #define R300_FPI2_OUTA_RCP … #define R300_FPI2_OUTA_RSQ … #define R300_FPI2_OUTA_SAT … #define R300_FPI2_UNKNOWN_31 … /* END: Fragment program instruction set */ /* Fog state and color */ #define R300_RE_FOG_STATE … #define R300_FOG_ENABLE … #define R300_FOG_MODE_LINEAR … #define R300_FOG_MODE_EXP … #define R300_FOG_MODE_EXP2 … #define R300_FOG_MODE_MASK … #define R300_FOG_COLOR_R … #define R300_FOG_COLOR_G … #define R300_FOG_COLOR_B … #define R300_PP_ALPHA_TEST … #define R300_REF_ALPHA_MASK … #define R300_ALPHA_TEST_FAIL … #define R300_ALPHA_TEST_LESS … #define R300_ALPHA_TEST_LEQUAL … #define R300_ALPHA_TEST_EQUAL … #define R300_ALPHA_TEST_GEQUAL … #define R300_ALPHA_TEST_GREATER … #define R300_ALPHA_TEST_NEQUAL … #define R300_ALPHA_TEST_PASS … #define R300_ALPHA_TEST_OP_MASK … #define R300_ALPHA_TEST_ENABLE … /* gap */ /* Fragment program parameters in 7.16 floating point */ #define R300_PFS_PARAM_0_X … #define R300_PFS_PARAM_0_Y … #define R300_PFS_PARAM_0_Z … #define R300_PFS_PARAM_0_W … /* GUESS: PARAM_31 is last, based on native limits reported by fglrx */ #define R300_PFS_PARAM_31_X … #define R300_PFS_PARAM_31_Y … #define R300_PFS_PARAM_31_Z … #define R300_PFS_PARAM_31_W … /* Notes: * - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in * the application * - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND * are set to the same * function (both registers are always set up completely in any case) * - Most blend flags are simply copied from R200 and not tested yet */ #define R300_RB3D_CBLEND … #define R300_RB3D_ABLEND … /* the following only appear in CBLEND */ #define R300_BLEND_ENABLE … #define R300_BLEND_UNKNOWN … #define R300_BLEND_NO_SEPARATE … /* the following are shared between CBLEND and ABLEND */ #define R300_FCN_MASK … #define R300_COMB_FCN_ADD_CLAMP … #define R300_COMB_FCN_ADD_NOCLAMP … #define R300_COMB_FCN_SUB_CLAMP … #define R300_COMB_FCN_SUB_NOCLAMP … #define R300_COMB_FCN_MIN … #define R300_COMB_FCN_MAX … #define R300_COMB_FCN_RSUB_CLAMP … #define R300_COMB_FCN_RSUB_NOCLAMP … #define R300_BLEND_GL_ZERO … #define R300_BLEND_GL_ONE … #define R300_BLEND_GL_SRC_COLOR … #define R300_BLEND_GL_ONE_MINUS_SRC_COLOR … #define R300_BLEND_GL_DST_COLOR … #define R300_BLEND_GL_ONE_MINUS_DST_COLOR … #define R300_BLEND_GL_SRC_ALPHA … #define R300_BLEND_GL_ONE_MINUS_SRC_ALPHA … #define R300_BLEND_GL_DST_ALPHA … #define R300_BLEND_GL_ONE_MINUS_DST_ALPHA … #define R300_BLEND_GL_SRC_ALPHA_SATURATE … #define R300_BLEND_GL_CONST_COLOR … #define R300_BLEND_GL_ONE_MINUS_CONST_COLOR … #define R300_BLEND_GL_CONST_ALPHA … #define R300_BLEND_GL_ONE_MINUS_CONST_ALPHA … #define R300_BLEND_MASK … #define R300_SRC_BLEND_SHIFT … #define R300_DST_BLEND_SHIFT … #define R300_RB3D_BLEND_COLOR … #define R300_RB3D_COLORMASK … #define R300_COLORMASK0_B … #define R300_COLORMASK0_G … #define R300_COLORMASK0_R … #define R300_COLORMASK0_A … /* gap */ #define R300_RB3D_COLOROFFSET0 … #define R300_COLOROFFSET_MASK … #define R300_RB3D_COLOROFFSET1 … #define R300_RB3D_COLOROFFSET2 … #define R300_RB3D_COLOROFFSET3 … /* gap */ /* Bit 16: Larger tiles * Bit 17: 4x2 tiles * Bit 18: Extremely weird tile like, but some pixels duplicated? */ #define R300_RB3D_COLORPITCH0 … #define R300_COLORPITCH_MASK … #define R300_COLOR_TILE_ENABLE … #define R300_COLOR_MICROTILE_ENABLE … #define R300_COLOR_MICROTILE_SQUARE_ENABLE … #define R300_COLOR_ENDIAN_NO_SWAP … #define R300_COLOR_ENDIAN_WORD_SWAP … #define R300_COLOR_ENDIAN_DWORD_SWAP … #define R300_COLOR_FORMAT_RGB565 … #define R300_COLOR_FORMAT_ARGB8888 … #define R300_RB3D_COLORPITCH1 … #define R300_RB3D_COLORPITCH2 … #define R300_RB3D_COLORPITCH3 … #define R300_RB3D_AARESOLVE_OFFSET … #define R300_RB3D_AARESOLVE_PITCH … #define R300_RB3D_AARESOLVE_CTL … /* gap */ /* Guess by Vladimir. * Set to 0A before 3D operations, set to 02 afterwards. */ /*#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C*/ #define R300_RB3D_DSTCACHE_UNKNOWN_02 … #define R300_RB3D_DSTCACHE_UNKNOWN_0A … /* gap */ /* There seems to be no "write only" setting, so use Z-test = ALWAYS * for this. * Bit (1<<8) is the "test" bit. so plain write is 6 - vd */ #define R300_ZB_CNTL … #define R300_STENCIL_ENABLE … #define R300_Z_ENABLE … #define R300_Z_WRITE_ENABLE … #define R300_Z_SIGNED_COMPARE … #define R300_STENCIL_FRONT_BACK … #define R300_ZB_ZSTENCILCNTL … /* functions */ #define R300_ZS_NEVER … #define R300_ZS_LESS … #define R300_ZS_LEQUAL … #define R300_ZS_EQUAL … #define R300_ZS_GEQUAL … #define R300_ZS_GREATER … #define R300_ZS_NOTEQUAL … #define R300_ZS_ALWAYS … #define R300_ZS_MASK … /* operations */ #define R300_ZS_KEEP … #define R300_ZS_ZERO … #define R300_ZS_REPLACE … #define R300_ZS_INCR … #define R300_ZS_DECR … #define R300_ZS_INVERT … #define R300_ZS_INCR_WRAP … #define R300_ZS_DECR_WRAP … #define R300_Z_FUNC_SHIFT … /* front and back refer to operations done for front and back faces, i.e. separate stencil function support */ #define R300_S_FRONT_FUNC_SHIFT … #define R300_S_FRONT_SFAIL_OP_SHIFT … #define R300_S_FRONT_ZPASS_OP_SHIFT … #define R300_S_FRONT_ZFAIL_OP_SHIFT … #define R300_S_BACK_FUNC_SHIFT … #define R300_S_BACK_SFAIL_OP_SHIFT … #define R300_S_BACK_ZPASS_OP_SHIFT … #define R300_S_BACK_ZFAIL_OP_SHIFT … #define R300_ZB_STENCILREFMASK … #define R300_STENCILREF_SHIFT … #define R300_STENCILREF_MASK … #define R300_STENCILMASK_SHIFT … #define R300_STENCILMASK_MASK … #define R300_STENCILWRITEMASK_SHIFT … #define R300_STENCILWRITEMASK_MASK … /* gap */ #define R300_ZB_FORMAT … #define R300_DEPTHFORMAT_16BIT_INT_Z … #define R300_DEPTHFORMAT_16BIT_13E3 … #define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL … /* reserved up to (15 << 0) */ #define R300_INVERT_13E3_LEADING_ONES … #define R300_INVERT_13E3_LEADING_ZEROS … #define R300_ZB_ZTOP … #define R300_ZTOP_DISABLE … #define R300_ZTOP_ENABLE … /* gap */ #define R300_ZB_ZCACHE_CTLSTAT … #define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT … #define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE … #define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT … #define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE … #define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE … #define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY … #define R300_ZB_BW_CNTL … #define R300_HIZ_DISABLE … #define R300_HIZ_ENABLE … #define R300_HIZ_MIN … #define R300_HIZ_MAX … #define R300_FAST_FILL_DISABLE … #define R300_FAST_FILL_ENABLE … #define R300_RD_COMP_DISABLE … #define R300_RD_COMP_ENABLE … #define R300_WR_COMP_DISABLE … #define R300_WR_COMP_ENABLE … #define R300_ZB_CB_CLEAR_RMW … #define R300_ZB_CB_CLEAR_CACHE_LINEAR … #define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE … #define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE … #define R500_ZEQUAL_OPTIMIZE_ENABLE … #define R500_ZEQUAL_OPTIMIZE_DISABLE … #define R500_SEQUAL_OPTIMIZE_ENABLE … #define R500_SEQUAL_OPTIMIZE_DISABLE … #define R500_BMASK_ENABLE … #define R500_BMASK_DISABLE … #define R500_HIZ_EQUAL_REJECT_DISABLE … #define R500_HIZ_EQUAL_REJECT_ENABLE … #define R500_HIZ_FP_EXP_BITS_DISABLE … #define R500_HIZ_FP_EXP_BITS_1 … #define R500_HIZ_FP_EXP_BITS_2 … #define R500_HIZ_FP_EXP_BITS_3 … #define R500_HIZ_FP_EXP_BITS_4 … #define R500_HIZ_FP_EXP_BITS_5 … #define R500_HIZ_FP_INVERT_LEADING_ONES … #define R500_HIZ_FP_INVERT_LEADING_ZEROS … #define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE … #define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE … #define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE … #define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE … #define R500_PEQ_PACKING_DISABLE … #define R500_PEQ_PACKING_ENABLE … #define R500_COVERED_PTR_MASKING_DISABLE … #define R500_COVERED_PTR_MASKING_ENABLE … /* gap */ /* Z Buffer Address Offset. * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles. */ #define R300_ZB_DEPTHOFFSET … /* Z Buffer Pitch and Endian Control */ #define R300_ZB_DEPTHPITCH … #define R300_DEPTHPITCH_MASK … #define R300_DEPTHMACROTILE_DISABLE … #define R300_DEPTHMACROTILE_ENABLE … #define R300_DEPTHMICROTILE_LINEAR … #define R300_DEPTHMICROTILE_TILED … #define R300_DEPTHMICROTILE_TILED_SQUARE … #define R300_DEPTHENDIAN_NO_SWAP … #define R300_DEPTHENDIAN_WORD_SWAP … #define R300_DEPTHENDIAN_DWORD_SWAP … #define R300_DEPTHENDIAN_HALF_DWORD_SWAP … /* Z Buffer Clear Value */ #define R300_ZB_DEPTHCLEARVALUE … #define R300_ZB_ZMASK_OFFSET … #define R300_ZB_ZMASK_PITCH … #define R300_ZB_ZMASK_WRINDEX … #define R300_ZB_ZMASK_DWORD … #define R300_ZB_ZMASK_RDINDEX … /* Hierarchical Z Memory Offset */ #define R300_ZB_HIZ_OFFSET … /* Hierarchical Z Write Index */ #define R300_ZB_HIZ_WRINDEX … /* Hierarchical Z Data */ #define R300_ZB_HIZ_DWORD … /* Hierarchical Z Read Index */ #define R300_ZB_HIZ_RDINDEX … /* Hierarchical Z Pitch */ #define R300_ZB_HIZ_PITCH … /* Z Buffer Z Pass Counter Data */ #define R300_ZB_ZPASS_DATA … /* Z Buffer Z Pass Counter Address */ #define R300_ZB_ZPASS_ADDR … /* Depth buffer X and Y coordinate offset */ #define R300_ZB_DEPTHXY_OFFSET … #define R300_DEPTHX_OFFSET_SHIFT … #define R300_DEPTHX_OFFSET_MASK … #define R300_DEPTHY_OFFSET_SHIFT … #define R300_DEPTHY_OFFSET_MASK … /* Sets the fifo sizes */ #define R500_ZB_FIFO_SIZE … #define R500_OP_FIFO_SIZE_FULL … #define R500_OP_FIFO_SIZE_HALF … #define R500_OP_FIFO_SIZE_QUATER … #define R500_OP_FIFO_SIZE_EIGTHS … /* Stencil Reference Value and Mask for backfacing quads */ /* R300_ZB_STENCILREFMASK handles front face */ #define R500_ZB_STENCILREFMASK_BF … #define R500_STENCILREF_SHIFT … #define R500_STENCILREF_MASK … #define R500_STENCILMASK_SHIFT … #define R500_STENCILMASK_MASK … #define R500_STENCILWRITEMASK_SHIFT … #define R500_STENCILWRITEMASK_MASK … /* BEGIN: Vertex program instruction set */ /* Every instruction is four dwords long: * DWORD 0: output and opcode * DWORD 1: first argument * DWORD 2: second argument * DWORD 3: third argument * * Notes: * - ABS r, a is implemented as MAX r, a, -a * - MOV is implemented as ADD to zero * - XPD is implemented as MUL + MAD * - FLR is implemented as FRC + ADD * - apparently, fglrx tries to schedule instructions so that there is at * least one instruction between the write to a temporary and the first * read from said temporary; however, violations of this scheduling are * allowed * - register indices seem to be unrelated with OpenGL aliasing to * conventional state * - only one attribute and one parameter can be loaded at a time; however, * the same attribute/parameter can be used for more than one argument * - the second software argument for POW is the third hardware argument * (no idea why) * - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_2 * * There is some magic surrounding LIT: * The single argument is replicated across all three inputs, but swizzled: * First argument: xyzy * Second argument: xyzx * Third argument: xyzw * Whenever the result is used later in the fragment program, fglrx forces * x and w to be 1.0 in the input selection; I don't know whether this is * strictly necessary */ #define R300_VPI_OUT_OP_DOT … #define R300_VPI_OUT_OP_MUL … #define R300_VPI_OUT_OP_ADD … #define R300_VPI_OUT_OP_MAD … #define R300_VPI_OUT_OP_DST … #define R300_VPI_OUT_OP_FRC … #define R300_VPI_OUT_OP_MAX … #define R300_VPI_OUT_OP_MIN … #define R300_VPI_OUT_OP_SGE … #define R300_VPI_OUT_OP_SLT … /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */ #define R300_VPI_OUT_OP_UNK12 … #define R300_VPI_OUT_OP_ARL … #define R300_VPI_OUT_OP_EXP … #define R300_VPI_OUT_OP_LOG … /* Used in fog computations, scalar(scalar) */ #define R300_VPI_OUT_OP_UNK67 … #define R300_VPI_OUT_OP_LIT … #define R300_VPI_OUT_OP_POW … #define R300_VPI_OUT_OP_RCP … #define R300_VPI_OUT_OP_RSQ … /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */ #define R300_VPI_OUT_OP_UNK73 … #define R300_VPI_OUT_OP_EX2 … #define R300_VPI_OUT_OP_LG2 … #define R300_VPI_OUT_OP_MAD_2 … /* all temps, vector(scalar, vector, vector) */ #define R300_VPI_OUT_OP_UNK129 … #define R300_VPI_OUT_REG_CLASS_TEMPORARY … #define R300_VPI_OUT_REG_CLASS_ADDR … #define R300_VPI_OUT_REG_CLASS_RESULT … #define R300_VPI_OUT_REG_CLASS_MASK … #define R300_VPI_OUT_REG_INDEX_SHIFT … /* GUESS based on fglrx native limits */ #define R300_VPI_OUT_REG_INDEX_MASK … #define R300_VPI_OUT_WRITE_X … #define R300_VPI_OUT_WRITE_Y … #define R300_VPI_OUT_WRITE_Z … #define R300_VPI_OUT_WRITE_W … #define R300_VPI_IN_REG_CLASS_TEMPORARY … #define R300_VPI_IN_REG_CLASS_ATTRIBUTE … #define R300_VPI_IN_REG_CLASS_PARAMETER … #define R300_VPI_IN_REG_CLASS_NONE … #define R300_VPI_IN_REG_CLASS_MASK … #define R300_VPI_IN_REG_INDEX_SHIFT … /* GUESS based on fglrx native limits */ #define R300_VPI_IN_REG_INDEX_MASK … /* The R300 can select components from the input register arbitrarily. * Use the following constants, shifted by the component shift you * want to select */ #define R300_VPI_IN_SELECT_X … #define R300_VPI_IN_SELECT_Y … #define R300_VPI_IN_SELECT_Z … #define R300_VPI_IN_SELECT_W … #define R300_VPI_IN_SELECT_ZERO … #define R300_VPI_IN_SELECT_ONE … #define R300_VPI_IN_SELECT_MASK … #define R300_VPI_IN_X_SHIFT … #define R300_VPI_IN_Y_SHIFT … #define R300_VPI_IN_Z_SHIFT … #define R300_VPI_IN_W_SHIFT … #define R300_VPI_IN_NEG_X … #define R300_VPI_IN_NEG_Y … #define R300_VPI_IN_NEG_Z … #define R300_VPI_IN_NEG_W … /* END: Vertex program instruction set */ /* BEGIN: Packet 3 commands */ /* A primitive emission dword. */ #define R300_PRIM_TYPE_NONE … #define R300_PRIM_TYPE_POINT … #define R300_PRIM_TYPE_LINE … #define R300_PRIM_TYPE_LINE_STRIP … #define R300_PRIM_TYPE_TRI_LIST … #define R300_PRIM_TYPE_TRI_FAN … #define R300_PRIM_TYPE_TRI_STRIP … #define R300_PRIM_TYPE_TRI_TYPE2 … #define R300_PRIM_TYPE_RECT_LIST … #define R300_PRIM_TYPE_3VRT_POINT_LIST … #define R300_PRIM_TYPE_3VRT_LINE_LIST … /* GUESS (based on r200) */ #define R300_PRIM_TYPE_POINT_SPRITES … #define R300_PRIM_TYPE_LINE_LOOP … #define R300_PRIM_TYPE_QUADS … #define R300_PRIM_TYPE_QUAD_STRIP … #define R300_PRIM_TYPE_POLYGON … #define R300_PRIM_TYPE_MASK … #define R300_PRIM_WALK_IND … #define R300_PRIM_WALK_LIST … #define R300_PRIM_WALK_RING … #define R300_PRIM_WALK_MASK … /* GUESS (based on r200) */ #define R300_PRIM_COLOR_ORDER_BGRA … #define R300_PRIM_COLOR_ORDER_RGBA … #define R300_PRIM_NUM_VERTICES_SHIFT … #define R300_PRIM_NUM_VERTICES_MASK … /* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR. * Two parameter dwords: * 0. The first parameter appears to be always 0 * 1. The second parameter is a standard primitive emission dword. */ #define R300_PACKET3_3D_DRAW_VBUF … /* Specify the full set of vertex arrays as (address, stride). * The first parameter is the number of vertex arrays specified. * The rest of the command is a variable length list of blocks, where * each block is three dwords long and specifies two arrays. * The first dword of a block is split into two words, the lower significant * word refers to the first array, the more significant word to the second * array in the block. * The low byte of each word contains the size of an array entry in dwords, * the high byte contains the stride of the array. * The second dword of a block contains the pointer to the first array, * the third dword of a block contains the pointer to the second array. * Note that if the total number of arrays is odd, the third dword of * the last block is omitted. */ #define R300_PACKET3_3D_LOAD_VBPNTR … #define R300_PACKET3_INDX_BUFFER … #define R300_EB_UNK1_SHIFT … #define R300_EB_UNK1 … #define R300_EB_UNK2 … #define R300_PACKET3_3D_DRAW_VBUF_2 … #define R300_PACKET3_3D_DRAW_INDX_2 … /* END: Packet 3 commands */ /* Color formats for 2d packets */ #define R300_CP_COLOR_FORMAT_CI8 … #define R300_CP_COLOR_FORMAT_ARGB1555 … #define R300_CP_COLOR_FORMAT_RGB565 … #define R300_CP_COLOR_FORMAT_ARGB8888 … #define R300_CP_COLOR_FORMAT_RGB332 … #define R300_CP_COLOR_FORMAT_RGB8 … #define R300_CP_COLOR_FORMAT_ARGB4444 … /* * CP type-3 packets */ #define R300_CP_CMD_BITBLT_MULTI … #define R500_VAP_INDEX_OFFSET … #define R500_GA_US_VECTOR_INDEX … #define R500_GA_US_VECTOR_DATA … #define R500_RS_IP_0 … #define R500_RS_INST_0 … #define R500_US_CONFIG … #define R500_US_FC_CTRL … #define R500_US_CODE_ADDR … #define R500_RB3D_COLOR_CLEAR_VALUE_AR … #define R500_RB3D_CONSTANT_COLOR_AR … #define R300_SU_REG_DEST … #define RV530_FG_ZBREG_DEST … #define R300_ZB_ZPASS_DATA … #define R300_ZB_ZPASS_ADDR … #endif /* _R300_REG_H */
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