/* * Copyright 2012 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Alex Deucher */ #ifndef __CIK_REG_H__ #define __CIK_REG_H__ #define CIK_DIDT_IND_INDEX … #define CIK_DIDT_IND_DATA … #define CIK_DC_GPIO_HPD_MASK … #define CIK_DC_GPIO_HPD_A … #define CIK_DC_GPIO_HPD_EN … #define CIK_DC_GPIO_HPD_Y … #define CIK_GRPH_CONTROL … #define CIK_GRPH_DEPTH(x) … #define CIK_GRPH_DEPTH_8BPP … #define CIK_GRPH_DEPTH_16BPP … #define CIK_GRPH_DEPTH_32BPP … #define CIK_GRPH_NUM_BANKS(x) … #define CIK_ADDR_SURF_2_BANK … #define CIK_ADDR_SURF_4_BANK … #define CIK_ADDR_SURF_8_BANK … #define CIK_ADDR_SURF_16_BANK … #define CIK_GRPH_Z(x) … #define CIK_GRPH_BANK_WIDTH(x) … #define CIK_ADDR_SURF_BANK_WIDTH_1 … #define CIK_ADDR_SURF_BANK_WIDTH_2 … #define CIK_ADDR_SURF_BANK_WIDTH_4 … #define CIK_ADDR_SURF_BANK_WIDTH_8 … #define CIK_GRPH_FORMAT(x) … /* 8 BPP */ #define CIK_GRPH_FORMAT_INDEXED … /* 16 BPP */ #define CIK_GRPH_FORMAT_ARGB1555 … #define CIK_GRPH_FORMAT_ARGB565 … #define CIK_GRPH_FORMAT_ARGB4444 … #define CIK_GRPH_FORMAT_AI88 … #define CIK_GRPH_FORMAT_MONO16 … #define CIK_GRPH_FORMAT_BGRA5551 … /* 32 BPP */ #define CIK_GRPH_FORMAT_ARGB8888 … #define CIK_GRPH_FORMAT_ARGB2101010 … #define CIK_GRPH_FORMAT_32BPP_DIG … #define CIK_GRPH_FORMAT_8B_ARGB2101010 … #define CIK_GRPH_FORMAT_BGRA1010102 … #define CIK_GRPH_FORMAT_8B_BGRA1010102 … #define CIK_GRPH_FORMAT_RGB111110 … #define CIK_GRPH_FORMAT_BGR101111 … #define CIK_GRPH_BANK_HEIGHT(x) … #define CIK_ADDR_SURF_BANK_HEIGHT_1 … #define CIK_ADDR_SURF_BANK_HEIGHT_2 … #define CIK_ADDR_SURF_BANK_HEIGHT_4 … #define CIK_ADDR_SURF_BANK_HEIGHT_8 … #define CIK_GRPH_TILE_SPLIT(x) … #define CIK_ADDR_SURF_TILE_SPLIT_64B … #define CIK_ADDR_SURF_TILE_SPLIT_128B … #define CIK_ADDR_SURF_TILE_SPLIT_256B … #define CIK_ADDR_SURF_TILE_SPLIT_512B … #define CIK_ADDR_SURF_TILE_SPLIT_1KB … #define CIK_ADDR_SURF_TILE_SPLIT_2KB … #define CIK_ADDR_SURF_TILE_SPLIT_4KB … #define CIK_GRPH_MACRO_TILE_ASPECT(x) … #define CIK_ADDR_SURF_MACRO_TILE_ASPECT_1 … #define CIK_ADDR_SURF_MACRO_TILE_ASPECT_2 … #define CIK_ADDR_SURF_MACRO_TILE_ASPECT_4 … #define CIK_ADDR_SURF_MACRO_TILE_ASPECT_8 … #define CIK_GRPH_ARRAY_MODE(x) … #define CIK_GRPH_ARRAY_LINEAR_GENERAL … #define CIK_GRPH_ARRAY_LINEAR_ALIGNED … #define CIK_GRPH_ARRAY_1D_TILED_THIN1 … #define CIK_GRPH_ARRAY_2D_TILED_THIN1 … #define CIK_GRPH_PIPE_CONFIG(x) … #define CIK_ADDR_SURF_P2 … #define CIK_ADDR_SURF_P4_8x16 … #define CIK_ADDR_SURF_P4_16x16 … #define CIK_ADDR_SURF_P4_16x32 … #define CIK_ADDR_SURF_P4_32x32 … #define CIK_ADDR_SURF_P8_16x16_8x16 … #define CIK_ADDR_SURF_P8_16x32_8x16 … #define CIK_ADDR_SURF_P8_32x32_8x16 … #define CIK_ADDR_SURF_P8_16x32_16x16 … #define CIK_ADDR_SURF_P8_32x32_16x16 … #define CIK_ADDR_SURF_P8_32x32_16x32 … #define CIK_ADDR_SURF_P8_32x64_32x32 … #define CIK_GRPH_MICRO_TILE_MODE(x) … #define CIK_DISPLAY_MICRO_TILING … #define CIK_THIN_MICRO_TILING … #define CIK_DEPTH_MICRO_TILING … #define CIK_ROTATED_MICRO_TILING … /* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */ #define CIK_CUR_CONTROL … #define CIK_CURSOR_EN … #define CIK_CURSOR_MODE(x) … #define CIK_CURSOR_MONO … #define CIK_CURSOR_24_1 … #define CIK_CURSOR_24_8_PRE_MULT … #define CIK_CURSOR_24_8_UNPRE_MULT … #define CIK_CURSOR_2X_MAGNIFY … #define CIK_CURSOR_FORCE_MC_ON … #define CIK_CURSOR_URGENT_CONTROL(x) … #define CIK_CURSOR_URGENT_ALWAYS … #define CIK_CURSOR_URGENT_1_8 … #define CIK_CURSOR_URGENT_1_4 … #define CIK_CURSOR_URGENT_3_8 … #define CIK_CURSOR_URGENT_1_2 … #define CIK_CUR_SURFACE_ADDRESS … #define CIK_CUR_SURFACE_ADDRESS_MASK … #define CIK_CUR_SIZE … #define CIK_CUR_SURFACE_ADDRESS_HIGH … #define CIK_CUR_POSITION … #define CIK_CUR_HOT_SPOT … #define CIK_CUR_COLOR1 … #define CIK_CUR_COLOR2 … #define CIK_CUR_UPDATE … #define CIK_CURSOR_UPDATE_PENDING … #define CIK_CURSOR_UPDATE_TAKEN … #define CIK_CURSOR_UPDATE_LOCK … #define CIK_CURSOR_DISABLE_MULTIPLE_UPDATE … #define CIK_ALPHA_CONTROL … #define CIK_CURSOR_ALPHA_BLND_ENA … #define CIK_LB_DATA_FORMAT … #define CIK_INTERLEAVE_EN … #define CIK_LB_DESKTOP_HEIGHT … #define SQ_IND_INDEX … #define SQ_CMD … #define SQ_IND_DATA … /* * The TCP_WATCHx_xxxx addresses that are shown here are in dwords, * and that's why they are multiplied by 4 */ #define TCP_WATCH0_ADDR_H … #define TCP_WATCH1_ADDR_H … #define TCP_WATCH2_ADDR_H … #define TCP_WATCH3_ADDR_H … #define TCP_WATCH0_ADDR_L … #define TCP_WATCH1_ADDR_L … #define TCP_WATCH2_ADDR_L … #define TCP_WATCH3_ADDR_L … #define TCP_WATCH0_CNTL … #define TCP_WATCH1_CNTL … #define TCP_WATCH2_CNTL … #define TCP_WATCH3_CNTL … #define CPC_INT_CNTL … #define CP_HQD_IQ_RPTR … #define SDMA0_RLC0_RB_CNTL … #define SDMA_RB_VMID(x) … #define SDMA0_RLC0_RB_BASE … #define SDMA0_RLC0_RB_BASE_HI … #define SDMA0_RLC0_RB_RPTR … #define SDMA0_RLC0_RB_WPTR … #define SDMA0_RLC0_RB_WPTR_POLL_CNTL … #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI … #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO … #define SDMA0_RLC0_RB_RPTR_ADDR_HI … #define SDMA0_RLC0_RB_RPTR_ADDR_LO … #define SDMA0_RLC0_IB_CNTL … #define SDMA0_RLC0_IB_RPTR … #define SDMA0_RLC0_IB_OFFSET … #define SDMA0_RLC0_IB_BASE_LO … #define SDMA0_RLC0_IB_BASE_HI … #define SDMA0_RLC0_IB_SIZE … #define SDMA0_RLC0_SKIP_CNTL … #define SDMA0_RLC0_CONTEXT_STATUS … #define SDMA_RLC_IDLE … #define SDMA0_RLC0_DOORBELL … #define SDMA_OFFSET(x) … #define SDMA_DB_ENABLE … #define SDMA0_RLC0_VIRTUAL_ADDR … #define SDMA_ATC … #define SDMA_VA_PTR32 … #define SDMA_VA_SHARED_BASE(x) … #define SDMA0_RLC0_APE1_CNTL … #define SDMA0_RLC0_DOORBELL_LOG … #define SDMA0_RLC0_WATERMARK … #define SDMA0_CNTL … #define SDMA1_CNTL … enum { … }; enum { … }; enum { … }; TCP_WATCH_CNTL_BITS; #endif
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