/* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. * * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation on the rights to use, copy, modify, merge, * publish, distribute, sublicense, and/or sell copies of the Software, * and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ /* * Authors: * Kevin E. Martin <[email protected]> * Rickard E. Faith <[email protected]> * Alan Hourihane <[email protected]> * * References: * * !!!! FIXME !!!! * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April * 1999. * * !!!! FIXME !!!! * RAGE 128 Software Development Manual (Technical Reference Manual P/N * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. * */ /* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */ #ifndef _RADEON_REG_H_ #define _RADEON_REG_H_ #include "r300_reg.h" #include "r500_reg.h" #include "r600_reg.h" #include "evergreen_reg.h" #include "ni_reg.h" #include "si_reg.h" #include "cik_reg.h" #define RADEON_MC_AGP_LOCATION … #define RADEON_MC_AGP_START_MASK … #define RADEON_MC_AGP_START_SHIFT … #define RADEON_MC_AGP_TOP_MASK … #define RADEON_MC_AGP_TOP_SHIFT … #define RADEON_MC_FB_LOCATION … #define RADEON_MC_FB_START_MASK … #define RADEON_MC_FB_START_SHIFT … #define RADEON_MC_FB_TOP_MASK … #define RADEON_MC_FB_TOP_SHIFT … #define RADEON_AGP_BASE_2 … #define RADEON_AGP_BASE … #define ATI_DATATYPE_VQ … #define ATI_DATATYPE_CI4 … #define ATI_DATATYPE_CI8 … #define ATI_DATATYPE_ARGB1555 … #define ATI_DATATYPE_RGB565 … #define ATI_DATATYPE_RGB888 … #define ATI_DATATYPE_ARGB8888 … #define ATI_DATATYPE_RGB332 … #define ATI_DATATYPE_Y8 … #define ATI_DATATYPE_RGB8 … #define ATI_DATATYPE_CI16 … #define ATI_DATATYPE_VYUY_422 … #define ATI_DATATYPE_YVYU_422 … #define ATI_DATATYPE_AYUV_444 … #define ATI_DATATYPE_ARGB4444 … /* Registers for 2D/Video/Overlay */ #define RADEON_ADAPTER_ID … #define RADEON_AGP_BASE … #define RADEON_AGP_CNTL … #define RADEON_AGP_APER_SIZE_256MB … #define RADEON_AGP_APER_SIZE_128MB … #define RADEON_AGP_APER_SIZE_64MB … #define RADEON_AGP_APER_SIZE_32MB … #define RADEON_AGP_APER_SIZE_16MB … #define RADEON_AGP_APER_SIZE_8MB … #define RADEON_AGP_APER_SIZE_4MB … #define RADEON_AGP_APER_SIZE_MASK … #define RADEON_STATUS_PCI_CONFIG … #define RADEON_CAP_LIST … #define RADEON_CAPABILITIES_PTR_PCI_CONFIG … #define RADEON_CAP_PTR_MASK … #define RADEON_CAP_ID_NULL … #define RADEON_CAP_ID_AGP … #define RADEON_CAP_ID_EXP … #define RADEON_AGP_COMMAND … #define RADEON_AGP_COMMAND_PCI_CONFIG … #define RADEON_AGP_ENABLE … #define RADEON_AGP_PLL_CNTL … #define RADEON_AGP_STATUS … #define RADEON_AGP_1X_MODE … #define RADEON_AGP_2X_MODE … #define RADEON_AGP_4X_MODE … #define RADEON_AGP_FW_MODE … #define RADEON_AGP_MODE_MASK … #define RADEON_AGPv3_MODE … #define RADEON_AGPv3_4X_MODE … #define RADEON_AGPv3_8X_MODE … #define RADEON_ATTRDR … #define RADEON_ATTRDW … #define RADEON_ATTRX … #define RADEON_AUX_SC_CNTL … #define RADEON_AUX1_SC_EN … #define RADEON_AUX1_SC_MODE_OR … #define RADEON_AUX1_SC_MODE_NAND … #define RADEON_AUX2_SC_EN … #define RADEON_AUX2_SC_MODE_OR … #define RADEON_AUX2_SC_MODE_NAND … #define RADEON_AUX3_SC_EN … #define RADEON_AUX3_SC_MODE_OR … #define RADEON_AUX3_SC_MODE_NAND … #define RADEON_AUX1_SC_BOTTOM … #define RADEON_AUX1_SC_LEFT … #define RADEON_AUX1_SC_RIGHT … #define RADEON_AUX1_SC_TOP … #define RADEON_AUX2_SC_BOTTOM … #define RADEON_AUX2_SC_LEFT … #define RADEON_AUX2_SC_RIGHT … #define RADEON_AUX2_SC_TOP … #define RADEON_AUX3_SC_BOTTOM … #define RADEON_AUX3_SC_LEFT … #define RADEON_AUX3_SC_RIGHT … #define RADEON_AUX3_SC_TOP … #define RADEON_AUX_WINDOW_HORZ_CNTL … #define RADEON_AUX_WINDOW_VERT_CNTL … #define RADEON_BASE_CODE … #define RADEON_BIOS_0_SCRATCH … #define RADEON_FP_PANEL_SCALABLE … #define RADEON_FP_PANEL_SCALE_EN … #define RADEON_FP_CHIP_SCALE_EN … #define RADEON_DRIVER_BRIGHTNESS_EN … #define RADEON_DISPLAY_ROT_MASK … #define RADEON_DISPLAY_ROT_00 … #define RADEON_DISPLAY_ROT_90 … #define RADEON_DISPLAY_ROT_180 … #define RADEON_DISPLAY_ROT_270 … #define RADEON_BIOS_1_SCRATCH … #define RADEON_BIOS_2_SCRATCH … #define RADEON_BIOS_3_SCRATCH … #define RADEON_BIOS_4_SCRATCH … #define RADEON_CRT1_ATTACHED_MASK … #define RADEON_CRT1_ATTACHED_MONO … #define RADEON_CRT1_ATTACHED_COLOR … #define RADEON_LCD1_ATTACHED … #define RADEON_DFP1_ATTACHED … #define RADEON_TV1_ATTACHED_MASK … #define RADEON_TV1_ATTACHED_COMP … #define RADEON_TV1_ATTACHED_SVIDEO … #define RADEON_CRT2_ATTACHED_MASK … #define RADEON_CRT2_ATTACHED_MONO … #define RADEON_CRT2_ATTACHED_COLOR … #define RADEON_DFP2_ATTACHED … #define RADEON_BIOS_5_SCRATCH … #define RADEON_LCD1_ON … #define RADEON_CRT1_ON … #define RADEON_TV1_ON … #define RADEON_DFP1_ON … #define RADEON_CRT2_ON … #define RADEON_CV1_ON … #define RADEON_DFP2_ON … #define RADEON_LCD1_CRTC_MASK … #define RADEON_LCD1_CRTC_SHIFT … #define RADEON_CRT1_CRTC_MASK … #define RADEON_CRT1_CRTC_SHIFT … #define RADEON_TV1_CRTC_MASK … #define RADEON_TV1_CRTC_SHIFT … #define RADEON_DFP1_CRTC_MASK … #define RADEON_DFP1_CRTC_SHIFT … #define RADEON_CRT2_CRTC_MASK … #define RADEON_CRT2_CRTC_SHIFT … #define RADEON_CV1_CRTC_MASK … #define RADEON_CV1_CRTC_SHIFT … #define RADEON_DFP2_CRTC_MASK … #define RADEON_DFP2_CRTC_SHIFT … #define RADEON_ACC_REQ_LCD1 … #define RADEON_ACC_REQ_CRT1 … #define RADEON_ACC_REQ_TV1 … #define RADEON_ACC_REQ_DFP1 … #define RADEON_ACC_REQ_CRT2 … #define RADEON_ACC_REQ_TV2 … #define RADEON_ACC_REQ_DFP2 … #define RADEON_BIOS_6_SCRATCH … #define RADEON_ACC_MODE_CHANGE … #define RADEON_EXT_DESKTOP_MODE … #define RADEON_LCD_DPMS_ON … #define RADEON_CRT_DPMS_ON … #define RADEON_TV_DPMS_ON … #define RADEON_DFP_DPMS_ON … #define RADEON_DPMS_MASK … #define RADEON_DPMS_ON … #define RADEON_DPMS_STANDBY … #define RADEON_DPMS_SUSPEND … #define RADEON_DPMS_OFF … #define RADEON_SCREEN_BLANKING … #define RADEON_DRIVER_CRITICAL … #define RADEON_DISPLAY_SWITCHING_DIS … #define RADEON_BIOS_7_SCRATCH … #define RADEON_SYS_HOTKEY … #define RADEON_DRV_LOADED … #define RADEON_BIOS_ROM … #define RADEON_BIST … #define RADEON_BRUSH_DATA0 … #define RADEON_BRUSH_DATA1 … #define RADEON_BRUSH_DATA10 … #define RADEON_BRUSH_DATA11 … #define RADEON_BRUSH_DATA12 … #define RADEON_BRUSH_DATA13 … #define RADEON_BRUSH_DATA14 … #define RADEON_BRUSH_DATA15 … #define RADEON_BRUSH_DATA16 … #define RADEON_BRUSH_DATA17 … #define RADEON_BRUSH_DATA18 … #define RADEON_BRUSH_DATA19 … #define RADEON_BRUSH_DATA2 … #define RADEON_BRUSH_DATA20 … #define RADEON_BRUSH_DATA21 … #define RADEON_BRUSH_DATA22 … #define RADEON_BRUSH_DATA23 … #define RADEON_BRUSH_DATA24 … #define RADEON_BRUSH_DATA25 … #define RADEON_BRUSH_DATA26 … #define RADEON_BRUSH_DATA27 … #define RADEON_BRUSH_DATA28 … #define RADEON_BRUSH_DATA29 … #define RADEON_BRUSH_DATA3 … #define RADEON_BRUSH_DATA30 … #define RADEON_BRUSH_DATA31 … #define RADEON_BRUSH_DATA32 … #define RADEON_BRUSH_DATA33 … #define RADEON_BRUSH_DATA34 … #define RADEON_BRUSH_DATA35 … #define RADEON_BRUSH_DATA36 … #define RADEON_BRUSH_DATA37 … #define RADEON_BRUSH_DATA38 … #define RADEON_BRUSH_DATA39 … #define RADEON_BRUSH_DATA4 … #define RADEON_BRUSH_DATA40 … #define RADEON_BRUSH_DATA41 … #define RADEON_BRUSH_DATA42 … #define RADEON_BRUSH_DATA43 … #define RADEON_BRUSH_DATA44 … #define RADEON_BRUSH_DATA45 … #define RADEON_BRUSH_DATA46 … #define RADEON_BRUSH_DATA47 … #define RADEON_BRUSH_DATA48 … #define RADEON_BRUSH_DATA49 … #define RADEON_BRUSH_DATA5 … #define RADEON_BRUSH_DATA50 … #define RADEON_BRUSH_DATA51 … #define RADEON_BRUSH_DATA52 … #define RADEON_BRUSH_DATA53 … #define RADEON_BRUSH_DATA54 … #define RADEON_BRUSH_DATA55 … #define RADEON_BRUSH_DATA56 … #define RADEON_BRUSH_DATA57 … #define RADEON_BRUSH_DATA58 … #define RADEON_BRUSH_DATA59 … #define RADEON_BRUSH_DATA6 … #define RADEON_BRUSH_DATA60 … #define RADEON_BRUSH_DATA61 … #define RADEON_BRUSH_DATA62 … #define RADEON_BRUSH_DATA63 … #define RADEON_BRUSH_DATA7 … #define RADEON_BRUSH_DATA8 … #define RADEON_BRUSH_DATA9 … #define RADEON_BRUSH_SCALE … #define RADEON_BRUSH_Y_X … #define RADEON_BUS_CNTL … #define RADEON_BUS_MASTER_DIS … #define RADEON_BUS_BIOS_DIS_ROM … #define RS600_BUS_MASTER_DIS … #define RS600_MSI_REARM … #define RADEON_BUS_RD_DISCARD_EN … #define RADEON_BUS_RD_ABORT_EN … #define RADEON_BUS_MSTR_DISCONNECT_EN … #define RADEON_BUS_WRT_BURST … #define RADEON_BUS_READ_BURST … #define RADEON_BUS_CNTL1 … #define RADEON_BUS_WAIT_ON_LOCK_EN … #define RV370_BUS_CNTL … #define RV370_BUS_BIOS_DIS_ROM … /* rv370/rv380, rv410, r423/r430/r480, r5xx */ #define RADEON_MSI_REARM_EN … #define RV370_MSI_REARM_EN … /* #define RADEON_PCIE_INDEX 0x0030 */ /* #define RADEON_PCIE_DATA 0x0034 */ #define RADEON_PCIE_LC_LINK_WIDTH_CNTL … #define RADEON_PCIE_LC_LINK_WIDTH_SHIFT … #define RADEON_PCIE_LC_LINK_WIDTH_MASK … #define RADEON_PCIE_LC_LINK_WIDTH_X0 … #define RADEON_PCIE_LC_LINK_WIDTH_X1 … #define RADEON_PCIE_LC_LINK_WIDTH_X2 … #define RADEON_PCIE_LC_LINK_WIDTH_X4 … #define RADEON_PCIE_LC_LINK_WIDTH_X8 … #define RADEON_PCIE_LC_LINK_WIDTH_X12 … #define RADEON_PCIE_LC_LINK_WIDTH_X16 … #define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT … #define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK … #define RADEON_PCIE_LC_RECONFIG_NOW … #define RADEON_PCIE_LC_RECONFIG_LATER … #define RADEON_PCIE_LC_SHORT_RECONFIG_EN … #define R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE … #define R600_PCIE_LC_RENEGOTIATION_SUPPORT … #define R600_PCIE_LC_RENEGOTIATE_EN … #define R600_PCIE_LC_SHORT_RECONFIG_EN … #define R600_PCIE_LC_UPCONFIGURE_SUPPORT … #define R600_PCIE_LC_UPCONFIGURE_DIS … #define R600_TARGET_AND_CURRENT_PROFILE_INDEX … #define R700_TARGET_AND_CURRENT_PROFILE_INDEX … #define RADEON_CACHE_CNTL … #define RADEON_CACHE_LINE … #define RADEON_CAPABILITIES_ID … #define RADEON_CAPABILITIES_PTR … #define RADEON_CLK_PIN_CNTL … #define RADEON_DONT_USE_XTALIN … #define RADEON_SCLK_DYN_START_CNTL … #define RADEON_CLOCK_CNTL_DATA … #define RADEON_CLOCK_CNTL_INDEX … #define RADEON_PLL_WR_EN … #define RADEON_PLL_DIV_SEL … #define RADEON_PLL2_DIV_SEL_MASK … #define RADEON_CLK_PWRMGT_CNTL … #define RADEON_ENGIN_DYNCLK_MODE … #define RADEON_ACTIVE_HILO_LAT_MASK … #define RADEON_ACTIVE_HILO_LAT_SHIFT … #define RADEON_DISP_DYN_STOP_LAT_MASK … #define RADEON_MC_BUSY … #define RADEON_DLL_READY … #define RADEON_CG_NO1_DEBUG_0 … #define RADEON_CG_NO1_DEBUG_MASK … #define RADEON_DYN_STOP_MODE_MASK … #define RADEON_TVPLL_PWRMGT_OFF … #define RADEON_TVCLK_TURNOFF … #define RADEON_PLL_PWRMGT_CNTL … #define RADEON_PM_MODE_SEL … #define RADEON_TCL_BYPASS_DISABLE … #define RADEON_CLR_CMP_CLR_3D … #define RADEON_CLR_CMP_CLR_DST … #define RADEON_CLR_CMP_CLR_SRC … #define RADEON_CLR_CMP_CNTL … #define RADEON_SRC_CMP_EQ_COLOR … #define RADEON_SRC_CMP_NEQ_COLOR … #define RADEON_CLR_CMP_SRC_SOURCE … #define RADEON_CLR_CMP_MASK … #define RADEON_CLR_CMP_MSK … #define RADEON_CLR_CMP_MASK_3D … #define RADEON_COMMAND … #define RADEON_COMPOSITE_SHADOW_ID … #define RADEON_CONFIG_APER_0_BASE … #define RADEON_CONFIG_APER_1_BASE … #define RADEON_CONFIG_APER_SIZE … #define RADEON_CONFIG_BONDS … #define RADEON_CONFIG_CNTL … #define RADEON_CFG_VGA_RAM_EN … #define RADEON_CFG_VGA_IO_DIS … #define RADEON_CFG_ATI_REV_A11 … #define RADEON_CFG_ATI_REV_A12 … #define RADEON_CFG_ATI_REV_A13 … #define RADEON_CFG_ATI_REV_ID_MASK … #define RADEON_CONFIG_MEMSIZE … #define RADEON_CONFIG_MEMSIZE_EMBEDDED … #define RADEON_CONFIG_REG_1_BASE … #define RADEON_CONFIG_REG_APER_SIZE … #define RADEON_CONFIG_XSTRAP … #define RADEON_CONSTANT_COLOR_C … #define RADEON_CONSTANT_COLOR_MASK … #define RADEON_CONSTANT_COLOR_ONE … #define RADEON_CONSTANT_COLOR_ZERO … #define RADEON_CRC_CMDFIFO_ADDR … #define RADEON_CRC_CMDFIFO_DOUT … #define RADEON_GRPH_BUFFER_CNTL … #define RADEON_GRPH_START_REQ_MASK … #define RADEON_GRPH_START_REQ_SHIFT … #define RADEON_GRPH_STOP_REQ_MASK … #define RADEON_GRPH_STOP_REQ_SHIFT … #define RADEON_GRPH_CRITICAL_POINT_MASK … #define RADEON_GRPH_CRITICAL_POINT_SHIFT … #define RADEON_GRPH_CRITICAL_CNTL … #define RADEON_GRPH_BUFFER_SIZE … #define RADEON_GRPH_CRITICAL_AT_SOF … #define RADEON_GRPH_STOP_CNTL … #define RADEON_GRPH2_BUFFER_CNTL … #define RADEON_GRPH2_START_REQ_MASK … #define RADEON_GRPH2_START_REQ_SHIFT … #define RADEON_GRPH2_STOP_REQ_MASK … #define RADEON_GRPH2_STOP_REQ_SHIFT … #define RADEON_GRPH2_CRITICAL_POINT_MASK … #define RADEON_GRPH2_CRITICAL_POINT_SHIFT … #define RADEON_GRPH2_CRITICAL_CNTL … #define RADEON_GRPH2_BUFFER_SIZE … #define RADEON_GRPH2_CRITICAL_AT_SOF … #define RADEON_GRPH2_STOP_CNTL … #define RADEON_CRTC_CRNT_FRAME … #define RADEON_CRTC_EXT_CNTL … #define RADEON_CRTC_VGA_XOVERSCAN … #define RADEON_VGA_ATI_LINEAR … #define RADEON_XCRT_CNT_EN … #define RADEON_CRTC_HSYNC_DIS … #define RADEON_CRTC_VSYNC_DIS … #define RADEON_CRTC_DISPLAY_DIS … #define RADEON_CRTC_SYNC_TRISTAT … #define RADEON_CRTC_CRT_ON … #define RADEON_CRTC_EXT_CNTL_DPMS_BYTE … #define RADEON_CRTC_HSYNC_DIS_BYTE … #define RADEON_CRTC_VSYNC_DIS_BYTE … #define RADEON_CRTC_DISPLAY_DIS_BYTE … #define RADEON_CRTC_GEN_CNTL … #define RADEON_CRTC_DBL_SCAN_EN … #define RADEON_CRTC_INTERLACE_EN … #define RADEON_CRTC_CSYNC_EN … #define RADEON_CRTC_ICON_EN … #define RADEON_CRTC_CUR_EN … #define RADEON_CRTC_VSTAT_MODE_MASK … #define RADEON_CRTC_CUR_MODE_MASK … #define RADEON_CRTC_CUR_MODE_SHIFT … #define RADEON_CRTC_CUR_MODE_MONO … #define RADEON_CRTC_CUR_MODE_24BPP … #define RADEON_CRTC_EXT_DISP_EN … #define RADEON_CRTC_EN … #define RADEON_CRTC_DISP_REQ_EN_B … #define RADEON_CRTC2_GEN_CNTL … #define RADEON_CRTC2_DBL_SCAN_EN … #define RADEON_CRTC2_INTERLACE_EN … #define RADEON_CRTC2_SYNC_TRISTAT … #define RADEON_CRTC2_HSYNC_TRISTAT … #define RADEON_CRTC2_VSYNC_TRISTAT … #define RADEON_CRTC2_CRT2_ON … #define RADEON_CRTC2_PIX_WIDTH_SHIFT … #define RADEON_CRTC2_PIX_WIDTH_MASK … #define RADEON_CRTC2_ICON_EN … #define RADEON_CRTC2_CUR_EN … #define RADEON_CRTC2_CUR_MODE_MASK … #define RADEON_CRTC2_DISP_DIS … #define RADEON_CRTC2_EN … #define RADEON_CRTC2_DISP_REQ_EN_B … #define RADEON_CRTC2_CSYNC_EN … #define RADEON_CRTC2_HSYNC_DIS … #define RADEON_CRTC2_VSYNC_DIS … #define RADEON_CRTC_MORE_CNTL … #define RADEON_CRTC_AUTO_HORZ_CENTER_EN … #define RADEON_CRTC_AUTO_VERT_CENTER_EN … #define RADEON_CRTC_H_CUTOFF_ACTIVE_EN … #define RADEON_CRTC_V_CUTOFF_ACTIVE_EN … #define RADEON_CRTC_GUI_TRIG_VLINE … #define RADEON_CRTC_H_SYNC_STRT_WID … #define RADEON_CRTC_H_SYNC_STRT_PIX … #define RADEON_CRTC_H_SYNC_STRT_CHAR … #define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT … #define RADEON_CRTC_H_SYNC_WID … #define RADEON_CRTC_H_SYNC_WID_SHIFT … #define RADEON_CRTC_H_SYNC_POL … #define RADEON_CRTC2_H_SYNC_STRT_WID … #define RADEON_CRTC2_H_SYNC_STRT_PIX … #define RADEON_CRTC2_H_SYNC_STRT_CHAR … #define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT … #define RADEON_CRTC2_H_SYNC_WID … #define RADEON_CRTC2_H_SYNC_WID_SHIFT … #define RADEON_CRTC2_H_SYNC_POL … #define RADEON_CRTC_H_TOTAL_DISP … #define RADEON_CRTC_H_TOTAL … #define RADEON_CRTC_H_TOTAL_SHIFT … #define RADEON_CRTC_H_DISP … #define RADEON_CRTC_H_DISP_SHIFT … #define RADEON_CRTC2_H_TOTAL_DISP … #define RADEON_CRTC2_H_TOTAL … #define RADEON_CRTC2_H_TOTAL_SHIFT … #define RADEON_CRTC2_H_DISP … #define RADEON_CRTC2_H_DISP_SHIFT … #define RADEON_CRTC_OFFSET_RIGHT … #define RADEON_CRTC_OFFSET … #define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET … #define RADEON_CRTC_OFFSET__OFFSET_LOCK … #define RADEON_CRTC2_OFFSET … #define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET … #define RADEON_CRTC2_OFFSET__OFFSET_LOCK … #define RADEON_CRTC_OFFSET_CNTL … #define RADEON_CRTC_TILE_LINE_SHIFT … #define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT … #define R300_CRTC_X_Y_MODE_EN_RIGHT … #define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK … #define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO … #define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE … #define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE … #define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS … #define R300_CRTC_X_Y_MODE_EN … #define R300_CRTC_MICRO_TILE_BUFFER_MASK … #define R300_CRTC_MICRO_TILE_BUFFER_AUTO … #define R300_CRTC_MICRO_TILE_BUFFER_SINGLE … #define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE … #define R300_CRTC_MICRO_TILE_BUFFER_DIS … #define R300_CRTC_MICRO_TILE_EN_RIGHT … #define R300_CRTC_MICRO_TILE_EN … #define R300_CRTC_MACRO_TILE_EN_RIGHT … #define R300_CRTC_MACRO_TILE_EN … #define RADEON_CRTC_TILE_EN_RIGHT … #define RADEON_CRTC_TILE_EN … #define RADEON_CRTC_OFFSET_FLIP_CNTL … #define RADEON_CRTC_STEREO_OFFSET_EN … #define RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN … #define RADEON_CRTC_GUI_TRIG_OFFSET_RIGHT_EN … #define R300_CRTC_TILE_X0_Y0 … #define R300_CRTC2_TILE_X0_Y0 … #define RADEON_CRTC2_OFFSET_CNTL … #define RADEON_CRTC2_OFFSET_FLIP_CNTL … #define RADEON_CRTC2_TILE_EN … #define RADEON_CRTC_PITCH … #define RADEON_CRTC_PITCH__SHIFT … #define RADEON_CRTC_PITCH__RIGHT_SHIFT … #define RADEON_CRTC2_PITCH … #define RADEON_CRTC_STATUS … #define RADEON_CRTC_VBLANK_CUR … #define RADEON_CRTC_VBLANK_SAVE … #define RADEON_CRTC_VBLANK_SAVE_CLEAR … #define RADEON_CRTC2_STATUS … #define RADEON_CRTC2_VBLANK_CUR … #define RADEON_CRTC2_VBLANK_SAVE … #define RADEON_CRTC2_VBLANK_SAVE_CLEAR … #define RADEON_CRTC_V_SYNC_STRT_WID … #define RADEON_CRTC_V_SYNC_STRT … #define RADEON_CRTC_V_SYNC_STRT_SHIFT … #define RADEON_CRTC_V_SYNC_WID … #define RADEON_CRTC_V_SYNC_WID_SHIFT … #define RADEON_CRTC_V_SYNC_POL … #define RADEON_CRTC2_V_SYNC_STRT_WID … #define RADEON_CRTC2_V_SYNC_STRT … #define RADEON_CRTC2_V_SYNC_STRT_SHIFT … #define RADEON_CRTC2_V_SYNC_WID … #define RADEON_CRTC2_V_SYNC_WID_SHIFT … #define RADEON_CRTC2_V_SYNC_POL … #define RADEON_CRTC_V_TOTAL_DISP … #define RADEON_CRTC_V_TOTAL … #define RADEON_CRTC_V_TOTAL_SHIFT … #define RADEON_CRTC_V_DISP … #define RADEON_CRTC_V_DISP_SHIFT … #define RADEON_CRTC2_V_TOTAL_DISP … #define RADEON_CRTC2_V_TOTAL … #define RADEON_CRTC2_V_TOTAL_SHIFT … #define RADEON_CRTC2_V_DISP … #define RADEON_CRTC2_V_DISP_SHIFT … #define RADEON_CRTC_VLINE_CRNT_VLINE … #define RADEON_CRTC_CRNT_VLINE_MASK … #define RADEON_CRTC2_CRNT_FRAME … #define RADEON_CRTC2_GUI_TRIG_VLINE … #define RADEON_CRTC2_VLINE_CRNT_VLINE … #define RADEON_CRTC8_DATA … #define RADEON_CRTC8_IDX … #define RADEON_CUR_CLR0 … #define RADEON_CUR_CLR1 … #define RADEON_CUR_HORZ_VERT_OFF … #define RADEON_CUR_HORZ_VERT_POSN … #define RADEON_CUR_OFFSET … #define RADEON_CUR_LOCK … #define RADEON_CUR2_CLR0 … #define RADEON_CUR2_CLR1 … #define RADEON_CUR2_HORZ_VERT_OFF … #define RADEON_CUR2_HORZ_VERT_POSN … #define RADEON_CUR2_OFFSET … #define RADEON_CUR2_LOCK … #define RADEON_DAC_CNTL … #define RADEON_DAC_RANGE_CNTL … #define RADEON_DAC_RANGE_CNTL_PS2 … #define RADEON_DAC_RANGE_CNTL_MASK … #define RADEON_DAC_BLANKING … #define RADEON_DAC_CMP_EN … #define RADEON_DAC_CMP_OUTPUT … #define RADEON_DAC_8BIT_EN … #define RADEON_DAC_TVO_EN … #define RADEON_DAC_VGA_ADR_EN … #define RADEON_DAC_PDWN … #define RADEON_DAC_MASK_ALL … #define RADEON_DAC_CNTL2 … #define RADEON_DAC2_TV_CLK_SEL … #define RADEON_DAC2_DAC_CLK_SEL … #define RADEON_DAC2_DAC2_CLK_SEL … #define RADEON_DAC2_PALETTE_ACC_CTL … #define RADEON_DAC2_CMP_EN … #define RADEON_DAC2_CMP_OUT_R … #define RADEON_DAC2_CMP_OUT_G … #define RADEON_DAC2_CMP_OUT_B … #define RADEON_DAC2_CMP_OUTPUT … #define RADEON_DAC_EXT_CNTL … #define RADEON_DAC2_FORCE_BLANK_OFF_EN … #define RADEON_DAC2_FORCE_DATA_EN … #define RADEON_DAC_FORCE_BLANK_OFF_EN … #define RADEON_DAC_FORCE_DATA_EN … #define RADEON_DAC_FORCE_DATA_SEL_MASK … #define RADEON_DAC_FORCE_DATA_SEL_R … #define RADEON_DAC_FORCE_DATA_SEL_G … #define RADEON_DAC_FORCE_DATA_SEL_B … #define RADEON_DAC_FORCE_DATA_SEL_RGB … #define RADEON_DAC_FORCE_DATA_MASK … #define RADEON_DAC_FORCE_DATA_SHIFT … #define RADEON_DAC_MACRO_CNTL … #define RADEON_DAC_PDWN_R … #define RADEON_DAC_PDWN_G … #define RADEON_DAC_PDWN_B … #define RADEON_DISP_PWR_MAN … #define RADEON_DISP_PWR_MAN_D3_CRTC_EN … #define RADEON_DISP_PWR_MAN_D3_CRTC2_EN … #define RADEON_DISP_PWR_MAN_DPMS_ON … #define RADEON_DISP_PWR_MAN_DPMS_STANDBY … #define RADEON_DISP_PWR_MAN_DPMS_SUSPEND … #define RADEON_DISP_PWR_MAN_DPMS_OFF … #define RADEON_DISP_D3_RST … #define RADEON_DISP_D3_REG_RST … #define RADEON_DISP_D3_GRPH_RST … #define RADEON_DISP_D3_SUBPIC_RST … #define RADEON_DISP_D3_OV0_RST … #define RADEON_DISP_D1D2_GRPH_RST … #define RADEON_DISP_D1D2_SUBPIC_RST … #define RADEON_DISP_D1D2_OV0_RST … #define RADEON_DIG_TMDS_ENABLE_RST … #define RADEON_TV_ENABLE_RST … #define RADEON_AUTO_PWRUP_EN … #define RADEON_TV_DAC_CNTL … #define RADEON_TV_DAC_NBLANK … #define RADEON_TV_DAC_NHOLD … #define RADEON_TV_DAC_PEDESTAL … #define RADEON_TV_MONITOR_DETECT_EN … #define RADEON_TV_DAC_CMPOUT … #define RADEON_TV_DAC_STD_MASK … #define RADEON_TV_DAC_STD_PAL … #define RADEON_TV_DAC_STD_NTSC … #define RADEON_TV_DAC_STD_PS2 … #define RADEON_TV_DAC_STD_RS343 … #define RADEON_TV_DAC_BGSLEEP … #define RADEON_TV_DAC_BGADJ_MASK … #define RADEON_TV_DAC_BGADJ_SHIFT … #define RADEON_TV_DAC_DACADJ_MASK … #define RADEON_TV_DAC_DACADJ_SHIFT … #define RADEON_TV_DAC_RDACPD … #define RADEON_TV_DAC_GDACPD … #define RADEON_TV_DAC_BDACPD … #define RADEON_TV_DAC_RDACDET … #define RADEON_TV_DAC_GDACDET … #define RADEON_TV_DAC_BDACDET … #define R420_TV_DAC_DACADJ_MASK … #define R420_TV_DAC_RDACPD … #define R420_TV_DAC_GDACPD … #define R420_TV_DAC_BDACPD … #define R420_TV_DAC_TVENABLE … #define RADEON_DISP_HW_DEBUG … #define RADEON_CRT2_DISP1_SEL … #define RADEON_DISP_OUTPUT_CNTL … #define RADEON_DISP_DAC_SOURCE_MASK … #define RADEON_DISP_DAC2_SOURCE_MASK … #define RADEON_DISP_DAC_SOURCE_CRTC2 … #define RADEON_DISP_DAC_SOURCE_RMX … #define RADEON_DISP_DAC_SOURCE_LTU … #define RADEON_DISP_DAC2_SOURCE_CRTC2 … #define RADEON_DISP_TVDAC_SOURCE_MASK … #define RADEON_DISP_TVDAC_SOURCE_CRTC … #define RADEON_DISP_TVDAC_SOURCE_CRTC2 … #define RADEON_DISP_TVDAC_SOURCE_RMX … #define RADEON_DISP_TVDAC_SOURCE_LTU … #define RADEON_DISP_TRANS_MATRIX_MASK … #define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB … #define RADEON_DISP_TRANS_MATRIX_GRAPHICS … #define RADEON_DISP_TRANS_MATRIX_VIDEO … #define RADEON_DISP_TV_SOURCE_CRTC … #define RADEON_DISP_TV_SOURCE_LTU … #define RADEON_DISP_TV_OUT_CNTL … #define RADEON_DISP_TV_PATH_SRC_CRTC2 … #define RADEON_DISP_TV_PATH_SRC_CRTC1 … #define RADEON_DAC_CRC_SIG … #define RADEON_DAC_DATA … #define RADEON_DAC_MASK … #define RADEON_DAC_R_INDEX … #define RADEON_DAC_W_INDEX … #define RADEON_DDA_CONFIG … #define RADEON_DDA_ON_OFF … #define RADEON_DEFAULT_OFFSET … #define RADEON_DEFAULT_PITCH … #define RADEON_DEFAULT_SC_BOTTOM_RIGHT … #define RADEON_DEFAULT_SC_RIGHT_MAX … #define RADEON_DEFAULT_SC_BOTTOM_MAX … #define RADEON_DESTINATION_3D_CLR_CMP_VAL … #define RADEON_DESTINATION_3D_CLR_CMP_MSK … #define RADEON_DEVICE_ID … #define RADEON_DISP_MISC_CNTL … #define RADEON_SOFT_RESET_GRPH_PP … #define RADEON_DISP_MERGE_CNTL … #define RADEON_DISP_ALPHA_MODE_MASK … #define RADEON_DISP_ALPHA_MODE_KEY … #define RADEON_DISP_ALPHA_MODE_PER_PIXEL … #define RADEON_DISP_ALPHA_MODE_GLOBAL … #define RADEON_DISP_RGB_OFFSET_EN … #define RADEON_DISP_GRPH_ALPHA_MASK … #define RADEON_DISP_OV0_ALPHA_MASK … #define RADEON_DISP_LIN_TRANS_BYPASS … #define RADEON_DISP2_MERGE_CNTL … #define RADEON_DISP2_RGB_OFFSET_EN … #define RADEON_DISP_LIN_TRANS_GRPH_A … #define RADEON_DISP_LIN_TRANS_GRPH_B … #define RADEON_DISP_LIN_TRANS_GRPH_C … #define RADEON_DISP_LIN_TRANS_GRPH_D … #define RADEON_DISP_LIN_TRANS_GRPH_E … #define RADEON_DISP_LIN_TRANS_GRPH_F … #define RADEON_DP_BRUSH_BKGD_CLR … #define RADEON_DP_BRUSH_FRGD_CLR … #define RADEON_DP_CNTL … #define RADEON_DST_X_LEFT_TO_RIGHT … #define RADEON_DST_Y_TOP_TO_BOTTOM … #define RADEON_DP_DST_TILE_LINEAR … #define RADEON_DP_DST_TILE_MACRO … #define RADEON_DP_DST_TILE_MICRO … #define RADEON_DP_DST_TILE_BOTH … #define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR … #define RADEON_DST_Y_MAJOR … #define RADEON_DST_Y_DIR_TOP_TO_BOTTOM … #define RADEON_DST_X_DIR_LEFT_TO_RIGHT … #define RADEON_DP_DATATYPE … #define RADEON_HOST_BIG_ENDIAN_EN … #define RADEON_DP_GUI_MASTER_CNTL … #define RADEON_GMC_SRC_PITCH_OFFSET_CNTL … #define RADEON_GMC_DST_PITCH_OFFSET_CNTL … #define RADEON_GMC_SRC_CLIPPING … #define RADEON_GMC_DST_CLIPPING … #define RADEON_GMC_BRUSH_DATATYPE_MASK … #define RADEON_GMC_BRUSH_8X8_MONO_FG_BG … #define RADEON_GMC_BRUSH_8X8_MONO_FG_LA … #define RADEON_GMC_BRUSH_1X8_MONO_FG_BG … #define RADEON_GMC_BRUSH_1X8_MONO_FG_LA … #define RADEON_GMC_BRUSH_32x1_MONO_FG_BG … #define RADEON_GMC_BRUSH_32x1_MONO_FG_LA … #define RADEON_GMC_BRUSH_32x32_MONO_FG_BG … #define RADEON_GMC_BRUSH_32x32_MONO_FG_LA … #define RADEON_GMC_BRUSH_8x8_COLOR … #define RADEON_GMC_BRUSH_1X8_COLOR … #define RADEON_GMC_BRUSH_SOLID_COLOR … #define RADEON_GMC_BRUSH_NONE … #define RADEON_GMC_DST_8BPP_CI … #define RADEON_GMC_DST_15BPP … #define RADEON_GMC_DST_16BPP … #define RADEON_GMC_DST_24BPP … #define RADEON_GMC_DST_32BPP … #define RADEON_GMC_DST_8BPP_RGB … #define RADEON_GMC_DST_Y8 … #define RADEON_GMC_DST_RGB8 … #define RADEON_GMC_DST_VYUY … #define RADEON_GMC_DST_YVYU … #define RADEON_GMC_DST_AYUV444 … #define RADEON_GMC_DST_ARGB4444 … #define RADEON_GMC_DST_DATATYPE_MASK … #define RADEON_GMC_DST_DATATYPE_SHIFT … #define RADEON_GMC_SRC_DATATYPE_MASK … #define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG … #define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA … #define RADEON_GMC_SRC_DATATYPE_COLOR … #define RADEON_GMC_BYTE_PIX_ORDER … #define RADEON_GMC_BYTE_MSB_TO_LSB … #define RADEON_GMC_BYTE_LSB_TO_MSB … #define RADEON_GMC_CONVERSION_TEMP … #define RADEON_GMC_CONVERSION_TEMP_6500 … #define RADEON_GMC_CONVERSION_TEMP_9300 … #define RADEON_GMC_ROP3_MASK … #define RADEON_DP_SRC_SOURCE_MASK … #define RADEON_DP_SRC_SOURCE_MEMORY … #define RADEON_DP_SRC_SOURCE_HOST_DATA … #define RADEON_GMC_3D_FCN_EN … #define RADEON_GMC_CLR_CMP_CNTL_DIS … #define RADEON_GMC_AUX_CLIP_DIS … #define RADEON_GMC_WR_MSK_DIS … #define RADEON_GMC_LD_BRUSH_Y_X … #define RADEON_ROP3_ZERO … #define RADEON_ROP3_DSa … #define RADEON_ROP3_SDna … #define RADEON_ROP3_S … #define RADEON_ROP3_DSna … #define RADEON_ROP3_D … #define RADEON_ROP3_DSx … #define RADEON_ROP3_DSo … #define RADEON_ROP3_DSon … #define RADEON_ROP3_DSxn … #define RADEON_ROP3_Dn … #define RADEON_ROP3_SDno … #define RADEON_ROP3_Sn … #define RADEON_ROP3_DSno … #define RADEON_ROP3_DSan … #define RADEON_ROP3_ONE … #define RADEON_ROP3_DPa … #define RADEON_ROP3_PDna … #define RADEON_ROP3_P … #define RADEON_ROP3_DPna … #define RADEON_ROP3_D … #define RADEON_ROP3_DPx … #define RADEON_ROP3_DPo … #define RADEON_ROP3_DPon … #define RADEON_ROP3_PDxn … #define RADEON_ROP3_PDno … #define RADEON_ROP3_Pn … #define RADEON_ROP3_DPno … #define RADEON_ROP3_DPan … #define RADEON_DP_GUI_MASTER_CNTL_C … #define RADEON_DP_MIX … #define RADEON_DP_SRC_BKGD_CLR … #define RADEON_DP_SRC_FRGD_CLR … #define RADEON_DP_WRITE_MASK … #define RADEON_DST_BRES_DEC … #define RADEON_DST_BRES_ERR … #define RADEON_DST_BRES_INC … #define RADEON_DST_BRES_LNTH … #define RADEON_DST_BRES_LNTH_SUB … #define RADEON_DST_HEIGHT … #define RADEON_DST_HEIGHT_WIDTH … #define RADEON_DST_HEIGHT_WIDTH_8 … #define RADEON_DST_HEIGHT_WIDTH_BW … #define RADEON_DST_HEIGHT_Y … #define RADEON_DST_LINE_START … #define RADEON_DST_LINE_END … #define RADEON_DST_LINE_PATCOUNT … #define RADEON_BRES_CNTL_SHIFT … #define RADEON_DST_OFFSET … #define RADEON_DST_PITCH … #define RADEON_DST_PITCH_OFFSET … #define RADEON_DST_PITCH_OFFSET_C … #define RADEON_PITCH_SHIFT … #define RADEON_DST_TILE_LINEAR … #define RADEON_DST_TILE_MACRO … #define RADEON_DST_TILE_MICRO … #define RADEON_DST_TILE_BOTH … #define RADEON_DST_WIDTH … #define RADEON_DST_WIDTH_HEIGHT … #define RADEON_DST_WIDTH_X … #define RADEON_DST_WIDTH_X_INCY … #define RADEON_DST_X … #define RADEON_DST_X_SUB … #define RADEON_DST_X_Y … #define RADEON_DST_Y … #define RADEON_DST_Y_SUB … #define RADEON_DST_Y_X … #define RADEON_FCP_CNTL … #define RADEON_FCP0_SRC_PCICLK … #define RADEON_FCP0_SRC_PCLK … #define RADEON_FCP0_SRC_PCLKb … #define RADEON_FCP0_SRC_HREF … #define RADEON_FCP0_SRC_GND … #define RADEON_FCP0_SRC_HREFb … #define RADEON_FLUSH_1 … #define RADEON_FLUSH_2 … #define RADEON_FLUSH_3 … #define RADEON_FLUSH_4 … #define RADEON_FLUSH_5 … #define RADEON_FLUSH_6 … #define RADEON_FLUSH_7 … #define RADEON_FOG_3D_TABLE_START … #define RADEON_FOG_3D_TABLE_END … #define RADEON_FOG_3D_TABLE_DENSITY … #define RADEON_FOG_TABLE_INDEX … #define RADEON_FOG_TABLE_DATA … #define RADEON_FP_CRTC_H_TOTAL_DISP … #define RADEON_FP_CRTC_V_TOTAL_DISP … #define RADEON_FP_CRTC_H_TOTAL_MASK … #define RADEON_FP_CRTC_H_DISP_MASK … #define RADEON_FP_CRTC_V_TOTAL_MASK … #define RADEON_FP_CRTC_V_DISP_MASK … #define RADEON_FP_H_SYNC_STRT_CHAR_MASK … #define RADEON_FP_H_SYNC_WID_MASK … #define RADEON_FP_V_SYNC_STRT_MASK … #define RADEON_FP_V_SYNC_WID_MASK … #define RADEON_FP_CRTC_H_TOTAL_SHIFT … #define RADEON_FP_CRTC_H_DISP_SHIFT … #define RADEON_FP_CRTC_V_TOTAL_SHIFT … #define RADEON_FP_CRTC_V_DISP_SHIFT … #define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT … #define RADEON_FP_H_SYNC_WID_SHIFT … #define RADEON_FP_V_SYNC_STRT_SHIFT … #define RADEON_FP_V_SYNC_WID_SHIFT … #define RADEON_FP_GEN_CNTL … #define RADEON_FP_FPON … #define RADEON_FP_BLANK_EN … #define RADEON_FP_TMDS_EN … #define RADEON_FP_PANEL_FORMAT … #define RADEON_FP_EN_TMDS … #define RADEON_FP_DETECT_SENSE … #define RADEON_FP_DETECT_INT_POL … #define R200_FP_SOURCE_SEL_MASK … #define R200_FP_SOURCE_SEL_CRTC1 … #define R200_FP_SOURCE_SEL_CRTC2 … #define R200_FP_SOURCE_SEL_RMX … #define R200_FP_SOURCE_SEL_TRANS … #define RADEON_FP_SEL_CRTC1 … #define RADEON_FP_SEL_CRTC2 … #define R300_HPD_SEL(x) … #define RADEON_FP_CRTC_DONT_SHADOW_HPAR … #define RADEON_FP_CRTC_DONT_SHADOW_VPAR … #define RADEON_FP_CRTC_DONT_SHADOW_HEND … #define RADEON_FP_CRTC_USE_SHADOW_VEND … #define RADEON_FP_RMX_HVSYNC_CONTROL_EN … #define RADEON_FP_DFP_SYNC_SEL … #define RADEON_FP_CRTC_LOCK_8DOT … #define RADEON_FP_CRT_SYNC_SEL … #define RADEON_FP_USE_SHADOW_EN … #define RADEON_FP_CRT_SYNC_ALT … #define RADEON_FP2_GEN_CNTL … #define RADEON_FP2_BLANK_EN … #define RADEON_FP2_ON … #define RADEON_FP2_PANEL_FORMAT … #define RADEON_FP2_DETECT_SENSE … #define RADEON_FP2_DETECT_INT_POL … #define R200_FP2_SOURCE_SEL_MASK … #define R200_FP2_SOURCE_SEL_CRTC1 … #define R200_FP2_SOURCE_SEL_CRTC2 … #define R200_FP2_SOURCE_SEL_RMX … #define R200_FP2_SOURCE_SEL_TRANS_UNIT … #define RADEON_FP2_SRC_SEL_MASK … #define RADEON_FP2_SRC_SEL_CRTC2 … #define RADEON_FP2_FP_POL … #define RADEON_FP2_LP_POL … #define RADEON_FP2_SCK_POL … #define RADEON_FP2_LCD_CNTL_MASK … #define RADEON_FP2_PAD_FLOP_EN … #define RADEON_FP2_CRC_EN … #define RADEON_FP2_CRC_READ_EN … #define RADEON_FP2_DVO_EN … #define RADEON_FP2_DVO_RATE_SEL_SDR … #define R200_FP2_DVO_RATE_SEL_SDR … #define R300_FP2_DVO_CLOCK_MODE_SINGLE … #define R300_FP2_DVO_DUAL_CHANNEL_EN … #define RADEON_FP_H_SYNC_STRT_WID … #define RADEON_FP_H2_SYNC_STRT_WID … #define RADEON_FP_HORZ_STRETCH … #define RADEON_FP_HORZ2_STRETCH … #define RADEON_HORZ_STRETCH_RATIO_MASK … #define RADEON_HORZ_STRETCH_RATIO_MAX … #define RADEON_HORZ_PANEL_SIZE … #define RADEON_HORZ_PANEL_SHIFT … #define RADEON_HORZ_STRETCH_PIXREP … #define RADEON_HORZ_STRETCH_BLEND … #define RADEON_HORZ_STRETCH_ENABLE … #define RADEON_HORZ_AUTO_RATIO … #define RADEON_HORZ_FP_LOOP_STRETCH … #define RADEON_HORZ_AUTO_RATIO_INC … #define RADEON_FP_HORZ_VERT_ACTIVE … #define RADEON_FP_V_SYNC_STRT_WID … #define RADEON_FP_VERT_STRETCH … #define RADEON_FP_V2_SYNC_STRT_WID … #define RADEON_FP_VERT2_STRETCH … #define RADEON_VERT_PANEL_SIZE … #define RADEON_VERT_PANEL_SHIFT … #define RADEON_VERT_STRETCH_RATIO_MASK … #define RADEON_VERT_STRETCH_RATIO_SHIFT … #define RADEON_VERT_STRETCH_RATIO_MAX … #define RADEON_VERT_STRETCH_ENABLE … #define RADEON_VERT_STRETCH_LINEREP … #define RADEON_VERT_STRETCH_BLEND … #define RADEON_VERT_AUTO_RATIO_EN … #define RADEON_VERT_AUTO_RATIO_INC … #define RADEON_VERT_STRETCH_RESERVED … #define RS400_FP_2ND_GEN_CNTL … #define RS400_FP_2ND_ON … #define RS400_FP_2ND_BLANK_EN … #define RS400_TMDS_2ND_EN … #define RS400_PANEL_FORMAT_2ND … #define RS400_FP_2ND_EN_TMDS … #define RS400_FP_2ND_DETECT_SENSE … #define RS400_FP_2ND_SOURCE_SEL_MASK … #define RS400_FP_2ND_SOURCE_SEL_CRTC1 … #define RS400_FP_2ND_SOURCE_SEL_CRTC2 … #define RS400_FP_2ND_SOURCE_SEL_RMX … #define RS400_FP_2ND_DETECT_EN … #define RS400_HPD_2ND_SEL … #define RS400_FP2_2_GEN_CNTL … #define RS400_FP2_2_BLANK_EN … #define RS400_FP2_2_ON … #define RS400_FP2_2_PANEL_FORMAT … #define RS400_FP2_2_DETECT_SENSE … #define RS400_FP2_2_SOURCE_SEL_MASK … #define RS400_FP2_2_SOURCE_SEL_CRTC1 … #define RS400_FP2_2_SOURCE_SEL_CRTC2 … #define RS400_FP2_2_SOURCE_SEL_RMX … #define RS400_FP2_2_DVO2_EN … #define RS400_TMDS2_CNTL … #define RS400_TMDS2_TRANSMITTER_CNTL … #define RS400_TMDS2_PLLEN … #define RS400_TMDS2_PLLRST … #define RADEON_GEN_INT_CNTL … #define RADEON_CRTC_VBLANK_MASK … #define RADEON_FP_DETECT_MASK … #define RADEON_CRTC2_VBLANK_MASK … #define RADEON_FP2_DETECT_MASK … #define RADEON_GUI_IDLE_MASK … #define RADEON_SW_INT_ENABLE … #define RADEON_GEN_INT_STATUS … #define AVIVO_DISPLAY_INT_STATUS … #define RADEON_CRTC_VBLANK_STAT … #define RADEON_CRTC_VBLANK_STAT_ACK … #define RADEON_FP_DETECT_STAT … #define RADEON_FP_DETECT_STAT_ACK … #define RADEON_CRTC2_VBLANK_STAT … #define RADEON_CRTC2_VBLANK_STAT_ACK … #define RADEON_FP2_DETECT_STAT … #define RADEON_FP2_DETECT_STAT_ACK … #define RADEON_GUI_IDLE_STAT … #define RADEON_GUI_IDLE_STAT_ACK … #define RADEON_SW_INT_FIRE … #define RADEON_SW_INT_TEST … #define RADEON_SW_INT_TEST_ACK … #define RADEON_GENENB … #define RADEON_GENFC_RD … #define RADEON_GENFC_WT … #define RADEON_GENMO_RD … #define RADEON_GENMO_WT … #define RADEON_GENS0 … #define RADEON_GENS1 … #define RADEON_GPIO_MONID … #define RADEON_GPIO_MONIDB … #define RADEON_GPIO_CRT2_DDC … #define RADEON_GPIO_DVI_DDC … #define RADEON_GPIO_VGA_DDC … #define RADEON_GPIO_A_0 … #define RADEON_GPIO_A_1 … #define RADEON_GPIO_Y_0 … #define RADEON_GPIO_Y_1 … #define RADEON_GPIO_Y_SHIFT_0 … #define RADEON_GPIO_Y_SHIFT_1 … #define RADEON_GPIO_EN_0 … #define RADEON_GPIO_EN_1 … #define RADEON_GPIO_MASK_0 … #define RADEON_GPIO_MASK_1 … #define RADEON_GRPH8_DATA … #define RADEON_GRPH8_IDX … #define RADEON_GUI_SCRATCH_REG0 … #define RADEON_GUI_SCRATCH_REG1 … #define RADEON_GUI_SCRATCH_REG2 … #define RADEON_GUI_SCRATCH_REG3 … #define RADEON_GUI_SCRATCH_REG4 … #define RADEON_GUI_SCRATCH_REG5 … #define RADEON_HEADER … #define RADEON_HOST_DATA0 … #define RADEON_HOST_DATA1 … #define RADEON_HOST_DATA2 … #define RADEON_HOST_DATA3 … #define RADEON_HOST_DATA4 … #define RADEON_HOST_DATA5 … #define RADEON_HOST_DATA6 … #define RADEON_HOST_DATA7 … #define RADEON_HOST_DATA_LAST … #define RADEON_HOST_PATH_CNTL … #define RADEON_HP_LIN_RD_CACHE_DIS … #define RADEON_HDP_READ_BUFFER_INVALIDATE … #define RADEON_HDP_SOFT_RESET … #define RADEON_HDP_APER_CNTL … #define RADEON_HTOTAL_CNTL … #define RADEON_HTOT_CNTL_VGA_EN … #define RADEON_HTOTAL2_CNTL … /* Multimedia I2C bus */ #define RADEON_I2C_CNTL_0 … #define RADEON_I2C_DONE … #define RADEON_I2C_NACK … #define RADEON_I2C_HALT … #define RADEON_I2C_SOFT_RST … #define RADEON_I2C_DRIVE_EN … #define RADEON_I2C_DRIVE_SEL … #define RADEON_I2C_START … #define RADEON_I2C_STOP … #define RADEON_I2C_RECEIVE … #define RADEON_I2C_ABORT … #define RADEON_I2C_GO … #define RADEON_I2C_PRESCALE_SHIFT … #define RADEON_I2C_CNTL_1 … #define RADEON_I2C_DATA_COUNT_SHIFT … #define RADEON_I2C_ADDR_COUNT_SHIFT … #define RADEON_I2C_INTRA_BYTE_DELAY_SHIFT … #define RADEON_I2C_SEL … #define RADEON_I2C_EN … #define RADEON_I2C_TIME_LIMIT_SHIFT … #define RADEON_I2C_DATA … #define RADEON_DVI_I2C_CNTL_0 … #define R200_DVI_I2C_PIN_SEL(x) … #define R200_SEL_DDC1 … #define R200_SEL_DDC2 … #define R200_SEL_DDC3 … #define RADEON_SW_WANTS_TO_USE_DVI_I2C … #define RADEON_SW_CAN_USE_DVI_I2C … #define RADEON_SW_DONE_USING_DVI_I2C … #define RADEON_HW_NEEDS_DVI_I2C … #define RADEON_ABORT_HW_DVI_I2C … #define RADEON_HW_USING_DVI_I2C … #define RADEON_DVI_I2C_CNTL_1 … #define RADEON_DVI_I2C_DATA … #define RADEON_INTERRUPT_LINE … #define RADEON_INTERRUPT_PIN … #define RADEON_IO_BASE … #define RADEON_LATENCY … #define RADEON_LEAD_BRES_DEC … #define RADEON_LEAD_BRES_LNTH … #define RADEON_LEAD_BRES_LNTH_SUB … #define RADEON_LVDS_GEN_CNTL … #define RADEON_LVDS_ON … #define RADEON_LVDS_DISPLAY_DIS … #define RADEON_LVDS_PANEL_TYPE … #define RADEON_LVDS_PANEL_FORMAT … #define RADEON_LVDS_NO_FM … #define RADEON_LVDS_2_GREY … #define RADEON_LVDS_4_GREY … #define RADEON_LVDS_RST_FM … #define RADEON_LVDS_EN … #define RADEON_LVDS_BL_MOD_LEVEL_SHIFT … #define RADEON_LVDS_BL_MOD_LEVEL_MASK … #define RADEON_LVDS_BL_MOD_EN … #define RADEON_LVDS_BL_CLK_SEL … #define RADEON_LVDS_DIGON … #define RADEON_LVDS_BLON … #define RADEON_LVDS_FP_POL_LOW … #define RADEON_LVDS_LP_POL_LOW … #define RADEON_LVDS_DTM_POL_LOW … #define RADEON_LVDS_SEL_CRTC2 … #define RADEON_LVDS_FPDI_EN … #define RADEON_LVDS_HSYNC_DELAY_SHIFT … #define RADEON_LVDS_PLL_CNTL … #define RADEON_HSYNC_DELAY_SHIFT … #define RADEON_HSYNC_DELAY_MASK … #define RADEON_LVDS_PLL_EN … #define RADEON_LVDS_PLL_RESET … #define R300_LVDS_SRC_SEL_MASK … #define R300_LVDS_SRC_SEL_CRTC1 … #define R300_LVDS_SRC_SEL_CRTC2 … #define R300_LVDS_SRC_SEL_RMX … #define RADEON_LVDS_SS_GEN_CNTL … #define RADEON_LVDS_PWRSEQ_DELAY1_SHIFT … #define RADEON_LVDS_PWRSEQ_DELAY2_SHIFT … #define RADEON_MAX_LATENCY … #define RADEON_DISPLAY_BASE_ADDR … #define RADEON_DISPLAY2_BASE_ADDR … #define RADEON_OV0_BASE_ADDR … #define RADEON_NB_TOM … #define R300_MC_INIT_MISC_LAT_TIMER … #define R300_MC_DISP0R_INIT_LAT_SHIFT … #define R300_MC_DISP0R_INIT_LAT_MASK … #define R300_MC_DISP1R_INIT_LAT_SHIFT … #define R300_MC_DISP1R_INIT_LAT_MASK … #define RADEON_MCLK_CNTL … #define RADEON_MCLKA_SRC_SEL_MASK … #define RADEON_FORCEON_MCLKA … #define RADEON_FORCEON_MCLKB … #define RADEON_FORCEON_YCLKA … #define RADEON_FORCEON_YCLKB … #define RADEON_FORCEON_MC … #define RADEON_FORCEON_AIC … #define R300_DISABLE_MC_MCLKA … #define R300_DISABLE_MC_MCLKB … #define RADEON_MCLK_MISC … #define RADEON_MC_MCLK_MAX_DYN_STOP_LAT … #define RADEON_IO_MCLK_MAX_DYN_STOP_LAT … #define RADEON_MC_MCLK_DYN_ENABLE … #define RADEON_IO_MCLK_DYN_ENABLE … #define RADEON_GPIOPAD_MASK … #define RADEON_GPIOPAD_A … #define RADEON_GPIOPAD_EN … #define RADEON_GPIOPAD_Y … #define RADEON_MDGPIO_MASK … #define RADEON_MDGPIO_A … #define RADEON_MDGPIO_EN … #define RADEON_MDGPIO_Y … #define RADEON_MEM_ADDR_CONFIG … #define RADEON_MEM_BASE … #define RADEON_MEM_CNTL … #define RADEON_MEM_NUM_CHANNELS_MASK … #define RADEON_MEM_USE_B_CH_ONLY … #define RV100_HALF_MODE … #define R300_MEM_NUM_CHANNELS_MASK … #define R300_MEM_USE_CD_CH_ONLY … #define RADEON_MEM_TIMING_CNTL … #define RADEON_MEM_INIT_LAT_TIMER … #define RADEON_MEM_INTF_CNTL … #define RADEON_MEM_SDRAM_MODE_REG … #define RADEON_SDRAM_MODE_MASK … #define RADEON_B3MEM_RESET_MASK … #define RADEON_MEM_CFG_TYPE_DDR … #define RADEON_MEM_STR_CNTL … #define RADEON_MEM_PWRUP_COMPL_A … #define RADEON_MEM_PWRUP_COMPL_B … #define R300_MEM_PWRUP_COMPL_C … #define R300_MEM_PWRUP_COMPL_D … #define RADEON_MEM_PWRUP_COMPLETE … #define R300_MEM_PWRUP_COMPLETE … #define RADEON_MC_STATUS … #define RADEON_MC_IDLE … #define R300_MC_IDLE … #define RADEON_MEM_VGA_RP_SEL … #define RADEON_MEM_VGA_WP_SEL … #define RADEON_MIN_GRANT … #define RADEON_MM_DATA … #define RADEON_MM_INDEX … #define RADEON_MM_APER … #define RADEON_MPLL_CNTL … #define RADEON_MPP_TB_CONFIG … #define RADEON_MPP_GP_CONFIG … #define RADEON_SEPROM_CNTL1 … #define RADEON_SCK_PRESCALE_SHIFT … #define RADEON_SCK_PRESCALE_MASK … #define R300_MC_IND_INDEX … #define R300_MC_IND_ADDR_MASK … #define R300_MC_IND_WR_EN … #define R300_MC_IND_DATA … #define R300_MC_READ_CNTL_AB … #define R300_MEM_RBS_POSITION_A_MASK … #define R300_MC_READ_CNTL_CD_mcind … #define R300_MEM_RBS_POSITION_C_MASK … #define RADEON_N_VIF_COUNT … #define RADEON_OV0_AUTO_FLIP_CNTL … #define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM … #define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD … #define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD … #define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD … #define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE … #define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT … #define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN … #define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN … #define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN … #define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE … #define RADEON_OV0_COLOUR_CNTL … #define RADEON_OV0_DEINTERLACE_PATTERN … #define RADEON_OV0_EXCLUSIVE_HORZ … #define RADEON_EXCL_HORZ_START_MASK … #define RADEON_EXCL_HORZ_END_MASK … #define RADEON_EXCL_HORZ_BACK_PORCH_MASK … #define RADEON_EXCL_HORZ_EXCLUSIVE_EN … #define RADEON_OV0_EXCLUSIVE_VERT … #define RADEON_EXCL_VERT_START_MASK … #define RADEON_EXCL_VERT_END_MASK … #define RADEON_OV0_FILTER_CNTL … #define RADEON_FILTER_PROGRAMMABLE_COEF … #define RADEON_FILTER_HC_COEF_HORZ_Y … #define RADEON_FILTER_HC_COEF_HORZ_UV … #define RADEON_FILTER_HC_COEF_VERT_Y … #define RADEON_FILTER_HC_COEF_VERT_UV … #define RADEON_FILTER_HARDCODED_COEF … #define RADEON_FILTER_COEF_MASK … #define RADEON_OV0_FOUR_TAP_COEF_0 … #define RADEON_OV0_FOUR_TAP_COEF_1 … #define RADEON_OV0_FOUR_TAP_COEF_2 … #define RADEON_OV0_FOUR_TAP_COEF_3 … #define RADEON_OV0_FOUR_TAP_COEF_4 … #define RADEON_OV0_FLAG_CNTL … #define RADEON_OV0_GAMMA_000_00F … #define RADEON_OV0_GAMMA_010_01F … #define RADEON_OV0_GAMMA_020_03F … #define RADEON_OV0_GAMMA_040_07F … #define RADEON_OV0_GAMMA_080_0BF … #define RADEON_OV0_GAMMA_0C0_0FF … #define RADEON_OV0_GAMMA_100_13F … #define RADEON_OV0_GAMMA_140_17F … #define RADEON_OV0_GAMMA_180_1BF … #define RADEON_OV0_GAMMA_1C0_1FF … #define RADEON_OV0_GAMMA_200_23F … #define RADEON_OV0_GAMMA_240_27F … #define RADEON_OV0_GAMMA_280_2BF … #define RADEON_OV0_GAMMA_2C0_2FF … #define RADEON_OV0_GAMMA_300_33F … #define RADEON_OV0_GAMMA_340_37F … #define RADEON_OV0_GAMMA_380_3BF … #define RADEON_OV0_GAMMA_3C0_3FF … #define RADEON_OV0_GRAPHICS_KEY_CLR_LOW … #define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH … #define RADEON_OV0_H_INC … #define RADEON_OV0_KEY_CNTL … #define RADEON_VIDEO_KEY_FN_MASK … #define RADEON_VIDEO_KEY_FN_FALSE … #define RADEON_VIDEO_KEY_FN_TRUE … #define RADEON_VIDEO_KEY_FN_EQ … #define RADEON_VIDEO_KEY_FN_NE … #define RADEON_GRAPHIC_KEY_FN_MASK … #define RADEON_GRAPHIC_KEY_FN_FALSE … #define RADEON_GRAPHIC_KEY_FN_TRUE … #define RADEON_GRAPHIC_KEY_FN_EQ … #define RADEON_GRAPHIC_KEY_FN_NE … #define RADEON_CMP_MIX_MASK … #define RADEON_CMP_MIX_OR … #define RADEON_CMP_MIX_AND … #define RADEON_OV0_LIN_TRANS_A … #define RADEON_OV0_LIN_TRANS_B … #define RADEON_OV0_LIN_TRANS_C … #define RADEON_OV0_LIN_TRANS_D … #define RADEON_OV0_LIN_TRANS_E … #define RADEON_OV0_LIN_TRANS_F … #define RADEON_OV0_P1_BLANK_LINES_AT_TOP … #define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK … #define RADEON_P1_ACTIVE_LINES_M1 … #define RADEON_OV0_P1_H_ACCUM_INIT … #define RADEON_OV0_P1_V_ACCUM_INIT … #define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT … #define RADEON_OV0_P1_V_ACCUM_INIT_MASK … #define RADEON_OV0_P1_X_START_END … #define RADEON_OV0_P2_X_START_END … #define RADEON_OV0_P23_BLANK_LINES_AT_TOP … #define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK … #define RADEON_P23_ACTIVE_LINES_M1 … #define RADEON_OV0_P23_H_ACCUM_INIT … #define RADEON_OV0_P23_V_ACCUM_INIT … #define RADEON_OV0_P3_X_START_END … #define RADEON_OV0_REG_LOAD_CNTL … #define RADEON_REG_LD_CTL_LOCK … #define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK … #define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP … #define RADEON_REG_LD_CTL_LOCK_READBACK … #define RADEON_REG_LD_CTL_FLIP_READBACK … #define RADEON_OV0_SCALE_CNTL … #define RADEON_SCALER_HORZ_PICK_NEAREST … #define RADEON_SCALER_VERT_PICK_NEAREST … #define RADEON_SCALER_SIGNED_UV … #define RADEON_SCALER_GAMMA_SEL_MASK … #define RADEON_SCALER_GAMMA_SEL_BRIGHT … #define RADEON_SCALER_GAMMA_SEL_G22 … #define RADEON_SCALER_GAMMA_SEL_G18 … #define RADEON_SCALER_GAMMA_SEL_G14 … #define RADEON_SCALER_COMCORE_SHIFT_UP_ONE … #define RADEON_SCALER_SURFAC_FORMAT … #define RADEON_SCALER_SOURCE_15BPP … #define RADEON_SCALER_SOURCE_16BPP … #define RADEON_SCALER_SOURCE_32BPP … #define RADEON_SCALER_SOURCE_YUV9 … #define RADEON_SCALER_SOURCE_YUV12 … #define RADEON_SCALER_SOURCE_VYUY422 … #define RADEON_SCALER_SOURCE_YVYU422 … #define RADEON_SCALER_ADAPTIVE_DEINT … #define RADEON_SCALER_TEMPORAL_DEINT … #define RADEON_SCALER_CRTC_SEL … #define RADEON_SCALER_SMART_SWITCH … #define RADEON_SCALER_BURST_PER_PLANE … #define RADEON_SCALER_DOUBLE_BUFFER … #define RADEON_SCALER_DIS_LIMIT … #define RADEON_SCALER_LIN_TRANS_BYPASS … #define RADEON_SCALER_INT_EMU … #define RADEON_SCALER_ENABLE … #define RADEON_SCALER_SOFT_RESET … #define RADEON_OV0_STEP_BY … #define RADEON_OV0_TEST … #define RADEON_OV0_V_INC … #define RADEON_OV0_VID_BUF_PITCH0_VALUE … #define RADEON_OV0_VID_BUF_PITCH1_VALUE … #define RADEON_OV0_VID_BUF0_BASE_ADRS … #define RADEON_VIF_BUF0_PITCH_SEL … #define RADEON_VIF_BUF0_TILE_ADRS … #define RADEON_VIF_BUF0_BASE_ADRS_MASK … #define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK … #define RADEON_OV0_VID_BUF1_BASE_ADRS … #define RADEON_VIF_BUF1_PITCH_SEL … #define RADEON_VIF_BUF1_TILE_ADRS … #define RADEON_VIF_BUF1_BASE_ADRS_MASK … #define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK … #define RADEON_OV0_VID_BUF2_BASE_ADRS … #define RADEON_VIF_BUF2_PITCH_SEL … #define RADEON_VIF_BUF2_TILE_ADRS … #define RADEON_VIF_BUF2_BASE_ADRS_MASK … #define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK … #define RADEON_OV0_VID_BUF3_BASE_ADRS … #define RADEON_OV0_VID_BUF4_BASE_ADRS … #define RADEON_OV0_VID_BUF5_BASE_ADRS … #define RADEON_OV0_VIDEO_KEY_CLR_HIGH … #define RADEON_OV0_VIDEO_KEY_CLR_LOW … #define RADEON_OV0_Y_X_START … #define RADEON_OV0_Y_X_END … #define RADEON_OV1_Y_X_START … #define RADEON_OV1_Y_X_END … #define RADEON_OVR_CLR … #define RADEON_OVR_WID_LEFT_RIGHT … #define RADEON_OVR_WID_TOP_BOTTOM … #define RADEON_OVR2_CLR … #define RADEON_OVR2_WID_LEFT_RIGHT … #define RADEON_OVR2_WID_TOP_BOTTOM … /* first capture unit */ #define RADEON_CAP0_BUF0_OFFSET … #define RADEON_CAP0_BUF1_OFFSET … #define RADEON_CAP0_BUF0_EVEN_OFFSET … #define RADEON_CAP0_BUF1_EVEN_OFFSET … #define RADEON_CAP0_BUF_PITCH … #define RADEON_CAP0_V_WINDOW … #define RADEON_CAP0_H_WINDOW … #define RADEON_CAP0_VBI0_OFFSET … #define RADEON_CAP0_VBI1_OFFSET … #define RADEON_CAP0_VBI_V_WINDOW … #define RADEON_CAP0_VBI_H_WINDOW … #define RADEON_CAP0_PORT_MODE_CNTL … #define RADEON_CAP0_TRIG_CNTL … #define RADEON_CAP0_DEBUG … #define RADEON_CAP0_CONFIG … #define RADEON_CAP0_CONFIG_CONTINUOS … #define RADEON_CAP0_CONFIG_START_FIELD_EVEN … #define RADEON_CAP0_CONFIG_START_BUF_GET … #define RADEON_CAP0_CONFIG_START_BUF_SET … #define RADEON_CAP0_CONFIG_BUF_TYPE_ALT … #define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME … #define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME … #define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE … #define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE … #define RADEON_CAP0_CONFIG_MIRROR_EN … #define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN … #define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV … #define RADEON_CAP0_CONFIG_ANC_DECODE_EN … #define RADEON_CAP0_CONFIG_VBI_EN … #define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN … #define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN … #define RADEON_CAP0_CONFIG_FAKE_FIELD_EN … #define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE … #define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE … #define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 … #define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 … #define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 … #define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 … #define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE … #define RADEON_CAP0_CONFIG_FORMAT_CCIR656 … #define RADEON_CAP0_CONFIG_FORMAT_ZV … #define RADEON_CAP0_CONFIG_FORMAT_VIP … #define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT … #define RADEON_CAP0_CONFIG_HORZ_DECIMATOR … #define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 … #define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 … #define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 … #define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 … #define RADEON_CAP0_ANC_ODD_OFFSET … #define RADEON_CAP0_ANC_EVEN_OFFSET … #define RADEON_CAP0_ANC_H_WINDOW … #define RADEON_CAP0_VIDEO_SYNC_TEST … #define RADEON_CAP0_ONESHOT_BUF_OFFSET … #define RADEON_CAP0_BUF_STATUS … /* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */ /* #define RADEON_CAP0_XSHARPNESS 0x097C */ #define RADEON_CAP0_VBI2_OFFSET … #define RADEON_CAP0_VBI3_OFFSET … #define RADEON_CAP0_ANC2_OFFSET … #define RADEON_CAP0_ANC3_OFFSET … #define RADEON_VID_BUFFER_CONTROL … /* second capture unit */ #define RADEON_CAP1_BUF0_OFFSET … #define RADEON_CAP1_BUF1_OFFSET … #define RADEON_CAP1_BUF0_EVEN_OFFSET … #define RADEON_CAP1_BUF1_EVEN_OFFSET … #define RADEON_CAP1_BUF_PITCH … #define RADEON_CAP1_V_WINDOW … #define RADEON_CAP1_H_WINDOW … #define RADEON_CAP1_VBI_ODD_OFFSET … #define RADEON_CAP1_VBI_EVEN_OFFSET … #define RADEON_CAP1_VBI_V_WINDOW … #define RADEON_CAP1_VBI_H_WINDOW … #define RADEON_CAP1_PORT_MODE_CNTL … #define RADEON_CAP1_TRIG_CNTL … #define RADEON_CAP1_DEBUG … #define RADEON_CAP1_CONFIG … #define RADEON_CAP1_ANC_ODD_OFFSET … #define RADEON_CAP1_ANC_EVEN_OFFSET … #define RADEON_CAP1_ANC_H_WINDOW … #define RADEON_CAP1_VIDEO_SYNC_TEST … #define RADEON_CAP1_ONESHOT_BUF_OFFSET … #define RADEON_CAP1_BUF_STATUS … #define RADEON_CAP1_DWNSC_XRATIO … #define RADEON_CAP1_XSHARPNESS … /* misc multimedia registers */ #define RADEON_IDCT_RUNS … #define RADEON_IDCT_LEVELS … #define RADEON_IDCT_CONTROL … #define RADEON_IDCT_AUTH_CONTROL … #define RADEON_IDCT_AUTH … #define RADEON_P2PLL_CNTL … #define RADEON_P2PLL_RESET … #define RADEON_P2PLL_SLEEP … #define RADEON_P2PLL_PVG_MASK … #define RADEON_P2PLL_PVG_SHIFT … #define RADEON_P2PLL_ATOMIC_UPDATE_EN … #define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN … #define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC … #define RADEON_P2PLL_DIV_0 … #define RADEON_P2PLL_FB0_DIV_MASK … #define RADEON_P2PLL_POST0_DIV_MASK … #define RADEON_P2PLL_REF_DIV … #define RADEON_P2PLL_REF_DIV_MASK … #define RADEON_P2PLL_ATOMIC_UPDATE_R … #define RADEON_P2PLL_ATOMIC_UPDATE_W … #define R300_PPLL_REF_DIV_ACC_MASK … #define R300_PPLL_REF_DIV_ACC_SHIFT … #define RADEON_PALETTE_DATA … #define RADEON_PALETTE_30_DATA … #define RADEON_PALETTE_INDEX … #define RADEON_PCI_GART_PAGE … #define RADEON_PIXCLKS_CNTL … #define RADEON_PIX2CLK_SRC_SEL_MASK … #define RADEON_PIX2CLK_SRC_SEL_CPUCLK … #define RADEON_PIX2CLK_SRC_SEL_PSCANCLK … #define RADEON_PIX2CLK_SRC_SEL_BYTECLK … #define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK … #define RADEON_PIX2CLK_ALWAYS_ONb … #define RADEON_PIX2CLK_DAC_ALWAYS_ONb … #define RADEON_PIXCLK_TV_SRC_SEL … #define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb … #define R300_DVOCLK_ALWAYS_ONb … #define RADEON_PIXCLK_BLEND_ALWAYS_ONb … #define RADEON_PIXCLK_GV_ALWAYS_ONb … #define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb … #define R300_PIXCLK_DVO_ALWAYS_ONb … #define RADEON_PIXCLK_LVDS_ALWAYS_ONb … #define RADEON_PIXCLK_TMDS_ALWAYS_ONb … #define R300_PIXCLK_TRANS_ALWAYS_ONb … #define R300_PIXCLK_TVO_ALWAYS_ONb … #define R300_P2G2CLK_ALWAYS_ONb … #define R300_P2G2CLK_DAC_ALWAYS_ONb … #define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF … #define RADEON_PLANE_3D_MASK_C … #define RADEON_PLL_TEST_CNTL … #define RADEON_PLL_MASK_READ_B … #define RADEON_PMI_CAP_ID … #define RADEON_PMI_DATA … #define RADEON_PMI_NXT_CAP_PTR … #define RADEON_PMI_PMC_REG … #define RADEON_PMI_PMCSR_REG … #define RADEON_PMI_REGISTER … #define RADEON_PPLL_CNTL … #define RADEON_PPLL_RESET … #define RADEON_PPLL_SLEEP … #define RADEON_PPLL_PVG_MASK … #define RADEON_PPLL_PVG_SHIFT … #define RADEON_PPLL_ATOMIC_UPDATE_EN … #define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN … #define RADEON_PPLL_ATOMIC_UPDATE_VSYNC … #define RADEON_PPLL_DIV_0 … #define RADEON_PPLL_DIV_1 … #define RADEON_PPLL_DIV_2 … #define RADEON_PPLL_DIV_3 … #define RADEON_PPLL_FB3_DIV_MASK … #define RADEON_PPLL_POST3_DIV_MASK … #define RADEON_PPLL_REF_DIV … #define RADEON_PPLL_REF_DIV_MASK … #define RADEON_PPLL_ATOMIC_UPDATE_R … #define RADEON_PPLL_ATOMIC_UPDATE_W … #define RADEON_PWR_MNGMT_CNTL_STATUS … #define RADEON_RBBM_GUICNTL … #define RADEON_HOST_DATA_SWAP_NONE … #define RADEON_HOST_DATA_SWAP_16BIT … #define RADEON_HOST_DATA_SWAP_32BIT … #define RADEON_HOST_DATA_SWAP_HDW … #define RADEON_RBBM_SOFT_RESET … #define RADEON_SOFT_RESET_CP … #define RADEON_SOFT_RESET_HI … #define RADEON_SOFT_RESET_SE … #define RADEON_SOFT_RESET_RE … #define RADEON_SOFT_RESET_PP … #define RADEON_SOFT_RESET_E2 … #define RADEON_SOFT_RESET_RB … #define RADEON_SOFT_RESET_HDP … #define RADEON_RBBM_STATUS … #define RADEON_RBBM_FIFOCNT_MASK … #define RADEON_RBBM_ACTIVE … #define RADEON_RB2D_DSTCACHE_CTLSTAT … #define RADEON_RB2D_DC_FLUSH … #define RADEON_RB2D_DC_FREE … #define RADEON_RB2D_DC_FLUSH_ALL … #define RADEON_RB2D_DC_BUSY … #define RADEON_RB2D_DSTCACHE_MODE … #define RADEON_DSTCACHE_CTLSTAT … #define RADEON_RB3D_ZCACHE_MODE … #define RADEON_RB3D_ZCACHE_CTLSTAT … #define RADEON_RB3D_ZC_FLUSH_ALL … #define RADEON_RB3D_DSTCACHE_MODE … #define RADEON_RB3D_DC_CACHE_ENABLE … #define RADEON_RB3D_DC_2D_CACHE_DISABLE … #define RADEON_RB3D_DC_3D_CACHE_DISABLE … #define RADEON_RB3D_DC_CACHE_DISABLE … #define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 … #define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 … #define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH … #define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH … #define R200_RB3D_DC_2D_CACHE_AUTOFREE … #define R200_RB3D_DC_3D_CACHE_AUTOFREE … #define RADEON_RB3D_DC_FORCE_RMW … #define RADEON_RB3D_DC_DISABLE_RI_FILL … #define RADEON_RB3D_DC_DISABLE_RI_READ … #define RADEON_RB3D_DSTCACHE_CTLSTAT … #define RADEON_RB3D_DC_FLUSH … #define RADEON_RB3D_DC_FREE … #define RADEON_RB3D_DC_FLUSH_ALL … #define RADEON_RB3D_DC_BUSY … #define RADEON_REG_BASE … #define RADEON_REGPROG_INF … #define RADEON_REVISION_ID … #define RADEON_SC_BOTTOM … #define RADEON_SC_BOTTOM_RIGHT … #define RADEON_SC_BOTTOM_RIGHT_C … #define RADEON_SC_LEFT … #define RADEON_SC_RIGHT … #define RADEON_SC_TOP … #define RADEON_SC_TOP_LEFT … #define RADEON_SC_TOP_LEFT_C … #define RADEON_SC_SIGN_MASK_LO … #define RADEON_SC_SIGN_MASK_HI … #define RADEON_M_SPLL_REF_FB_DIV … #define RADEON_M_SPLL_REF_DIV_SHIFT … #define RADEON_M_SPLL_REF_DIV_MASK … #define RADEON_MPLL_FB_DIV_SHIFT … #define RADEON_MPLL_FB_DIV_MASK … #define RADEON_SPLL_FB_DIV_SHIFT … #define RADEON_SPLL_FB_DIV_MASK … #define RADEON_SPLL_CNTL … #define RADEON_SPLL_SLEEP … #define RADEON_SPLL_RESET … #define RADEON_SPLL_PCP_MASK … #define RADEON_SPLL_PCP_SHIFT … #define RADEON_SPLL_PVG_MASK … #define RADEON_SPLL_PVG_SHIFT … #define RADEON_SPLL_PDC_MASK … #define RADEON_SPLL_PDC_SHIFT … #define RADEON_SCLK_CNTL … #define RADEON_SCLK_SRC_SEL_MASK … #define RADEON_DYN_STOP_LAT_MASK … #define RADEON_CP_MAX_DYN_STOP_LAT … #define RADEON_SCLK_FORCEON_MASK … #define RADEON_SCLK_FORCE_DISP2 … #define RADEON_SCLK_FORCE_CP … #define RADEON_SCLK_FORCE_HDP … #define RADEON_SCLK_FORCE_DISP1 … #define RADEON_SCLK_FORCE_TOP … #define RADEON_SCLK_FORCE_E2 … #define RADEON_SCLK_FORCE_SE … #define RADEON_SCLK_FORCE_IDCT … #define RADEON_SCLK_FORCE_VIP … #define RADEON_SCLK_FORCE_RE … #define RADEON_SCLK_FORCE_PB … #define RADEON_SCLK_FORCE_TAM … #define RADEON_SCLK_FORCE_TDM … #define RADEON_SCLK_FORCE_RB … #define RADEON_SCLK_FORCE_TV_SCLK … #define RADEON_SCLK_FORCE_SUBPIC … #define RADEON_SCLK_FORCE_OV0 … #define R300_SCLK_FORCE_VAP … #define R300_SCLK_FORCE_SR … #define R300_SCLK_FORCE_PX … #define R300_SCLK_FORCE_TX … #define R300_SCLK_FORCE_US … #define R300_SCLK_FORCE_SU … #define R300_SCLK_CNTL2 … #define R300_SCLK_TCL_MAX_DYN_STOP_LAT … #define R300_SCLK_GA_MAX_DYN_STOP_LAT … #define R300_SCLK_CBA_MAX_DYN_STOP_LAT … #define R300_SCLK_FORCE_TCL … #define R300_SCLK_FORCE_CBA … #define R300_SCLK_FORCE_GA … #define RADEON_SCLK_MORE_CNTL … #define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT … #define RADEON_SCLK_MORE_FORCEON … #define RADEON_SDRAM_MODE_REG … #define RADEON_SEQ8_DATA … #define RADEON_SEQ8_IDX … #define RADEON_SNAPSHOT_F_COUNT … #define RADEON_SNAPSHOT_VH_COUNTS … #define RADEON_SNAPSHOT_VIF_COUNT … #define RADEON_SRC_OFFSET … #define RADEON_SRC_PITCH … #define RADEON_SRC_PITCH_OFFSET … #define RADEON_SRC_SC_BOTTOM … #define RADEON_SRC_SC_BOTTOM_RIGHT … #define RADEON_SRC_SC_RIGHT … #define RADEON_SRC_X … #define RADEON_SRC_X_Y … #define RADEON_SRC_Y … #define RADEON_SRC_Y_X … #define RADEON_STATUS … #define RADEON_SUBPIC_CNTL … #define RADEON_SUB_CLASS … #define RADEON_SURFACE_CNTL … #define RADEON_SURF_TRANSLATION_DIS … #define RADEON_NONSURF_AP0_SWP_16BPP … #define RADEON_NONSURF_AP0_SWP_32BPP … #define RADEON_NONSURF_AP1_SWP_16BPP … #define RADEON_NONSURF_AP1_SWP_32BPP … #define RADEON_SURFACE0_INFO … #define RADEON_SURF_TILE_COLOR_MACRO … #define RADEON_SURF_TILE_COLOR_BOTH … #define RADEON_SURF_TILE_DEPTH_32BPP … #define RADEON_SURF_TILE_DEPTH_16BPP … #define R200_SURF_TILE_NONE … #define R200_SURF_TILE_COLOR_MACRO … #define R200_SURF_TILE_COLOR_MICRO … #define R200_SURF_TILE_COLOR_BOTH … #define R200_SURF_TILE_DEPTH_32BPP … #define R200_SURF_TILE_DEPTH_16BPP … #define R300_SURF_TILE_NONE … #define R300_SURF_TILE_COLOR_MACRO … #define R300_SURF_TILE_DEPTH_32BPP … #define RADEON_SURF_AP0_SWP_16BPP … #define RADEON_SURF_AP0_SWP_32BPP … #define RADEON_SURF_AP1_SWP_16BPP … #define RADEON_SURF_AP1_SWP_32BPP … #define RADEON_SURFACE0_LOWER_BOUND … #define RADEON_SURFACE0_UPPER_BOUND … #define RADEON_SURFACE1_INFO … #define RADEON_SURFACE1_LOWER_BOUND … #define RADEON_SURFACE1_UPPER_BOUND … #define RADEON_SURFACE2_INFO … #define RADEON_SURFACE2_LOWER_BOUND … #define RADEON_SURFACE2_UPPER_BOUND … #define RADEON_SURFACE3_INFO … #define RADEON_SURFACE3_LOWER_BOUND … #define RADEON_SURFACE3_UPPER_BOUND … #define RADEON_SURFACE4_INFO … #define RADEON_SURFACE4_LOWER_BOUND … #define RADEON_SURFACE4_UPPER_BOUND … #define RADEON_SURFACE5_INFO … #define RADEON_SURFACE5_LOWER_BOUND … #define RADEON_SURFACE5_UPPER_BOUND … #define RADEON_SURFACE6_INFO … #define RADEON_SURFACE6_LOWER_BOUND … #define RADEON_SURFACE6_UPPER_BOUND … #define RADEON_SURFACE7_INFO … #define RADEON_SURFACE7_LOWER_BOUND … #define RADEON_SURFACE7_UPPER_BOUND … #define RADEON_SW_SEMAPHORE … #define RADEON_TEST_DEBUG_CNTL … #define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN … #define RADEON_TEST_DEBUG_MUX … #define RADEON_TEST_DEBUG_OUT … #define RADEON_TMDS_PLL_CNTL … #define RADEON_TMDS_TRANSMITTER_CNTL … #define RADEON_TMDS_TRANSMITTER_PLLEN … #define RADEON_TMDS_TRANSMITTER_PLLRST … #define RADEON_TRAIL_BRES_DEC … #define RADEON_TRAIL_BRES_ERR … #define RADEON_TRAIL_BRES_INC … #define RADEON_TRAIL_X … #define RADEON_TRAIL_X_SUB … #define RADEON_VCLK_ECP_CNTL … #define RADEON_VCLK_SRC_SEL_MASK … #define RADEON_VCLK_SRC_SEL_CPUCLK … #define RADEON_VCLK_SRC_SEL_PSCANCLK … #define RADEON_VCLK_SRC_SEL_BYTECLK … #define RADEON_VCLK_SRC_SEL_PPLLCLK … #define RADEON_PIXCLK_ALWAYS_ONb … #define RADEON_PIXCLK_DAC_ALWAYS_ONb … #define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF … #define RADEON_VENDOR_ID … #define RADEON_VGA_DDA_CONFIG … #define RADEON_VGA_DDA_ON_OFF … #define RADEON_VID_BUFFER_CONTROL … #define RADEON_VIDEOMUX_CNTL … /* VIP bus */ #define RADEON_VIPH_CH0_DATA … #define RADEON_VIPH_CH1_DATA … #define RADEON_VIPH_CH2_DATA … #define RADEON_VIPH_CH3_DATA … #define RADEON_VIPH_CH0_ADDR … #define RADEON_VIPH_CH1_ADDR … #define RADEON_VIPH_CH2_ADDR … #define RADEON_VIPH_CH3_ADDR … #define RADEON_VIPH_CH0_SBCNT … #define RADEON_VIPH_CH1_SBCNT … #define RADEON_VIPH_CH2_SBCNT … #define RADEON_VIPH_CH3_SBCNT … #define RADEON_VIPH_CH0_ABCNT … #define RADEON_VIPH_CH1_ABCNT … #define RADEON_VIPH_CH2_ABCNT … #define RADEON_VIPH_CH3_ABCNT … #define RADEON_VIPH_CONTROL … #define RADEON_VIP_BUSY … #define RADEON_VIP_IDLE … #define RADEON_VIP_RESET … #define RADEON_VIPH_EN … #define RADEON_VIPH_DV_LAT … #define RADEON_VIPH_BM_CHUNK … #define RADEON_VIPH_DV_INT … #define RADEON_VIPH_TIMEOUT_STAT … #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT … #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK … #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS … #define RADEON_VIPH_REG_DATA … #define RADEON_VIPH_REG_ADDR … #define RADEON_WAIT_UNTIL … #define RADEON_WAIT_CRTC_PFLIP … #define RADEON_WAIT_RE_CRTC_VLINE … #define RADEON_WAIT_FE_CRTC_VLINE … #define RADEON_WAIT_CRTC_VLINE … #define RADEON_WAIT_DMA_VID_IDLE … #define RADEON_WAIT_DMA_GUI_IDLE … #define RADEON_WAIT_CMDFIFO … #define RADEON_WAIT_OV0_FLIP … #define RADEON_WAIT_AGP_FLUSH … #define RADEON_WAIT_2D_IDLE … #define RADEON_WAIT_3D_IDLE … #define RADEON_WAIT_2D_IDLECLEAN … #define RADEON_WAIT_3D_IDLECLEAN … #define RADEON_WAIT_HOST_IDLECLEAN … #define RADEON_CMDFIFO_ENTRIES_SHIFT … #define RADEON_CMDFIFO_ENTRIES_MASK … #define RADEON_WAIT_VAP_IDLE … #define RADEON_WAIT_BOTH_CRTC_PFLIP … #define RADEON_ENG_DISPLAY_SELECT_CRTC0 … #define RADEON_ENG_DISPLAY_SELECT_CRTC1 … #define RADEON_X_MPLL_REF_FB_DIV … #define RADEON_XCLK_CNTL … #define RADEON_XDLL_CNTL … #define RADEON_XPLL_CNTL … /* Registers for 3D/TCL */ #define RADEON_PP_BORDER_COLOR_0 … #define RADEON_PP_BORDER_COLOR_1 … #define RADEON_PP_BORDER_COLOR_2 … #define RADEON_PP_CNTL … #define RADEON_STIPPLE_ENABLE … #define RADEON_SCISSOR_ENABLE … #define RADEON_PATTERN_ENABLE … #define RADEON_SHADOW_ENABLE … #define RADEON_TEX_ENABLE_MASK … #define RADEON_TEX_0_ENABLE … #define RADEON_TEX_1_ENABLE … #define RADEON_TEX_2_ENABLE … #define RADEON_TEX_3_ENABLE … #define RADEON_TEX_BLEND_ENABLE_MASK … #define RADEON_TEX_BLEND_0_ENABLE … #define RADEON_TEX_BLEND_1_ENABLE … #define RADEON_TEX_BLEND_2_ENABLE … #define RADEON_TEX_BLEND_3_ENABLE … #define RADEON_PLANAR_YUV_ENABLE … #define RADEON_SPECULAR_ENABLE … #define RADEON_FOG_ENABLE … #define RADEON_ALPHA_TEST_ENABLE … #define RADEON_ANTI_ALIAS_NONE … #define RADEON_ANTI_ALIAS_LINE … #define RADEON_ANTI_ALIAS_POLY … #define RADEON_ANTI_ALIAS_LINE_POLY … #define RADEON_BUMP_MAP_ENABLE … #define RADEON_BUMPED_MAP_T0 … #define RADEON_BUMPED_MAP_T1 … #define RADEON_BUMPED_MAP_T2 … #define RADEON_TEX_3D_ENABLE_0 … #define RADEON_TEX_3D_ENABLE_1 … #define RADEON_MC_ENABLE … #define RADEON_PP_FOG_COLOR … #define RADEON_FOG_COLOR_MASK … #define RADEON_FOG_VERTEX … #define RADEON_FOG_TABLE … #define RADEON_FOG_USE_DEPTH … #define RADEON_FOG_USE_DIFFUSE_ALPHA … #define RADEON_FOG_USE_SPEC_ALPHA … #define RADEON_PP_LUM_MATRIX … #define RADEON_PP_MISC … #define RADEON_REF_ALPHA_MASK … #define RADEON_ALPHA_TEST_FAIL … #define RADEON_ALPHA_TEST_LESS … #define RADEON_ALPHA_TEST_LEQUAL … #define RADEON_ALPHA_TEST_EQUAL … #define RADEON_ALPHA_TEST_GEQUAL … #define RADEON_ALPHA_TEST_GREATER … #define RADEON_ALPHA_TEST_NEQUAL … #define RADEON_ALPHA_TEST_PASS … #define RADEON_ALPHA_TEST_OP_MASK … #define RADEON_CHROMA_FUNC_FAIL … #define RADEON_CHROMA_FUNC_PASS … #define RADEON_CHROMA_FUNC_NEQUAL … #define RADEON_CHROMA_FUNC_EQUAL … #define RADEON_CHROMA_KEY_NEAREST … #define RADEON_CHROMA_KEY_ZERO … #define RADEON_SHADOW_ID_AUTO_INC … #define RADEON_SHADOW_FUNC_EQUAL … #define RADEON_SHADOW_FUNC_NEQUAL … #define RADEON_SHADOW_PASS_1 … #define RADEON_SHADOW_PASS_2 … #define RADEON_RIGHT_HAND_CUBE_D3D … #define RADEON_RIGHT_HAND_CUBE_OGL … #define RADEON_PP_ROT_MATRIX_0 … #define RADEON_PP_ROT_MATRIX_1 … #define RADEON_PP_TXFILTER_0 … #define RADEON_PP_TXFILTER_1 … #define RADEON_PP_TXFILTER_2 … #define RADEON_MAG_FILTER_NEAREST … #define RADEON_MAG_FILTER_LINEAR … #define RADEON_MAG_FILTER_MASK … #define RADEON_MIN_FILTER_NEAREST … #define RADEON_MIN_FILTER_LINEAR … #define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST … #define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR … #define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST … #define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR … #define RADEON_MIN_FILTER_ANISO_NEAREST … #define RADEON_MIN_FILTER_ANISO_LINEAR … #define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST … #define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR … #define RADEON_MIN_FILTER_MASK … #define RADEON_MAX_ANISO_1_TO_1 … #define RADEON_MAX_ANISO_2_TO_1 … #define RADEON_MAX_ANISO_4_TO_1 … #define RADEON_MAX_ANISO_8_TO_1 … #define RADEON_MAX_ANISO_16_TO_1 … #define RADEON_MAX_ANISO_MASK … #define RADEON_LOD_BIAS_MASK … #define RADEON_LOD_BIAS_SHIFT … #define RADEON_MAX_MIP_LEVEL_MASK … #define RADEON_MAX_MIP_LEVEL_SHIFT … #define RADEON_YUV_TO_RGB … #define RADEON_YUV_TEMPERATURE_COOL … #define RADEON_YUV_TEMPERATURE_HOT … #define RADEON_YUV_TEMPERATURE_MASK … #define RADEON_WRAPEN_S … #define RADEON_CLAMP_S_WRAP … #define RADEON_CLAMP_S_MIRROR … #define RADEON_CLAMP_S_CLAMP_LAST … #define RADEON_CLAMP_S_MIRROR_CLAMP_LAST … #define RADEON_CLAMP_S_CLAMP_BORDER … #define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER … #define RADEON_CLAMP_S_CLAMP_GL … #define RADEON_CLAMP_S_MIRROR_CLAMP_GL … #define RADEON_CLAMP_S_MASK … #define RADEON_WRAPEN_T … #define RADEON_CLAMP_T_WRAP … #define RADEON_CLAMP_T_MIRROR … #define RADEON_CLAMP_T_CLAMP_LAST … #define RADEON_CLAMP_T_MIRROR_CLAMP_LAST … #define RADEON_CLAMP_T_CLAMP_BORDER … #define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER … #define RADEON_CLAMP_T_CLAMP_GL … #define RADEON_CLAMP_T_MIRROR_CLAMP_GL … #define RADEON_CLAMP_T_MASK … #define RADEON_BORDER_MODE_OGL … #define RADEON_BORDER_MODE_D3D … #define RADEON_PP_TXFORMAT_0 … #define RADEON_PP_TXFORMAT_1 … #define RADEON_PP_TXFORMAT_2 … #define RADEON_TXFORMAT_I8 … #define RADEON_TXFORMAT_AI88 … #define RADEON_TXFORMAT_RGB332 … #define RADEON_TXFORMAT_ARGB1555 … #define RADEON_TXFORMAT_RGB565 … #define RADEON_TXFORMAT_ARGB4444 … #define RADEON_TXFORMAT_ARGB8888 … #define RADEON_TXFORMAT_RGBA8888 … #define RADEON_TXFORMAT_Y8 … #define RADEON_TXFORMAT_VYUY422 … #define RADEON_TXFORMAT_YVYU422 … #define RADEON_TXFORMAT_DXT1 … #define RADEON_TXFORMAT_DXT23 … #define RADEON_TXFORMAT_DXT45 … #define RADEON_TXFORMAT_SHADOW16 … #define RADEON_TXFORMAT_SHADOW32 … #define RADEON_TXFORMAT_DUDV88 … #define RADEON_TXFORMAT_LDUDV655 … #define RADEON_TXFORMAT_LDUDUV8888 … #define RADEON_TXFORMAT_FORMAT_MASK … #define RADEON_TXFORMAT_FORMAT_SHIFT … #define RADEON_TXFORMAT_APPLE_YUV_MODE … #define RADEON_TXFORMAT_ALPHA_IN_MAP … #define RADEON_TXFORMAT_NON_POWER2 … #define RADEON_TXFORMAT_WIDTH_MASK … #define RADEON_TXFORMAT_WIDTH_SHIFT … #define RADEON_TXFORMAT_HEIGHT_MASK … #define RADEON_TXFORMAT_HEIGHT_SHIFT … #define RADEON_TXFORMAT_F5_WIDTH_MASK … #define RADEON_TXFORMAT_F5_WIDTH_SHIFT … #define RADEON_TXFORMAT_F5_HEIGHT_MASK … #define RADEON_TXFORMAT_F5_HEIGHT_SHIFT … #define RADEON_TXFORMAT_ST_ROUTE_STQ0 … #define RADEON_TXFORMAT_ST_ROUTE_MASK … #define RADEON_TXFORMAT_ST_ROUTE_STQ1 … #define RADEON_TXFORMAT_ST_ROUTE_STQ2 … #define RADEON_TXFORMAT_ENDIAN_NO_SWAP … #define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP … #define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP … #define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP … #define RADEON_TXFORMAT_ALPHA_MASK_ENABLE … #define RADEON_TXFORMAT_CHROMA_KEY_ENABLE … #define RADEON_TXFORMAT_CUBIC_MAP_ENABLE … #define RADEON_TXFORMAT_PERSPECTIVE_ENABLE … #define RADEON_PP_CUBIC_FACES_0 … #define RADEON_PP_CUBIC_FACES_1 … #define RADEON_PP_CUBIC_FACES_2 … #define RADEON_FACE_WIDTH_1_SHIFT … #define RADEON_FACE_HEIGHT_1_SHIFT … #define RADEON_FACE_WIDTH_1_MASK … #define RADEON_FACE_HEIGHT_1_MASK … #define RADEON_FACE_WIDTH_2_SHIFT … #define RADEON_FACE_HEIGHT_2_SHIFT … #define RADEON_FACE_WIDTH_2_MASK … #define RADEON_FACE_HEIGHT_2_MASK … #define RADEON_FACE_WIDTH_3_SHIFT … #define RADEON_FACE_HEIGHT_3_SHIFT … #define RADEON_FACE_WIDTH_3_MASK … #define RADEON_FACE_HEIGHT_3_MASK … #define RADEON_FACE_WIDTH_4_SHIFT … #define RADEON_FACE_HEIGHT_4_SHIFT … #define RADEON_FACE_WIDTH_4_MASK … #define RADEON_FACE_HEIGHT_4_MASK … #define RADEON_PP_TXOFFSET_0 … #define RADEON_PP_TXOFFSET_1 … #define RADEON_PP_TXOFFSET_2 … #define RADEON_TXO_ENDIAN_NO_SWAP … #define RADEON_TXO_ENDIAN_BYTE_SWAP … #define RADEON_TXO_ENDIAN_WORD_SWAP … #define RADEON_TXO_ENDIAN_HALFDW_SWAP … #define RADEON_TXO_MACRO_LINEAR … #define RADEON_TXO_MACRO_TILE … #define RADEON_TXO_MICRO_LINEAR … #define RADEON_TXO_MICRO_TILE_X2 … #define RADEON_TXO_MICRO_TILE_OPT … #define RADEON_TXO_OFFSET_MASK … #define RADEON_TXO_OFFSET_SHIFT … #define RADEON_PP_CUBIC_OFFSET_T0_0 … #define RADEON_PP_CUBIC_OFFSET_T0_1 … #define RADEON_PP_CUBIC_OFFSET_T0_2 … #define RADEON_PP_CUBIC_OFFSET_T0_3 … #define RADEON_PP_CUBIC_OFFSET_T0_4 … #define RADEON_PP_CUBIC_OFFSET_T1_0 … #define RADEON_PP_CUBIC_OFFSET_T1_1 … #define RADEON_PP_CUBIC_OFFSET_T1_2 … #define RADEON_PP_CUBIC_OFFSET_T1_3 … #define RADEON_PP_CUBIC_OFFSET_T1_4 … #define RADEON_PP_CUBIC_OFFSET_T2_0 … #define RADEON_PP_CUBIC_OFFSET_T2_1 … #define RADEON_PP_CUBIC_OFFSET_T2_2 … #define RADEON_PP_CUBIC_OFFSET_T2_3 … #define RADEON_PP_CUBIC_OFFSET_T2_4 … #define RADEON_PP_TEX_SIZE_0 … #define RADEON_PP_TEX_SIZE_1 … #define RADEON_PP_TEX_SIZE_2 … #define RADEON_TEX_USIZE_MASK … #define RADEON_TEX_USIZE_SHIFT … #define RADEON_TEX_VSIZE_MASK … #define RADEON_TEX_VSIZE_SHIFT … #define RADEON_SIGNED_RGB_MASK … #define RADEON_SIGNED_RGB_SHIFT … #define RADEON_SIGNED_ALPHA_MASK … #define RADEON_SIGNED_ALPHA_SHIFT … #define RADEON_PP_TEX_PITCH_0 … #define RADEON_PP_TEX_PITCH_1 … #define RADEON_PP_TEX_PITCH_2 … /* note: bits 13-5: 32 byte aligned stride of texture map */ #define RADEON_PP_TXCBLEND_0 … #define RADEON_PP_TXCBLEND_1 … #define RADEON_PP_TXCBLEND_2 … #define RADEON_COLOR_ARG_A_SHIFT … #define RADEON_COLOR_ARG_A_MASK … #define RADEON_COLOR_ARG_A_ZERO … #define RADEON_COLOR_ARG_A_CURRENT_COLOR … #define RADEON_COLOR_ARG_A_CURRENT_ALPHA … #define RADEON_COLOR_ARG_A_DIFFUSE_COLOR … #define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA … #define RADEON_COLOR_ARG_A_SPECULAR_COLOR … #define RADEON_COLOR_ARG_A_SPECULAR_ALPHA … #define RADEON_COLOR_ARG_A_TFACTOR_COLOR … #define RADEON_COLOR_ARG_A_TFACTOR_ALPHA … #define RADEON_COLOR_ARG_A_T0_COLOR … #define RADEON_COLOR_ARG_A_T0_ALPHA … #define RADEON_COLOR_ARG_A_T1_COLOR … #define RADEON_COLOR_ARG_A_T1_ALPHA … #define RADEON_COLOR_ARG_A_T2_COLOR … #define RADEON_COLOR_ARG_A_T2_ALPHA … #define RADEON_COLOR_ARG_A_T3_COLOR … #define RADEON_COLOR_ARG_A_T3_ALPHA … #define RADEON_COLOR_ARG_B_SHIFT … #define RADEON_COLOR_ARG_B_MASK … #define RADEON_COLOR_ARG_B_ZERO … #define RADEON_COLOR_ARG_B_CURRENT_COLOR … #define RADEON_COLOR_ARG_B_CURRENT_ALPHA … #define RADEON_COLOR_ARG_B_DIFFUSE_COLOR … #define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA … #define RADEON_COLOR_ARG_B_SPECULAR_COLOR … #define RADEON_COLOR_ARG_B_SPECULAR_ALPHA … #define RADEON_COLOR_ARG_B_TFACTOR_COLOR … #define RADEON_COLOR_ARG_B_TFACTOR_ALPHA … #define RADEON_COLOR_ARG_B_T0_COLOR … #define RADEON_COLOR_ARG_B_T0_ALPHA … #define RADEON_COLOR_ARG_B_T1_COLOR … #define RADEON_COLOR_ARG_B_T1_ALPHA … #define RADEON_COLOR_ARG_B_T2_COLOR … #define RADEON_COLOR_ARG_B_T2_ALPHA … #define RADEON_COLOR_ARG_B_T3_COLOR … #define RADEON_COLOR_ARG_B_T3_ALPHA … #define RADEON_COLOR_ARG_C_SHIFT … #define RADEON_COLOR_ARG_C_MASK … #define RADEON_COLOR_ARG_C_ZERO … #define RADEON_COLOR_ARG_C_CURRENT_COLOR … #define RADEON_COLOR_ARG_C_CURRENT_ALPHA … #define RADEON_COLOR_ARG_C_DIFFUSE_COLOR … #define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA … #define RADEON_COLOR_ARG_C_SPECULAR_COLOR … #define RADEON_COLOR_ARG_C_SPECULAR_ALPHA … #define RADEON_COLOR_ARG_C_TFACTOR_COLOR … #define RADEON_COLOR_ARG_C_TFACTOR_ALPHA … #define RADEON_COLOR_ARG_C_T0_COLOR … #define RADEON_COLOR_ARG_C_T0_ALPHA … #define RADEON_COLOR_ARG_C_T1_COLOR … #define RADEON_COLOR_ARG_C_T1_ALPHA … #define RADEON_COLOR_ARG_C_T2_COLOR … #define RADEON_COLOR_ARG_C_T2_ALPHA … #define RADEON_COLOR_ARG_C_T3_COLOR … #define RADEON_COLOR_ARG_C_T3_ALPHA … #define RADEON_COMP_ARG_A … #define RADEON_COMP_ARG_A_SHIFT … #define RADEON_COMP_ARG_B … #define RADEON_COMP_ARG_B_SHIFT … #define RADEON_COMP_ARG_C … #define RADEON_COMP_ARG_C_SHIFT … #define RADEON_BLEND_CTL_MASK … #define RADEON_BLEND_CTL_ADD … #define RADEON_BLEND_CTL_SUBTRACT … #define RADEON_BLEND_CTL_ADDSIGNED … #define RADEON_BLEND_CTL_BLEND … #define RADEON_BLEND_CTL_DOT3 … #define RADEON_SCALE_SHIFT … #define RADEON_SCALE_MASK … #define RADEON_SCALE_1X … #define RADEON_SCALE_2X … #define RADEON_SCALE_4X … #define RADEON_CLAMP_TX … #define RADEON_T0_EQ_TCUR … #define RADEON_T1_EQ_TCUR … #define RADEON_T2_EQ_TCUR … #define RADEON_T3_EQ_TCUR … #define RADEON_COLOR_ARG_MASK … #define RADEON_COMP_ARG_SHIFT … #define RADEON_PP_TXABLEND_0 … #define RADEON_PP_TXABLEND_1 … #define RADEON_PP_TXABLEND_2 … #define RADEON_ALPHA_ARG_A_SHIFT … #define RADEON_ALPHA_ARG_A_MASK … #define RADEON_ALPHA_ARG_A_ZERO … #define RADEON_ALPHA_ARG_A_CURRENT_ALPHA … #define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA … #define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA … #define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA … #define RADEON_ALPHA_ARG_A_T0_ALPHA … #define RADEON_ALPHA_ARG_A_T1_ALPHA … #define RADEON_ALPHA_ARG_A_T2_ALPHA … #define RADEON_ALPHA_ARG_A_T3_ALPHA … #define RADEON_ALPHA_ARG_B_SHIFT … #define RADEON_ALPHA_ARG_B_MASK … #define RADEON_ALPHA_ARG_B_ZERO … #define RADEON_ALPHA_ARG_B_CURRENT_ALPHA … #define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA … #define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA … #define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA … #define RADEON_ALPHA_ARG_B_T0_ALPHA … #define RADEON_ALPHA_ARG_B_T1_ALPHA … #define RADEON_ALPHA_ARG_B_T2_ALPHA … #define RADEON_ALPHA_ARG_B_T3_ALPHA … #define RADEON_ALPHA_ARG_C_SHIFT … #define RADEON_ALPHA_ARG_C_MASK … #define RADEON_ALPHA_ARG_C_ZERO … #define RADEON_ALPHA_ARG_C_CURRENT_ALPHA … #define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA … #define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA … #define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA … #define RADEON_ALPHA_ARG_C_T0_ALPHA … #define RADEON_ALPHA_ARG_C_T1_ALPHA … #define RADEON_ALPHA_ARG_C_T2_ALPHA … #define RADEON_ALPHA_ARG_C_T3_ALPHA … #define RADEON_DOT_ALPHA_DONT_REPLICATE … #define RADEON_ALPHA_ARG_MASK … #define RADEON_PP_TFACTOR_0 … #define RADEON_PP_TFACTOR_1 … #define RADEON_PP_TFACTOR_2 … #define RADEON_RB3D_BLENDCNTL … #define RADEON_COMB_FCN_MASK … #define RADEON_COMB_FCN_ADD_CLAMP … #define RADEON_COMB_FCN_ADD_NOCLAMP … #define RADEON_COMB_FCN_SUB_CLAMP … #define RADEON_COMB_FCN_SUB_NOCLAMP … #define RADEON_SRC_BLEND_GL_ZERO … #define RADEON_SRC_BLEND_GL_ONE … #define RADEON_SRC_BLEND_GL_SRC_COLOR … #define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR … #define RADEON_SRC_BLEND_GL_DST_COLOR … #define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR … #define RADEON_SRC_BLEND_GL_SRC_ALPHA … #define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA … #define RADEON_SRC_BLEND_GL_DST_ALPHA … #define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA … #define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE … #define RADEON_SRC_BLEND_MASK … #define RADEON_DST_BLEND_GL_ZERO … #define RADEON_DST_BLEND_GL_ONE … #define RADEON_DST_BLEND_GL_SRC_COLOR … #define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR … #define RADEON_DST_BLEND_GL_DST_COLOR … #define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR … #define RADEON_DST_BLEND_GL_SRC_ALPHA … #define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA … #define RADEON_DST_BLEND_GL_DST_ALPHA … #define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA … #define RADEON_DST_BLEND_MASK … #define RADEON_RB3D_CNTL … #define RADEON_ALPHA_BLEND_ENABLE … #define RADEON_PLANE_MASK_ENABLE … #define RADEON_DITHER_ENABLE … #define RADEON_ROUND_ENABLE … #define RADEON_SCALE_DITHER_ENABLE … #define RADEON_DITHER_INIT … #define RADEON_ROP_ENABLE … #define RADEON_STENCIL_ENABLE … #define RADEON_Z_ENABLE … #define RADEON_DEPTHXY_OFFSET_ENABLE … #define RADEON_RB3D_COLOR_FORMAT_SHIFT … #define RADEON_COLOR_FORMAT_ARGB1555 … #define RADEON_COLOR_FORMAT_RGB565 … #define RADEON_COLOR_FORMAT_ARGB8888 … #define RADEON_COLOR_FORMAT_RGB332 … #define RADEON_COLOR_FORMAT_Y8 … #define RADEON_COLOR_FORMAT_RGB8 … #define RADEON_COLOR_FORMAT_YUV422_VYUY … #define RADEON_COLOR_FORMAT_YUV422_YVYU … #define RADEON_COLOR_FORMAT_aYUV444 … #define RADEON_COLOR_FORMAT_ARGB4444 … #define RADEON_CLRCMP_FLIP_ENABLE … #define RADEON_RB3D_COLOROFFSET … #define RADEON_COLOROFFSET_MASK … #define RADEON_RB3D_COLORPITCH … #define RADEON_COLORPITCH_MASK … #define RADEON_COLOR_TILE_ENABLE … #define RADEON_COLOR_MICROTILE_ENABLE … #define RADEON_COLOR_ENDIAN_NO_SWAP … #define RADEON_COLOR_ENDIAN_WORD_SWAP … #define RADEON_COLOR_ENDIAN_DWORD_SWAP … #define RADEON_RB3D_DEPTHOFFSET … #define RADEON_RB3D_DEPTHPITCH … #define RADEON_DEPTHPITCH_MASK … #define RADEON_DEPTH_ENDIAN_NO_SWAP … #define RADEON_DEPTH_ENDIAN_WORD_SWAP … #define RADEON_DEPTH_ENDIAN_DWORD_SWAP … #define RADEON_RB3D_PLANEMASK … #define RADEON_RB3D_ROPCNTL … #define RADEON_ROP_MASK … #define RADEON_ROP_CLEAR … #define RADEON_ROP_NOR … #define RADEON_ROP_AND_INVERTED … #define RADEON_ROP_COPY_INVERTED … #define RADEON_ROP_AND_REVERSE … #define RADEON_ROP_INVERT … #define RADEON_ROP_XOR … #define RADEON_ROP_NAND … #define RADEON_ROP_AND … #define RADEON_ROP_EQUIV … #define RADEON_ROP_NOOP … #define RADEON_ROP_OR_INVERTED … #define RADEON_ROP_COPY … #define RADEON_ROP_OR_REVERSE … #define RADEON_ROP_OR … #define RADEON_ROP_SET … #define RADEON_RB3D_STENCILREFMASK … #define RADEON_STENCIL_REF_SHIFT … #define RADEON_STENCIL_REF_MASK … #define RADEON_STENCIL_MASK_SHIFT … #define RADEON_STENCIL_VALUE_MASK … #define RADEON_STENCIL_WRITEMASK_SHIFT … #define RADEON_STENCIL_WRITE_MASK … #define RADEON_RB3D_ZSTENCILCNTL … #define RADEON_DEPTH_FORMAT_MASK … #define RADEON_DEPTH_FORMAT_16BIT_INT_Z … #define RADEON_DEPTH_FORMAT_24BIT_INT_Z … #define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z … #define RADEON_DEPTH_FORMAT_32BIT_INT_Z … #define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z … #define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W … #define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W … #define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W … #define RADEON_Z_TEST_NEVER … #define RADEON_Z_TEST_LESS … #define RADEON_Z_TEST_LEQUAL … #define RADEON_Z_TEST_EQUAL … #define RADEON_Z_TEST_GEQUAL … #define RADEON_Z_TEST_GREATER … #define RADEON_Z_TEST_NEQUAL … #define RADEON_Z_TEST_ALWAYS … #define RADEON_Z_TEST_MASK … #define RADEON_STENCIL_TEST_NEVER … #define RADEON_STENCIL_TEST_LESS … #define RADEON_STENCIL_TEST_LEQUAL … #define RADEON_STENCIL_TEST_EQUAL … #define RADEON_STENCIL_TEST_GEQUAL … #define RADEON_STENCIL_TEST_GREATER … #define RADEON_STENCIL_TEST_NEQUAL … #define RADEON_STENCIL_TEST_ALWAYS … #define RADEON_STENCIL_TEST_MASK … #define RADEON_STENCIL_FAIL_KEEP … #define RADEON_STENCIL_FAIL_ZERO … #define RADEON_STENCIL_FAIL_REPLACE … #define RADEON_STENCIL_FAIL_INC … #define RADEON_STENCIL_FAIL_DEC … #define RADEON_STENCIL_FAIL_INVERT … #define RADEON_STENCIL_FAIL_MASK … #define RADEON_STENCIL_ZPASS_KEEP … #define RADEON_STENCIL_ZPASS_ZERO … #define RADEON_STENCIL_ZPASS_REPLACE … #define RADEON_STENCIL_ZPASS_INC … #define RADEON_STENCIL_ZPASS_DEC … #define RADEON_STENCIL_ZPASS_INVERT … #define RADEON_STENCIL_ZPASS_MASK … #define RADEON_STENCIL_ZFAIL_KEEP … #define RADEON_STENCIL_ZFAIL_ZERO … #define RADEON_STENCIL_ZFAIL_REPLACE … #define RADEON_STENCIL_ZFAIL_INC … #define RADEON_STENCIL_ZFAIL_DEC … #define RADEON_STENCIL_ZFAIL_INVERT … #define RADEON_STENCIL_ZFAIL_MASK … #define RADEON_Z_COMPRESSION_ENABLE … #define RADEON_FORCE_Z_DIRTY … #define RADEON_Z_WRITE_ENABLE … #define RADEON_RE_LINE_PATTERN … #define RADEON_LINE_PATTERN_MASK … #define RADEON_LINE_REPEAT_COUNT_SHIFT … #define RADEON_LINE_PATTERN_START_SHIFT … #define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER … #define RADEON_LINE_PATTERN_BIG_BIT_ORDER … #define RADEON_LINE_PATTERN_AUTO_RESET … #define RADEON_RE_LINE_STATE … #define RADEON_LINE_CURRENT_PTR_SHIFT … #define RADEON_LINE_CURRENT_COUNT_SHIFT … #define RADEON_RE_MISC … #define RADEON_STIPPLE_COORD_MASK … #define RADEON_STIPPLE_X_OFFSET_SHIFT … #define RADEON_STIPPLE_X_OFFSET_MASK … #define RADEON_STIPPLE_Y_OFFSET_SHIFT … #define RADEON_STIPPLE_Y_OFFSET_MASK … #define RADEON_STIPPLE_LITTLE_BIT_ORDER … #define RADEON_STIPPLE_BIG_BIT_ORDER … #define RADEON_RE_SOLID_COLOR … #define RADEON_RE_TOP_LEFT … #define RADEON_RE_LEFT_SHIFT … #define RADEON_RE_TOP_SHIFT … #define RADEON_RE_WIDTH_HEIGHT … #define RADEON_RE_WIDTH_SHIFT … #define RADEON_RE_HEIGHT_SHIFT … #define RADEON_RB3D_ZPASS_DATA … #define RADEON_RB3D_ZPASS_ADDR … #define RADEON_SE_CNTL … #define RADEON_FFACE_CULL_CW … #define RADEON_FFACE_CULL_CCW … #define RADEON_FFACE_CULL_DIR_MASK … #define RADEON_BFACE_CULL … #define RADEON_BFACE_SOLID … #define RADEON_FFACE_CULL … #define RADEON_FFACE_SOLID … #define RADEON_FFACE_CULL_MASK … #define RADEON_BADVTX_CULL_DISABLE … #define RADEON_FLAT_SHADE_VTX_0 … #define RADEON_FLAT_SHADE_VTX_1 … #define RADEON_FLAT_SHADE_VTX_2 … #define RADEON_FLAT_SHADE_VTX_LAST … #define RADEON_DIFFUSE_SHADE_SOLID … #define RADEON_DIFFUSE_SHADE_FLAT … #define RADEON_DIFFUSE_SHADE_GOURAUD … #define RADEON_DIFFUSE_SHADE_MASK … #define RADEON_ALPHA_SHADE_SOLID … #define RADEON_ALPHA_SHADE_FLAT … #define RADEON_ALPHA_SHADE_GOURAUD … #define RADEON_ALPHA_SHADE_MASK … #define RADEON_SPECULAR_SHADE_SOLID … #define RADEON_SPECULAR_SHADE_FLAT … #define RADEON_SPECULAR_SHADE_GOURAUD … #define RADEON_SPECULAR_SHADE_MASK … #define RADEON_FOG_SHADE_SOLID … #define RADEON_FOG_SHADE_FLAT … #define RADEON_FOG_SHADE_GOURAUD … #define RADEON_FOG_SHADE_MASK … #define RADEON_ZBIAS_ENABLE_POINT … #define RADEON_ZBIAS_ENABLE_LINE … #define RADEON_ZBIAS_ENABLE_TRI … #define RADEON_WIDELINE_ENABLE … #define RADEON_VPORT_XY_XFORM_ENABLE … #define RADEON_VPORT_Z_XFORM_ENABLE … #define RADEON_VTX_PIX_CENTER_D3D … #define RADEON_VTX_PIX_CENTER_OGL … #define RADEON_ROUND_MODE_TRUNC … #define RADEON_ROUND_MODE_ROUND … #define RADEON_ROUND_MODE_ROUND_EVEN … #define RADEON_ROUND_MODE_ROUND_ODD … #define RADEON_ROUND_PREC_16TH_PIX … #define RADEON_ROUND_PREC_8TH_PIX … #define RADEON_ROUND_PREC_4TH_PIX … #define RADEON_ROUND_PREC_HALF_PIX … #define R200_RE_CNTL … #define R200_STIPPLE_ENABLE … #define R200_SCISSOR_ENABLE … #define R200_PATTERN_ENABLE … #define R200_PERSPECTIVE_ENABLE … #define R200_POINT_SMOOTH … #define R200_VTX_STQ0_D3D … #define R200_VTX_STQ1_D3D … #define R200_VTX_STQ2_D3D … #define R200_VTX_STQ3_D3D … #define R200_VTX_STQ4_D3D … #define R200_VTX_STQ5_D3D … #define RADEON_SE_CNTL_STATUS … #define RADEON_VC_NO_SWAP … #define RADEON_VC_16BIT_SWAP … #define RADEON_VC_32BIT_SWAP … #define RADEON_VC_HALF_DWORD_SWAP … #define RADEON_TCL_BYPASS … #define RADEON_SE_COORD_FMT … #define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 … #define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 … #define RADEON_VTX_ST0_NONPARAMETRIC … #define RADEON_VTX_ST1_NONPARAMETRIC … #define RADEON_VTX_ST2_NONPARAMETRIC … #define RADEON_VTX_ST3_NONPARAMETRIC … #define RADEON_VTX_W0_NORMALIZE … #define RADEON_VTX_W0_IS_NOT_1_OVER_W0 … #define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 … #define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 … #define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 … #define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 … #define RADEON_TEX1_W_ROUTING_USE_W0 … #define RADEON_TEX1_W_ROUTING_USE_Q1 … #define RADEON_SE_LINE_WIDTH … #define RADEON_SE_TCL_LIGHT_MODEL_CTL … #define RADEON_LIGHTING_ENABLE … #define RADEON_LIGHT_IN_MODELSPACE … #define RADEON_LOCAL_VIEWER … #define RADEON_NORMALIZE_NORMALS … #define RADEON_RESCALE_NORMALS … #define RADEON_SPECULAR_LIGHTS … #define RADEON_DIFFUSE_SPECULAR_COMBINE … #define RADEON_LIGHT_ALPHA … #define RADEON_LOCAL_LIGHT_VEC_GL … #define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY … #define RADEON_LM_SOURCE_STATE_PREMULT … #define RADEON_LM_SOURCE_STATE_MULT … #define RADEON_LM_SOURCE_VERTEX_DIFFUSE … #define RADEON_LM_SOURCE_VERTEX_SPECULAR … #define RADEON_EMISSIVE_SOURCE_SHIFT … #define RADEON_AMBIENT_SOURCE_SHIFT … #define RADEON_DIFFUSE_SOURCE_SHIFT … #define RADEON_SPECULAR_SOURCE_SHIFT … #define RADEON_SE_TCL_MATERIAL_AMBIENT_RED … #define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN … #define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE … #define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA … #define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED … #define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN … #define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE … #define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA … #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED … #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN … #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE … #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA … #define RADEON_SE_TCL_MATERIAL_SPECULAR_RED … #define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN … #define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE … #define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA … #define RADEON_SE_TCL_MATRIX_SELECT_0 … #define RADEON_MODELVIEW_0_SHIFT … #define RADEON_MODELVIEW_1_SHIFT … #define RADEON_MODELVIEW_2_SHIFT … #define RADEON_MODELVIEW_3_SHIFT … #define RADEON_IT_MODELVIEW_0_SHIFT … #define RADEON_IT_MODELVIEW_1_SHIFT … #define RADEON_IT_MODELVIEW_2_SHIFT … #define RADEON_IT_MODELVIEW_3_SHIFT … #define RADEON_SE_TCL_MATRIX_SELECT_1 … #define RADEON_MODELPROJECT_0_SHIFT … #define RADEON_MODELPROJECT_1_SHIFT … #define RADEON_MODELPROJECT_2_SHIFT … #define RADEON_MODELPROJECT_3_SHIFT … #define RADEON_TEXMAT_0_SHIFT … #define RADEON_TEXMAT_1_SHIFT … #define RADEON_TEXMAT_2_SHIFT … #define RADEON_TEXMAT_3_SHIFT … #define RADEON_SE_TCL_OUTPUT_VTX_FMT … #define RADEON_TCL_VTX_W0 … #define RADEON_TCL_VTX_FP_DIFFUSE … #define RADEON_TCL_VTX_FP_ALPHA … #define RADEON_TCL_VTX_PK_DIFFUSE … #define RADEON_TCL_VTX_FP_SPEC … #define RADEON_TCL_VTX_FP_FOG … #define RADEON_TCL_VTX_PK_SPEC … #define RADEON_TCL_VTX_ST0 … #define RADEON_TCL_VTX_ST1 … #define RADEON_TCL_VTX_Q1 … #define RADEON_TCL_VTX_ST2 … #define RADEON_TCL_VTX_Q2 … #define RADEON_TCL_VTX_ST3 … #define RADEON_TCL_VTX_Q3 … #define RADEON_TCL_VTX_Q0 … #define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT … #define RADEON_TCL_VTX_NORM0 … #define RADEON_TCL_VTX_XY1 … #define RADEON_TCL_VTX_Z1 … #define RADEON_TCL_VTX_W1 … #define RADEON_TCL_VTX_NORM1 … #define RADEON_TCL_VTX_Z0 … #define RADEON_SE_TCL_OUTPUT_VTX_SEL … #define RADEON_TCL_COMPUTE_XYZW … #define RADEON_TCL_COMPUTE_DIFFUSE … #define RADEON_TCL_COMPUTE_SPECULAR … #define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN … #define RADEON_TCL_FORCE_INORDER_PROC … #define RADEON_TCL_TEX_INPUT_TEX_0 … #define RADEON_TCL_TEX_INPUT_TEX_1 … #define RADEON_TCL_TEX_INPUT_TEX_2 … #define RADEON_TCL_TEX_INPUT_TEX_3 … #define RADEON_TCL_TEX_COMPUTED_TEX_0 … #define RADEON_TCL_TEX_COMPUTED_TEX_1 … #define RADEON_TCL_TEX_COMPUTED_TEX_2 … #define RADEON_TCL_TEX_COMPUTED_TEX_3 … #define RADEON_TCL_TEX_0_OUTPUT_SHIFT … #define RADEON_TCL_TEX_1_OUTPUT_SHIFT … #define RADEON_TCL_TEX_2_OUTPUT_SHIFT … #define RADEON_TCL_TEX_3_OUTPUT_SHIFT … #define RADEON_SE_TCL_PER_LIGHT_CTL_0 … #define RADEON_LIGHT_0_ENABLE … #define RADEON_LIGHT_0_ENABLE_AMBIENT … #define RADEON_LIGHT_0_ENABLE_SPECULAR … #define RADEON_LIGHT_0_IS_LOCAL … #define RADEON_LIGHT_0_IS_SPOT … #define RADEON_LIGHT_0_DUAL_CONE … #define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN … #define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN … #define RADEON_LIGHT_0_SHIFT … #define RADEON_LIGHT_1_ENABLE … #define RADEON_LIGHT_1_ENABLE_AMBIENT … #define RADEON_LIGHT_1_ENABLE_SPECULAR … #define RADEON_LIGHT_1_IS_LOCAL … #define RADEON_LIGHT_1_IS_SPOT … #define RADEON_LIGHT_1_DUAL_CONE … #define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN … #define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN … #define RADEON_LIGHT_1_SHIFT … #define RADEON_SE_TCL_PER_LIGHT_CTL_1 … #define RADEON_LIGHT_2_SHIFT … #define RADEON_LIGHT_3_SHIFT … #define RADEON_SE_TCL_PER_LIGHT_CTL_2 … #define RADEON_LIGHT_4_SHIFT … #define RADEON_LIGHT_5_SHIFT … #define RADEON_SE_TCL_PER_LIGHT_CTL_3 … #define RADEON_LIGHT_6_SHIFT … #define RADEON_LIGHT_7_SHIFT … #define RADEON_SE_TCL_SHININESS … #define RADEON_SE_TCL_TEXTURE_PROC_CTL … #define RADEON_TEXGEN_TEXMAT_0_ENABLE … #define RADEON_TEXGEN_TEXMAT_1_ENABLE … #define RADEON_TEXGEN_TEXMAT_2_ENABLE … #define RADEON_TEXGEN_TEXMAT_3_ENABLE … #define RADEON_TEXMAT_0_ENABLE … #define RADEON_TEXMAT_1_ENABLE … #define RADEON_TEXMAT_2_ENABLE … #define RADEON_TEXMAT_3_ENABLE … #define RADEON_TEXGEN_INPUT_MASK … #define RADEON_TEXGEN_INPUT_TEXCOORD_0 … #define RADEON_TEXGEN_INPUT_TEXCOORD_1 … #define RADEON_TEXGEN_INPUT_TEXCOORD_2 … #define RADEON_TEXGEN_INPUT_TEXCOORD_3 … #define RADEON_TEXGEN_INPUT_OBJ … #define RADEON_TEXGEN_INPUT_EYE … #define RADEON_TEXGEN_INPUT_EYE_NORMAL … #define RADEON_TEXGEN_INPUT_EYE_REFLECT … #define RADEON_TEXGEN_INPUT_EYE_NORMALIZED … #define RADEON_TEXGEN_0_INPUT_SHIFT … #define RADEON_TEXGEN_1_INPUT_SHIFT … #define RADEON_TEXGEN_2_INPUT_SHIFT … #define RADEON_TEXGEN_3_INPUT_SHIFT … #define RADEON_SE_TCL_UCP_VERT_BLEND_CTL … #define RADEON_UCP_IN_CLIP_SPACE … #define RADEON_UCP_IN_MODEL_SPACE … #define RADEON_UCP_ENABLE_0 … #define RADEON_UCP_ENABLE_1 … #define RADEON_UCP_ENABLE_2 … #define RADEON_UCP_ENABLE_3 … #define RADEON_UCP_ENABLE_4 … #define RADEON_UCP_ENABLE_5 … #define RADEON_TCL_FOG_MASK … #define RADEON_TCL_FOG_DISABLE … #define RADEON_TCL_FOG_EXP … #define RADEON_TCL_FOG_EXP2 … #define RADEON_TCL_FOG_LINEAR … #define RADEON_RNG_BASED_FOG … #define RADEON_LIGHT_TWOSIDE … #define RADEON_BLEND_OP_COUNT_MASK … #define RADEON_BLEND_OP_COUNT_SHIFT … #define RADEON_POSITION_BLEND_OP_ENABLE … #define RADEON_NORMAL_BLEND_OP_ENABLE … #define RADEON_VERTEX_BLEND_SRC_0_PRIMARY … #define RADEON_VERTEX_BLEND_SRC_0_SECONDARY … #define RADEON_VERTEX_BLEND_SRC_1_PRIMARY … #define RADEON_VERTEX_BLEND_SRC_1_SECONDARY … #define RADEON_VERTEX_BLEND_SRC_2_PRIMARY … #define RADEON_VERTEX_BLEND_SRC_2_SECONDARY … #define RADEON_VERTEX_BLEND_SRC_3_PRIMARY … #define RADEON_VERTEX_BLEND_SRC_3_SECONDARY … #define RADEON_VERTEX_BLEND_WGT_MINUS_ONE … #define RADEON_CULL_FRONT_IS_CW … #define RADEON_CULL_FRONT_IS_CCW … #define RADEON_CULL_FRONT … #define RADEON_CULL_BACK … #define RADEON_FORCE_W_TO_ONE … #define RADEON_SE_VPORT_XSCALE … #define RADEON_SE_VPORT_XOFFSET … #define RADEON_SE_VPORT_YSCALE … #define RADEON_SE_VPORT_YOFFSET … #define RADEON_SE_VPORT_ZSCALE … #define RADEON_SE_VPORT_ZOFFSET … #define RADEON_SE_ZBIAS_FACTOR … #define RADEON_SE_ZBIAS_CONSTANT … #define RADEON_SE_VTX_FMT … #define RADEON_SE_VTX_FMT_XY … #define RADEON_SE_VTX_FMT_W0 … #define RADEON_SE_VTX_FMT_FPCOLOR … #define RADEON_SE_VTX_FMT_FPALPHA … #define RADEON_SE_VTX_FMT_PKCOLOR … #define RADEON_SE_VTX_FMT_FPSPEC … #define RADEON_SE_VTX_FMT_FPFOG … #define RADEON_SE_VTX_FMT_PKSPEC … #define RADEON_SE_VTX_FMT_ST0 … #define RADEON_SE_VTX_FMT_ST1 … #define RADEON_SE_VTX_FMT_Q1 … #define RADEON_SE_VTX_FMT_ST2 … #define RADEON_SE_VTX_FMT_Q2 … #define RADEON_SE_VTX_FMT_ST3 … #define RADEON_SE_VTX_FMT_Q3 … #define RADEON_SE_VTX_FMT_Q0 … #define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK … #define RADEON_SE_VTX_FMT_N0 … #define RADEON_SE_VTX_FMT_XY1 … #define RADEON_SE_VTX_FMT_Z1 … #define RADEON_SE_VTX_FMT_W1 … #define RADEON_SE_VTX_FMT_N1 … #define RADEON_SE_VTX_FMT_Z … #define RADEON_SE_VF_CNTL … #define RADEON_VF_PRIM_TYPE_POINT_LIST … #define RADEON_VF_PRIM_TYPE_LINE_LIST … #define RADEON_VF_PRIM_TYPE_LINE_STRIP … #define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST … #define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN … #define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP … #define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG … #define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST … #define RADEON_VF_PRIM_TYPE_POINT_LIST_3 … #define RADEON_VF_PRIM_TYPE_LINE_LIST_3 … #define RADEON_VF_PRIM_TYPE_SPIRIT_LIST … #define RADEON_VF_PRIM_TYPE_LINE_LOOP … #define RADEON_VF_PRIM_TYPE_QUAD_LIST … #define RADEON_VF_PRIM_TYPE_QUAD_STRIP … #define RADEON_VF_PRIM_TYPE_POLYGON … #define RADEON_VF_PRIM_WALK_STATE … #define RADEON_VF_PRIM_WALK_INDEX … #define RADEON_VF_PRIM_WALK_LIST … #define RADEON_VF_PRIM_WALK_DATA … #define RADEON_VF_COLOR_ORDER_RGBA … #define RADEON_VF_RADEON_MODE … #define RADEON_VF_TCL_OUTPUT_CTL_ENA … #define RADEON_VF_PROG_STREAM_ENA … #define RADEON_VF_INDEX_SIZE_SHIFT … #define RADEON_VF_NUM_VERTICES_SHIFT … #define RADEON_SE_PORT_DATA0 … #define R200_SE_VAP_CNTL … #define R200_VAP_TCL_ENABLE … #define R200_VAP_SINGLE_BUF_STATE_ENABLE … #define R200_VAP_FORCE_W_TO_ONE … #define R200_VAP_D3D_TEX_DEFAULT … #define R200_VAP_VF_MAX_VTX_NUM__SHIFT … #define R200_VAP_VF_MAX_VTX_NUM … #define R200_VAP_DX_CLIP_SPACE_DEF … #define R200_VF_MAX_VTX_INDX … #define R200_VF_MIN_VTX_INDX … #define R200_SE_VTE_CNTL … #define R200_VPORT_X_SCALE_ENA … #define R200_VPORT_X_OFFSET_ENA … #define R200_VPORT_Y_SCALE_ENA … #define R200_VPORT_Y_OFFSET_ENA … #define R200_VPORT_Z_SCALE_ENA … #define R200_VPORT_Z_OFFSET_ENA … #define R200_VTX_XY_FMT … #define R200_VTX_Z_FMT … #define R200_VTX_W0_FMT … #define R200_VTX_W0_NORMALIZE … #define R200_VTX_ST_DENORMALIZED … #define R200_SE_VAP_CNTL_STATUS … #define R200_VC_NO_SWAP … #define R200_VC_16BIT_SWAP … #define R200_VC_32BIT_SWAP … #define R200_PP_TXFILTER_0 … #define R200_PP_TXFILTER_1 … #define R200_PP_TXFILTER_2 … #define R200_PP_TXFILTER_3 … #define R200_PP_TXFILTER_4 … #define R200_PP_TXFILTER_5 … #define R200_MAG_FILTER_NEAREST … #define R200_MAG_FILTER_LINEAR … #define R200_MAG_FILTER_MASK … #define R200_MIN_FILTER_NEAREST … #define R200_MIN_FILTER_LINEAR … #define R200_MIN_FILTER_NEAREST_MIP_NEAREST … #define R200_MIN_FILTER_NEAREST_MIP_LINEAR … #define R200_MIN_FILTER_LINEAR_MIP_NEAREST … #define R200_MIN_FILTER_LINEAR_MIP_LINEAR … #define R200_MIN_FILTER_ANISO_NEAREST … #define R200_MIN_FILTER_ANISO_LINEAR … #define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST … #define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR … #define R200_MIN_FILTER_MASK … #define R200_MAX_ANISO_1_TO_1 … #define R200_MAX_ANISO_2_TO_1 … #define R200_MAX_ANISO_4_TO_1 … #define R200_MAX_ANISO_8_TO_1 … #define R200_MAX_ANISO_16_TO_1 … #define R200_MAX_ANISO_MASK … #define R200_MAX_MIP_LEVEL_MASK … #define R200_MAX_MIP_LEVEL_SHIFT … #define R200_YUV_TO_RGB … #define R200_YUV_TEMPERATURE_COOL … #define R200_YUV_TEMPERATURE_HOT … #define R200_YUV_TEMPERATURE_MASK … #define R200_WRAPEN_S … #define R200_CLAMP_S_WRAP … #define R200_CLAMP_S_MIRROR … #define R200_CLAMP_S_CLAMP_LAST … #define R200_CLAMP_S_MIRROR_CLAMP_LAST … #define R200_CLAMP_S_CLAMP_BORDER … #define R200_CLAMP_S_MIRROR_CLAMP_BORDER … #define R200_CLAMP_S_CLAMP_GL … #define R200_CLAMP_S_MIRROR_CLAMP_GL … #define R200_CLAMP_S_MASK … #define R200_WRAPEN_T … #define R200_CLAMP_T_WRAP … #define R200_CLAMP_T_MIRROR … #define R200_CLAMP_T_CLAMP_LAST … #define R200_CLAMP_T_MIRROR_CLAMP_LAST … #define R200_CLAMP_T_CLAMP_BORDER … #define R200_CLAMP_T_MIRROR_CLAMP_BORDER … #define R200_CLAMP_T_CLAMP_GL … #define R200_CLAMP_T_MIRROR_CLAMP_GL … #define R200_CLAMP_T_MASK … #define R200_KILL_LT_ZERO … #define R200_BORDER_MODE_OGL … #define R200_BORDER_MODE_D3D … #define R200_PP_TXFORMAT_0 … #define R200_PP_TXFORMAT_1 … #define R200_PP_TXFORMAT_2 … #define R200_PP_TXFORMAT_3 … #define R200_PP_TXFORMAT_4 … #define R200_PP_TXFORMAT_5 … #define R200_TXFORMAT_I8 … #define R200_TXFORMAT_AI88 … #define R200_TXFORMAT_RGB332 … #define R200_TXFORMAT_ARGB1555 … #define R200_TXFORMAT_RGB565 … #define R200_TXFORMAT_ARGB4444 … #define R200_TXFORMAT_ARGB8888 … #define R200_TXFORMAT_RGBA8888 … #define R200_TXFORMAT_Y8 … #define R200_TXFORMAT_AVYU4444 … #define R200_TXFORMAT_VYUY422 … #define R200_TXFORMAT_YVYU422 … #define R200_TXFORMAT_DXT1 … #define R200_TXFORMAT_DXT23 … #define R200_TXFORMAT_DXT45 … #define R200_TXFORMAT_DVDU88 … #define R200_TXFORMAT_LDVDU655 … #define R200_TXFORMAT_LDVDU8888 … #define R200_TXFORMAT_GR1616 … #define R200_TXFORMAT_ABGR8888 … #define R200_TXFORMAT_BGR111110 … #define R200_TXFORMAT_FORMAT_MASK … #define R200_TXFORMAT_FORMAT_SHIFT … #define R200_TXFORMAT_ALPHA_IN_MAP … #define R200_TXFORMAT_NON_POWER2 … #define R200_TXFORMAT_WIDTH_MASK … #define R200_TXFORMAT_WIDTH_SHIFT … #define R200_TXFORMAT_HEIGHT_MASK … #define R200_TXFORMAT_HEIGHT_SHIFT … #define R200_TXFORMAT_F5_WIDTH_MASK … #define R200_TXFORMAT_F5_WIDTH_SHIFT … #define R200_TXFORMAT_F5_HEIGHT_MASK … #define R200_TXFORMAT_F5_HEIGHT_SHIFT … #define R200_TXFORMAT_ST_ROUTE_STQ0 … #define R200_TXFORMAT_ST_ROUTE_STQ1 … #define R200_TXFORMAT_ST_ROUTE_STQ2 … #define R200_TXFORMAT_ST_ROUTE_STQ3 … #define R200_TXFORMAT_ST_ROUTE_STQ4 … #define R200_TXFORMAT_ST_ROUTE_STQ5 … #define R200_TXFORMAT_ST_ROUTE_MASK … #define R200_TXFORMAT_ST_ROUTE_SHIFT … #define R200_TXFORMAT_LOOKUP_DISABLE … #define R200_TXFORMAT_ALPHA_MASK_ENABLE … #define R200_TXFORMAT_CHROMA_KEY_ENABLE … #define R200_TXFORMAT_CUBIC_MAP_ENABLE … #define R200_PP_TXFORMAT_X_0 … #define R200_PP_TXFORMAT_X_1 … #define R200_PP_TXFORMAT_X_2 … #define R200_PP_TXFORMAT_X_3 … #define R200_PP_TXFORMAT_X_4 … #define R200_PP_TXFORMAT_X_5 … #define R200_PP_TXSIZE_0 … #define R200_PP_TXSIZE_1 … #define R200_PP_TXSIZE_2 … #define R200_PP_TXSIZE_3 … #define R200_PP_TXSIZE_4 … #define R200_PP_TXSIZE_5 … #define R200_PP_TXPITCH_0 … #define R200_PP_TXPITCH_1 … #define R200_PP_TXPITCH_2 … #define R200_PP_TXPITCH_3 … #define R200_PP_TXPITCH_4 … #define R200_PP_TXPITCH_5 … #define R200_PP_CUBIC_FACES_0 … #define R200_PP_CUBIC_FACES_1 … #define R200_PP_CUBIC_FACES_2 … #define R200_PP_CUBIC_FACES_3 … #define R200_PP_CUBIC_FACES_4 … #define R200_PP_CUBIC_FACES_5 … #define R200_PP_TXOFFSET_0 … #define R200_TXO_ENDIAN_NO_SWAP … #define R200_TXO_ENDIAN_BYTE_SWAP … #define R200_TXO_ENDIAN_WORD_SWAP … #define R200_TXO_ENDIAN_HALFDW_SWAP … #define R200_TXO_MACRO_LINEAR … #define R200_TXO_MACRO_TILE … #define R200_TXO_MICRO_LINEAR … #define R200_TXO_MICRO_TILE … #define R200_TXO_OFFSET_MASK … #define R200_TXO_OFFSET_SHIFT … #define R200_PP_CUBIC_OFFSET_F1_0 … #define R200_PP_CUBIC_OFFSET_F2_0 … #define R200_PP_CUBIC_OFFSET_F3_0 … #define R200_PP_CUBIC_OFFSET_F4_0 … #define R200_PP_CUBIC_OFFSET_F5_0 … #define R200_PP_TXOFFSET_1 … #define R200_PP_CUBIC_OFFSET_F1_1 … #define R200_PP_CUBIC_OFFSET_F2_1 … #define R200_PP_CUBIC_OFFSET_F3_1 … #define R200_PP_CUBIC_OFFSET_F4_1 … #define R200_PP_CUBIC_OFFSET_F5_1 … #define R200_PP_TXOFFSET_2 … #define R200_PP_CUBIC_OFFSET_F1_2 … #define R200_PP_CUBIC_OFFSET_F2_2 … #define R200_PP_CUBIC_OFFSET_F3_2 … #define R200_PP_CUBIC_OFFSET_F4_2 … #define R200_PP_CUBIC_OFFSET_F5_2 … #define R200_PP_TXOFFSET_3 … #define R200_PP_CUBIC_OFFSET_F1_3 … #define R200_PP_CUBIC_OFFSET_F2_3 … #define R200_PP_CUBIC_OFFSET_F3_3 … #define R200_PP_CUBIC_OFFSET_F4_3 … #define R200_PP_CUBIC_OFFSET_F5_3 … #define R200_PP_TXOFFSET_4 … #define R200_PP_CUBIC_OFFSET_F1_4 … #define R200_PP_CUBIC_OFFSET_F2_4 … #define R200_PP_CUBIC_OFFSET_F3_4 … #define R200_PP_CUBIC_OFFSET_F4_4 … #define R200_PP_CUBIC_OFFSET_F5_4 … #define R200_PP_TXOFFSET_5 … #define R200_PP_CUBIC_OFFSET_F1_5 … #define R200_PP_CUBIC_OFFSET_F2_5 … #define R200_PP_CUBIC_OFFSET_F3_5 … #define R200_PP_CUBIC_OFFSET_F4_5 … #define R200_PP_CUBIC_OFFSET_F5_5 … #define R200_PP_TFACTOR_0 … #define R200_PP_TFACTOR_1 … #define R200_PP_TFACTOR_2 … #define R200_PP_TFACTOR_3 … #define R200_PP_TFACTOR_4 … #define R200_PP_TFACTOR_5 … #define R200_PP_TXCBLEND_0 … #define R200_TXC_ARG_A_ZERO … #define R200_TXC_ARG_A_CURRENT_COLOR … #define R200_TXC_ARG_A_CURRENT_ALPHA … #define R200_TXC_ARG_A_DIFFUSE_COLOR … #define R200_TXC_ARG_A_DIFFUSE_ALPHA … #define R200_TXC_ARG_A_SPECULAR_COLOR … #define R200_TXC_ARG_A_SPECULAR_ALPHA … #define R200_TXC_ARG_A_TFACTOR_COLOR … #define R200_TXC_ARG_A_TFACTOR_ALPHA … #define R200_TXC_ARG_A_R0_COLOR … #define R200_TXC_ARG_A_R0_ALPHA … #define R200_TXC_ARG_A_R1_COLOR … #define R200_TXC_ARG_A_R1_ALPHA … #define R200_TXC_ARG_A_R2_COLOR … #define R200_TXC_ARG_A_R2_ALPHA … #define R200_TXC_ARG_A_R3_COLOR … #define R200_TXC_ARG_A_R3_ALPHA … #define R200_TXC_ARG_A_R4_COLOR … #define R200_TXC_ARG_A_R4_ALPHA … #define R200_TXC_ARG_A_R5_COLOR … #define R200_TXC_ARG_A_R5_ALPHA … #define R200_TXC_ARG_A_TFACTOR1_COLOR … #define R200_TXC_ARG_A_TFACTOR1_ALPHA … #define R200_TXC_ARG_A_MASK … #define R200_TXC_ARG_A_SHIFT … #define R200_TXC_ARG_B_ZERO … #define R200_TXC_ARG_B_CURRENT_COLOR … #define R200_TXC_ARG_B_CURRENT_ALPHA … #define R200_TXC_ARG_B_DIFFUSE_COLOR … #define R200_TXC_ARG_B_DIFFUSE_ALPHA … #define R200_TXC_ARG_B_SPECULAR_COLOR … #define R200_TXC_ARG_B_SPECULAR_ALPHA … #define R200_TXC_ARG_B_TFACTOR_COLOR … #define R200_TXC_ARG_B_TFACTOR_ALPHA … #define R200_TXC_ARG_B_R0_COLOR … #define R200_TXC_ARG_B_R0_ALPHA … #define R200_TXC_ARG_B_R1_COLOR … #define R200_TXC_ARG_B_R1_ALPHA … #define R200_TXC_ARG_B_R2_COLOR … #define R200_TXC_ARG_B_R2_ALPHA … #define R200_TXC_ARG_B_R3_COLOR … #define R200_TXC_ARG_B_R3_ALPHA … #define R200_TXC_ARG_B_R4_COLOR … #define R200_TXC_ARG_B_R4_ALPHA … #define R200_TXC_ARG_B_R5_COLOR … #define R200_TXC_ARG_B_R5_ALPHA … #define R200_TXC_ARG_B_TFACTOR1_COLOR … #define R200_TXC_ARG_B_TFACTOR1_ALPHA … #define R200_TXC_ARG_B_MASK … #define R200_TXC_ARG_B_SHIFT … #define R200_TXC_ARG_C_ZERO … #define R200_TXC_ARG_C_CURRENT_COLOR … #define R200_TXC_ARG_C_CURRENT_ALPHA … #define R200_TXC_ARG_C_DIFFUSE_COLOR … #define R200_TXC_ARG_C_DIFFUSE_ALPHA … #define R200_TXC_ARG_C_SPECULAR_COLOR … #define R200_TXC_ARG_C_SPECULAR_ALPHA … #define R200_TXC_ARG_C_TFACTOR_COLOR … #define R200_TXC_ARG_C_TFACTOR_ALPHA … #define R200_TXC_ARG_C_R0_COLOR … #define R200_TXC_ARG_C_R0_ALPHA … #define R200_TXC_ARG_C_R1_COLOR … #define R200_TXC_ARG_C_R1_ALPHA … #define R200_TXC_ARG_C_R2_COLOR … #define R200_TXC_ARG_C_R2_ALPHA … #define R200_TXC_ARG_C_R3_COLOR … #define R200_TXC_ARG_C_R3_ALPHA … #define R200_TXC_ARG_C_R4_COLOR … #define R200_TXC_ARG_C_R4_ALPHA … #define R200_TXC_ARG_C_R5_COLOR … #define R200_TXC_ARG_C_R5_ALPHA … #define R200_TXC_ARG_C_TFACTOR1_COLOR … #define R200_TXC_ARG_C_TFACTOR1_ALPHA … #define R200_TXC_ARG_C_MASK … #define R200_TXC_ARG_C_SHIFT … #define R200_TXC_COMP_ARG_A … #define R200_TXC_COMP_ARG_A_SHIFT … #define R200_TXC_BIAS_ARG_A … #define R200_TXC_SCALE_ARG_A … #define R200_TXC_NEG_ARG_A … #define R200_TXC_COMP_ARG_B … #define R200_TXC_COMP_ARG_B_SHIFT … #define R200_TXC_BIAS_ARG_B … #define R200_TXC_SCALE_ARG_B … #define R200_TXC_NEG_ARG_B … #define R200_TXC_COMP_ARG_C … #define R200_TXC_COMP_ARG_C_SHIFT … #define R200_TXC_BIAS_ARG_C … #define R200_TXC_SCALE_ARG_C … #define R200_TXC_NEG_ARG_C … #define R200_TXC_OP_MADD … #define R200_TXC_OP_CND0 … #define R200_TXC_OP_LERP … #define R200_TXC_OP_DOT3 … #define R200_TXC_OP_DOT4 … #define R200_TXC_OP_CONDITIONAL … #define R200_TXC_OP_DOT2_ADD … #define R200_TXC_OP_MASK … #define R200_PP_TXCBLEND2_0 … #define R200_TXC_TFACTOR_SEL_SHIFT … #define R200_TXC_TFACTOR_SEL_MASK … #define R200_TXC_TFACTOR1_SEL_SHIFT … #define R200_TXC_TFACTOR1_SEL_MASK … #define R200_TXC_SCALE_SHIFT … #define R200_TXC_SCALE_MASK … #define R200_TXC_SCALE_1X … #define R200_TXC_SCALE_2X … #define R200_TXC_SCALE_4X … #define R200_TXC_SCALE_8X … #define R200_TXC_SCALE_INV2 … #define R200_TXC_SCALE_INV4 … #define R200_TXC_SCALE_INV8 … #define R200_TXC_CLAMP_SHIFT … #define R200_TXC_CLAMP_MASK … #define R200_TXC_CLAMP_WRAP … #define R200_TXC_CLAMP_0_1 … #define R200_TXC_CLAMP_8_8 … #define R200_TXC_OUTPUT_REG_MASK … #define R200_TXC_OUTPUT_REG_NONE … #define R200_TXC_OUTPUT_REG_R0 … #define R200_TXC_OUTPUT_REG_R1 … #define R200_TXC_OUTPUT_REG_R2 … #define R200_TXC_OUTPUT_REG_R3 … #define R200_TXC_OUTPUT_REG_R4 … #define R200_TXC_OUTPUT_REG_R5 … #define R200_TXC_OUTPUT_MASK_MASK … #define R200_TXC_OUTPUT_MASK_RGB … #define R200_TXC_OUTPUT_MASK_RG … #define R200_TXC_OUTPUT_MASK_RB … #define R200_TXC_OUTPUT_MASK_R … #define R200_TXC_OUTPUT_MASK_GB … #define R200_TXC_OUTPUT_MASK_G … #define R200_TXC_OUTPUT_MASK_B … #define R200_TXC_OUTPUT_MASK_NONE … #define R200_TXC_REPL_NORMAL … #define R200_TXC_REPL_RED … #define R200_TXC_REPL_GREEN … #define R200_TXC_REPL_BLUE … #define R200_TXC_REPL_ARG_A_SHIFT … #define R200_TXC_REPL_ARG_A_MASK … #define R200_TXC_REPL_ARG_B_SHIFT … #define R200_TXC_REPL_ARG_B_MASK … #define R200_TXC_REPL_ARG_C_SHIFT … #define R200_TXC_REPL_ARG_C_MASK … #define R200_PP_TXABLEND_0 … #define R200_TXA_ARG_A_ZERO … #define R200_TXA_ARG_A_CURRENT_ALPHA … #define R200_TXA_ARG_A_CURRENT_BLUE … #define R200_TXA_ARG_A_DIFFUSE_ALPHA … #define R200_TXA_ARG_A_DIFFUSE_BLUE … #define R200_TXA_ARG_A_SPECULAR_ALPHA … #define R200_TXA_ARG_A_SPECULAR_BLUE … #define R200_TXA_ARG_A_TFACTOR_ALPHA … #define R200_TXA_ARG_A_TFACTOR_BLUE … #define R200_TXA_ARG_A_R0_ALPHA … #define R200_TXA_ARG_A_R0_BLUE … #define R200_TXA_ARG_A_R1_ALPHA … #define R200_TXA_ARG_A_R1_BLUE … #define R200_TXA_ARG_A_R2_ALPHA … #define R200_TXA_ARG_A_R2_BLUE … #define R200_TXA_ARG_A_R3_ALPHA … #define R200_TXA_ARG_A_R3_BLUE … #define R200_TXA_ARG_A_R4_ALPHA … #define R200_TXA_ARG_A_R4_BLUE … #define R200_TXA_ARG_A_R5_ALPHA … #define R200_TXA_ARG_A_R5_BLUE … #define R200_TXA_ARG_A_TFACTOR1_ALPHA … #define R200_TXA_ARG_A_TFACTOR1_BLUE … #define R200_TXA_ARG_A_MASK … #define R200_TXA_ARG_A_SHIFT … #define R200_TXA_ARG_B_ZERO … #define R200_TXA_ARG_B_CURRENT_ALPHA … #define R200_TXA_ARG_B_CURRENT_BLUE … #define R200_TXA_ARG_B_DIFFUSE_ALPHA … #define R200_TXA_ARG_B_DIFFUSE_BLUE … #define R200_TXA_ARG_B_SPECULAR_ALPHA … #define R200_TXA_ARG_B_SPECULAR_BLUE … #define R200_TXA_ARG_B_TFACTOR_ALPHA … #define R200_TXA_ARG_B_TFACTOR_BLUE … #define R200_TXA_ARG_B_R0_ALPHA … #define R200_TXA_ARG_B_R0_BLUE … #define R200_TXA_ARG_B_R1_ALPHA … #define R200_TXA_ARG_B_R1_BLUE … #define R200_TXA_ARG_B_R2_ALPHA … #define R200_TXA_ARG_B_R2_BLUE … #define R200_TXA_ARG_B_R3_ALPHA … #define R200_TXA_ARG_B_R3_BLUE … #define R200_TXA_ARG_B_R4_ALPHA … #define R200_TXA_ARG_B_R4_BLUE … #define R200_TXA_ARG_B_R5_ALPHA … #define R200_TXA_ARG_B_R5_BLUE … #define R200_TXA_ARG_B_TFACTOR1_ALPHA … #define R200_TXA_ARG_B_TFACTOR1_BLUE … #define R200_TXA_ARG_B_MASK … #define R200_TXA_ARG_B_SHIFT … #define R200_TXA_ARG_C_ZERO … #define R200_TXA_ARG_C_CURRENT_ALPHA … #define R200_TXA_ARG_C_CURRENT_BLUE … #define R200_TXA_ARG_C_DIFFUSE_ALPHA … #define R200_TXA_ARG_C_DIFFUSE_BLUE … #define R200_TXA_ARG_C_SPECULAR_ALPHA … #define R200_TXA_ARG_C_SPECULAR_BLUE … #define R200_TXA_ARG_C_TFACTOR_ALPHA … #define R200_TXA_ARG_C_TFACTOR_BLUE … #define R200_TXA_ARG_C_R0_ALPHA … #define R200_TXA_ARG_C_R0_BLUE … #define R200_TXA_ARG_C_R1_ALPHA … #define R200_TXA_ARG_C_R1_BLUE … #define R200_TXA_ARG_C_R2_ALPHA … #define R200_TXA_ARG_C_R2_BLUE … #define R200_TXA_ARG_C_R3_ALPHA … #define R200_TXA_ARG_C_R3_BLUE … #define R200_TXA_ARG_C_R4_ALPHA … #define R200_TXA_ARG_C_R4_BLUE … #define R200_TXA_ARG_C_R5_ALPHA … #define R200_TXA_ARG_C_R5_BLUE … #define R200_TXA_ARG_C_TFACTOR1_ALPHA … #define R200_TXA_ARG_C_TFACTOR1_BLUE … #define R200_TXA_ARG_C_MASK … #define R200_TXA_ARG_C_SHIFT … #define R200_TXA_COMP_ARG_A … #define R200_TXA_COMP_ARG_A_SHIFT … #define R200_TXA_BIAS_ARG_A … #define R200_TXA_SCALE_ARG_A … #define R200_TXA_NEG_ARG_A … #define R200_TXA_COMP_ARG_B … #define R200_TXA_COMP_ARG_B_SHIFT … #define R200_TXA_BIAS_ARG_B … #define R200_TXA_SCALE_ARG_B … #define R200_TXA_NEG_ARG_B … #define R200_TXA_COMP_ARG_C … #define R200_TXA_COMP_ARG_C_SHIFT … #define R200_TXA_BIAS_ARG_C … #define R200_TXA_SCALE_ARG_C … #define R200_TXA_NEG_ARG_C … #define R200_TXA_OP_MADD … #define R200_TXA_OP_CND0 … #define R200_TXA_OP_LERP … #define R200_TXA_OP_CONDITIONAL … #define R200_TXA_OP_MASK … #define R200_PP_TXABLEND2_0 … #define R200_TXA_TFACTOR_SEL_SHIFT … #define R200_TXA_TFACTOR_SEL_MASK … #define R200_TXA_TFACTOR1_SEL_SHIFT … #define R200_TXA_TFACTOR1_SEL_MASK … #define R200_TXA_SCALE_SHIFT … #define R200_TXA_SCALE_MASK … #define R200_TXA_SCALE_1X … #define R200_TXA_SCALE_2X … #define R200_TXA_SCALE_4X … #define R200_TXA_SCALE_8X … #define R200_TXA_SCALE_INV2 … #define R200_TXA_SCALE_INV4 … #define R200_TXA_SCALE_INV8 … #define R200_TXA_CLAMP_SHIFT … #define R200_TXA_CLAMP_MASK … #define R200_TXA_CLAMP_WRAP … #define R200_TXA_CLAMP_0_1 … #define R200_TXA_CLAMP_8_8 … #define R200_TXA_OUTPUT_REG_MASK … #define R200_TXA_OUTPUT_REG_NONE … #define R200_TXA_OUTPUT_REG_R0 … #define R200_TXA_OUTPUT_REG_R1 … #define R200_TXA_OUTPUT_REG_R2 … #define R200_TXA_OUTPUT_REG_R3 … #define R200_TXA_OUTPUT_REG_R4 … #define R200_TXA_OUTPUT_REG_R5 … #define R200_TXA_DOT_ALPHA … #define R200_TXA_REPL_NORMAL … #define R200_TXA_REPL_RED … #define R200_TXA_REPL_GREEN … #define R200_TXA_REPL_ARG_A_SHIFT … #define R200_TXA_REPL_ARG_A_MASK … #define R200_TXA_REPL_ARG_B_SHIFT … #define R200_TXA_REPL_ARG_B_MASK … #define R200_TXA_REPL_ARG_C_SHIFT … #define R200_TXA_REPL_ARG_C_MASK … #define R200_SE_VTX_FMT_0 … #define R200_VTX_XY … #define R200_VTX_Z0 … #define R200_VTX_W0 … #define R200_VTX_WEIGHT_COUNT_SHIFT … #define R200_VTX_PV_MATRIX_SEL … #define R200_VTX_N0 … #define R200_VTX_POINT_SIZE … #define R200_VTX_DISCRETE_FOG … #define R200_VTX_SHININESS_0 … #define R200_VTX_SHININESS_1 … #define R200_VTX_COLOR_NOT_PRESENT … #define R200_VTX_PK_RGBA … #define R200_VTX_FP_RGB … #define R200_VTX_FP_RGBA … #define R200_VTX_COLOR_MASK … #define R200_VTX_COLOR_0_SHIFT … #define R200_VTX_COLOR_1_SHIFT … #define R200_VTX_COLOR_2_SHIFT … #define R200_VTX_COLOR_3_SHIFT … #define R200_VTX_COLOR_4_SHIFT … #define R200_VTX_COLOR_5_SHIFT … #define R200_VTX_COLOR_6_SHIFT … #define R200_VTX_COLOR_7_SHIFT … #define R200_VTX_XY1 … #define R200_VTX_Z1 … #define R200_VTX_W1 … #define R200_VTX_N1 … #define R200_SE_VTX_FMT_1 … #define R200_VTX_TEX0_COMP_CNT_SHIFT … #define R200_VTX_TEX1_COMP_CNT_SHIFT … #define R200_VTX_TEX2_COMP_CNT_SHIFT … #define R200_VTX_TEX3_COMP_CNT_SHIFT … #define R200_VTX_TEX4_COMP_CNT_SHIFT … #define R200_VTX_TEX5_COMP_CNT_SHIFT … #define R200_SE_TCL_OUTPUT_VTX_FMT_0 … #define R200_SE_TCL_OUTPUT_VTX_FMT_1 … #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL … #define R200_OUTPUT_XYZW … #define R200_OUTPUT_COLOR_0 … #define R200_OUTPUT_COLOR_1 … #define R200_OUTPUT_TEX_0 … #define R200_OUTPUT_TEX_1 … #define R200_OUTPUT_TEX_2 … #define R200_OUTPUT_TEX_3 … #define R200_OUTPUT_TEX_4 … #define R200_OUTPUT_TEX_5 … #define R200_OUTPUT_TEX_MASK … #define R200_OUTPUT_DISCRETE_FOG … #define R200_OUTPUT_PT_SIZE … #define R200_FORCE_INORDER_PROC … #define R200_PP_CNTL_X … #define R200_PP_TXMULTI_CTL_0 … #define R200_PP_TXMULTI_CTL_1 … #define R200_PP_TXMULTI_CTL_2 … #define R200_PP_TXMULTI_CTL_3 … #define R200_PP_TXMULTI_CTL_4 … #define R200_PP_TXMULTI_CTL_5 … #define R200_SE_VTX_STATE_CNTL … #define R200_UPDATE_USER_COLOR_0_ENA_MASK … /* Registers for CP and Microcode Engine */ #define RADEON_CP_ME_RAM_ADDR … #define RADEON_CP_ME_RAM_RADDR … #define RADEON_CP_ME_RAM_DATAH … #define RADEON_CP_ME_RAM_DATAL … #define RADEON_CP_RB_BASE … #define RADEON_CP_RB_CNTL … #define RADEON_RB_BUFSZ_SHIFT … #define RADEON_RB_BUFSZ_MASK … #define RADEON_RB_BLKSZ_SHIFT … #define RADEON_RB_BLKSZ_MASK … #define RADEON_BUF_SWAP_32BIT … #define RADEON_MAX_FETCH_SHIFT … #define RADEON_MAX_FETCH_MASK … #define RADEON_RB_NO_UPDATE … #define RADEON_RB_RPTR_WR_ENA … #define RADEON_CP_RB_RPTR_ADDR … #define RADEON_CP_RB_RPTR … #define RADEON_CP_RB_WPTR … #define RADEON_CP_RB_RPTR_WR … #define RADEON_SCRATCH_UMSK … #define RADEON_SCRATCH_ADDR … #define R600_CP_RB_BASE … #define R600_CP_RB_CNTL … #define R600_RB_BUFSZ(x) … #define R600_RB_BLKSZ(x) … #define R600_RB_NO_UPDATE … #define R600_RB_RPTR_WR_ENA … #define R600_CP_RB_RPTR_WR … #define R600_CP_RB_RPTR_ADDR … #define R600_CP_RB_RPTR_ADDR_HI … #define R600_CP_RB_WPTR … #define R600_CP_RB_WPTR_ADDR … #define R600_CP_RB_WPTR_ADDR_HI … #define R600_CP_RB_RPTR … #define R600_CP_RB_WPTR_DELAY … #define RADEON_CP_IB_BASE … #define RADEON_CP_IB_BUFSZ … #define RADEON_CP_CSQ_CNTL … #define RADEON_CSQ_CNT_PRIMARY_MASK … #define RADEON_CSQ_PRIDIS_INDDIS … #define RADEON_CSQ_PRIPIO_INDDIS … #define RADEON_CSQ_PRIBM_INDDIS … #define RADEON_CSQ_PRIPIO_INDBM … #define RADEON_CSQ_PRIBM_INDBM … #define RADEON_CSQ_PRIPIO_INDPIO … #define R300_CP_RESYNC_ADDR … #define R300_CP_RESYNC_DATA … #define RADEON_CP_CSQ_STAT … #define RADEON_CSQ_RPTR_PRIMARY_MASK … #define RADEON_CSQ_WPTR_PRIMARY_MASK … #define RADEON_CSQ_RPTR_INDIRECT_MASK … #define RADEON_CSQ_WPTR_INDIRECT_MASK … #define RADEON_CP_CSQ2_STAT … #define RADEON_CP_CSQ_ADDR … #define RADEON_CP_CSQ_DATA … #define RADEON_CP_CSQ_APER_PRIMARY … #define RADEON_CP_CSQ_APER_INDIRECT … #define RADEON_CP_RB_WPTR_DELAY … #define RADEON_PRE_WRITE_TIMER_SHIFT … #define RADEON_PRE_WRITE_LIMIT_SHIFT … #define RADEON_CP_CSQ_MODE … #define RADEON_INDIRECT2_START_SHIFT … #define RADEON_INDIRECT2_START_MASK … #define RADEON_INDIRECT1_START_SHIFT … #define RADEON_INDIRECT1_START_MASK … #define RADEON_AIC_CNTL … #define RADEON_PCIGART_TRANSLATE_EN … #define RADEON_DIS_OUT_OF_PCI_GART_ACCESS … #define RS400_MSI_REARM … #define RADEON_AIC_LO_ADDR … #define RADEON_AIC_PT_BASE … #define RADEON_AIC_HI_ADDR … /* Constants */ /* #define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0 */ /* efine RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2 */ /* CP packet types */ #define RADEON_CP_PACKET0 … #define RADEON_CP_PACKET1 … #define RADEON_CP_PACKET2 … #define RADEON_CP_PACKET3 … #define RADEON_CP_PACKET_MASK … #define RADEON_CP_PACKET_COUNT_MASK … #define RADEON_CP_PACKET_MAX_DWORDS … #define RADEON_CP_PACKET0_REG_MASK … #define R300_CP_PACKET0_REG_MASK … #define R600_CP_PACKET0_REG_MASK … #define RADEON_CP_PACKET1_REG0_MASK … #define RADEON_CP_PACKET1_REG1_MASK … #define RADEON_CP_PACKET0_ONE_REG_WR … #define RADEON_CP_PACKET3_NOP … #define RADEON_CP_PACKET3_NEXT_CHAR … #define RADEON_CP_PACKET3_PLY_NEXTSCAN … #define RADEON_CP_PACKET3_SET_SCISSORS … #define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM … #define RADEON_CP_PACKET3_LOAD_MICROCODE … #define RADEON_CP_PACKET3_WAIT_FOR_IDLE … #define RADEON_CP_PACKET3_3D_DRAW_VBUF … #define RADEON_CP_PACKET3_3D_DRAW_IMMD … #define RADEON_CP_PACKET3_3D_DRAW_INDX … #define RADEON_CP_PACKET3_LOAD_PALETTE … #define R200_CP_PACKET3_3D_DRAW_IMMD_2 … #define RADEON_CP_PACKET3_3D_LOAD_VBPNTR … #define RADEON_CP_PACKET3_CNTL_PAINT … #define RADEON_CP_PACKET3_CNTL_BITBLT … #define RADEON_CP_PACKET3_CNTL_SMALLTEXT … #define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT … #define RADEON_CP_PACKET3_CNTL_POLYLINE … #define RADEON_CP_PACKET3_CNTL_POLYSCANLINES … #define RADEON_CP_PACKET3_CNTL_PAINT_MULTI … #define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI … #define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT … #define RADEON_CP_VC_FRMT_XY … #define RADEON_CP_VC_FRMT_W0 … #define RADEON_CP_VC_FRMT_FPCOLOR … #define RADEON_CP_VC_FRMT_FPALPHA … #define RADEON_CP_VC_FRMT_PKCOLOR … #define RADEON_CP_VC_FRMT_FPSPEC … #define RADEON_CP_VC_FRMT_FPFOG … #define RADEON_CP_VC_FRMT_PKSPEC … #define RADEON_CP_VC_FRMT_ST0 … #define RADEON_CP_VC_FRMT_ST1 … #define RADEON_CP_VC_FRMT_Q1 … #define RADEON_CP_VC_FRMT_ST2 … #define RADEON_CP_VC_FRMT_Q2 … #define RADEON_CP_VC_FRMT_ST3 … #define RADEON_CP_VC_FRMT_Q3 … #define RADEON_CP_VC_FRMT_Q0 … #define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK … #define RADEON_CP_VC_FRMT_N0 … #define RADEON_CP_VC_FRMT_XY1 … #define RADEON_CP_VC_FRMT_Z1 … #define RADEON_CP_VC_FRMT_W1 … #define RADEON_CP_VC_FRMT_N1 … #define RADEON_CP_VC_FRMT_Z … #define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE … #define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT … #define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE … #define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP … #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST … #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN … #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP … #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 … #define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST … #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST … #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST … #define RADEON_CP_VC_CNTL_PRIM_WALK_IND … #define RADEON_CP_VC_CNTL_PRIM_WALK_LIST … #define RADEON_CP_VC_CNTL_PRIM_WALK_RING … #define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA … #define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA … #define RADEON_CP_VC_CNTL_MAOS_ENABLE … #define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE … #define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE … #define RADEON_CP_VC_CNTL_TCL_DISABLE … #define RADEON_CP_VC_CNTL_TCL_ENABLE … #define RADEON_CP_VC_CNTL_NUM_SHIFT … #define RADEON_VS_MATRIX_0_ADDR … #define RADEON_VS_MATRIX_1_ADDR … #define RADEON_VS_MATRIX_2_ADDR … #define RADEON_VS_MATRIX_3_ADDR … #define RADEON_VS_MATRIX_4_ADDR … #define RADEON_VS_MATRIX_5_ADDR … #define RADEON_VS_MATRIX_6_ADDR … #define RADEON_VS_MATRIX_7_ADDR … #define RADEON_VS_MATRIX_8_ADDR … #define RADEON_VS_MATRIX_9_ADDR … #define RADEON_VS_MATRIX_10_ADDR … #define RADEON_VS_MATRIX_11_ADDR … #define RADEON_VS_MATRIX_12_ADDR … #define RADEON_VS_MATRIX_13_ADDR … #define RADEON_VS_MATRIX_14_ADDR … #define RADEON_VS_MATRIX_15_ADDR … #define RADEON_VS_LIGHT_AMBIENT_ADDR … #define RADEON_VS_LIGHT_DIFFUSE_ADDR … #define RADEON_VS_LIGHT_SPECULAR_ADDR … #define RADEON_VS_LIGHT_DIRPOS_ADDR … #define RADEON_VS_LIGHT_HWVSPOT_ADDR … #define RADEON_VS_LIGHT_ATTENUATION_ADDR … #define RADEON_VS_MATRIX_EYE2CLIP_ADDR … #define RADEON_VS_UCP_ADDR … #define RADEON_VS_GLOBAL_AMBIENT_ADDR … #define RADEON_VS_FOG_PARAM_ADDR … #define RADEON_VS_EYE_VECTOR_ADDR … #define RADEON_SS_LIGHT_DCD_ADDR … #define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR … #define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR … #define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR … #define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR … #define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR … #define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR … #define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR … #define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR … #define RADEON_SS_SHININESS … #define RADEON_TV_MASTER_CNTL … #define RADEON_TV_ASYNC_RST … #define RADEON_CRT_ASYNC_RST … #define RADEON_RESTART_PHASE_FIX … #define RADEON_TV_FIFO_ASYNC_RST … #define RADEON_VIN_ASYNC_RST … #define RADEON_AUD_ASYNC_RST … #define RADEON_DVS_ASYNC_RST … #define RADEON_CRT_FIFO_CE_EN … #define RADEON_TV_FIFO_CE_EN … #define RADEON_RE_SYNC_NOW_SEL_MASK … #define RADEON_TVCLK_ALWAYS_ONb … #define RADEON_TV_ON … #define RADEON_TV_PRE_DAC_MUX_CNTL … #define RADEON_Y_RED_EN … #define RADEON_C_GRN_EN … #define RADEON_CMP_BLU_EN … #define RADEON_DAC_DITHER_EN … #define RADEON_RED_MX_FORCE_DAC_DATA … #define RADEON_GRN_MX_FORCE_DAC_DATA … #define RADEON_BLU_MX_FORCE_DAC_DATA … #define RADEON_TV_FORCE_DAC_DATA_SHIFT … #define RADEON_TV_RGB_CNTL … #define RADEON_SWITCH_TO_BLUE … #define RADEON_RGB_DITHER_EN … #define RADEON_RGB_SRC_SEL_MASK … #define RADEON_RGB_SRC_SEL_CRTC1 … #define RADEON_RGB_SRC_SEL_RMX … #define RADEON_RGB_SRC_SEL_CRTC2 … #define RADEON_RGB_CONVERT_BY_PASS … #define RADEON_UVRAM_READ_MARGIN_SHIFT … #define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT … #define RADEON_RGB_ATTEN_SEL(x) … #define RADEON_TVOUT_SCALE_EN … #define RADEON_RGB_ATTEN_VAL(x) … #define RADEON_TV_SYNC_CNTL … #define RADEON_SYNC_OE … #define RADEON_SYNC_OUT … #define RADEON_SYNC_IN … #define RADEON_SYNC_PUB … #define RADEON_SYNC_PD … #define RADEON_TV_SYNC_IO_DRIVE … #define RADEON_TV_HTOTAL … #define RADEON_TV_HDISP … #define RADEON_TV_HSTART … #define RADEON_TV_HCOUNT … #define RADEON_TV_VTOTAL … #define RADEON_TV_VDISP … #define RADEON_TV_VCOUNT … #define RADEON_TV_FTOTAL … #define RADEON_TV_FCOUNT … #define RADEON_TV_FRESTART … #define RADEON_TV_HRESTART … #define RADEON_TV_VRESTART … #define RADEON_TV_HOST_READ_DATA … #define RADEON_TV_HOST_WRITE_DATA … #define RADEON_TV_HOST_RD_WT_CNTL … #define RADEON_HOST_FIFO_RD … #define RADEON_HOST_FIFO_RD_ACK … #define RADEON_HOST_FIFO_WT … #define RADEON_HOST_FIFO_WT_ACK … #define RADEON_TV_VSCALER_CNTL1 … #define RADEON_UV_INC_MASK … #define RADEON_UV_INC_SHIFT … #define RADEON_Y_W_EN … #define RADEON_RESTART_FIELD … #define RADEON_Y_DEL_W_SIG_SHIFT … #define RADEON_TV_TIMING_CNTL … #define RADEON_H_INC_MASK … #define RADEON_H_INC_SHIFT … #define RADEON_REQ_Y_FIRST … #define RADEON_FORCE_BURST_ALWAYS … #define RADEON_UV_POST_SCALE_BYPASS … #define RADEON_UV_OUTPUT_POST_SCALE_SHIFT … #define RADEON_TV_VSCALER_CNTL2 … #define RADEON_DITHER_MODE … #define RADEON_Y_OUTPUT_DITHER_EN … #define RADEON_UV_OUTPUT_DITHER_EN … #define RADEON_UV_TO_BUF_DITHER_EN … #define RADEON_TV_Y_FALL_CNTL … #define RADEON_Y_FALL_PING_PONG … #define RADEON_Y_COEF_EN … #define RADEON_TV_Y_RISE_CNTL … #define RADEON_Y_RISE_PING_PONG … #define RADEON_TV_Y_SAW_TOOTH_CNTL … #define RADEON_TV_UPSAMP_AND_GAIN_CNTL … #define RADEON_YUPSAMP_EN … #define RADEON_UVUPSAMP_EN … #define RADEON_TV_GAIN_LIMIT_SETTINGS … #define RADEON_Y_GAIN_LIMIT_SHIFT … #define RADEON_UV_GAIN_LIMIT_SHIFT … #define RADEON_TV_LINEAR_GAIN_SETTINGS … #define RADEON_Y_GAIN_SHIFT … #define RADEON_UV_GAIN_SHIFT … #define RADEON_TV_MODULATOR_CNTL1 … #define RADEON_YFLT_EN … #define RADEON_UVFLT_EN … #define RADEON_ALT_PHASE_EN … #define RADEON_SYNC_TIP_LEVEL … #define RADEON_BLANK_LEVEL_SHIFT … #define RADEON_SET_UP_LEVEL_SHIFT … #define RADEON_SLEW_RATE_LIMIT … #define RADEON_CY_FILT_BLEND_SHIFT … #define RADEON_TV_MODULATOR_CNTL2 … #define RADEON_TV_U_BURST_LEVEL_MASK … #define RADEON_TV_V_BURST_LEVEL_MASK … #define RADEON_TV_V_BURST_LEVEL_SHIFT … #define RADEON_TV_CRC_CNTL … #define RADEON_TV_UV_ADR … #define RADEON_MAX_UV_ADR_MASK … #define RADEON_MAX_UV_ADR_SHIFT … #define RADEON_TABLE1_BOT_ADR_MASK … #define RADEON_TABLE1_BOT_ADR_SHIFT … #define RADEON_TABLE3_TOP_ADR_MASK … #define RADEON_TABLE3_TOP_ADR_SHIFT … #define RADEON_HCODE_TABLE_SEL_MASK … #define RADEON_HCODE_TABLE_SEL_SHIFT … #define RADEON_VCODE_TABLE_SEL_MASK … #define RADEON_VCODE_TABLE_SEL_SHIFT … #define RADEON_TV_MAX_FIFO_ADDR … #define RADEON_TV_MAX_FIFO_ADDR_INTERNAL … #define RADEON_TV_PLL_FINE_CNTL … #define RADEON_TV_PLL_CNTL … #define RADEON_TV_M0LO_MASK … #define RADEON_TV_M0HI_MASK … #define RADEON_TV_M0HI_SHIFT … #define RADEON_TV_N0LO_MASK … #define RADEON_TV_N0LO_SHIFT … #define RADEON_TV_N0HI_MASK … #define RADEON_TV_N0HI_SHIFT … #define RADEON_TV_P_MASK … #define RADEON_TV_P_SHIFT … #define RADEON_TV_SLIP_EN … #define RADEON_TV_DTO_EN … #define RADEON_TV_PLL_CNTL1 … #define RADEON_TVPLL_RESET … #define RADEON_TVPLL_SLEEP … #define RADEON_TVPLL_REFCLK_SEL … #define RADEON_TVPCP_SHIFT … #define RADEON_TVPCP_MASK … #define RADEON_TVPVG_SHIFT … #define RADEON_TVPVG_MASK … #define RADEON_TVPDC_SHIFT … #define RADEON_TVPDC_MASK … #define RADEON_TVPLL_TEST_DIS … #define RADEON_TVCLK_SRC_SEL_TVPLL … #define RS400_DISP2_REQ_CNTL1 … #define RS400_DISP2_START_REQ_LEVEL_SHIFT … #define RS400_DISP2_START_REQ_LEVEL_MASK … #define RS400_DISP2_STOP_REQ_LEVEL_SHIFT … #define RS400_DISP2_STOP_REQ_LEVEL_MASK … #define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT … #define RS400_DISP2_ALLOW_FID_LEVEL_MASK … #define RS400_DISP2_REQ_CNTL2 … #define RS400_DISP2_CRITICAL_POINT_START_SHIFT … #define RS400_DISP2_CRITICAL_POINT_START_MASK … #define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT … #define RS400_DISP2_CRITICAL_POINT_STOP_MASK … #define RS400_DMIF_MEM_CNTL1 … #define RS400_DISP2_START_ADR_SHIFT … #define RS400_DISP2_START_ADR_MASK … #define RS400_DISP1_CRITICAL_POINT_START_SHIFT … #define RS400_DISP1_CRITICAL_POINT_START_MASK … #define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT … #define RS400_DISP1_CRITICAL_POINT_STOP_MASK … #define RS400_DISP1_REQ_CNTL1 … #define RS400_DISP1_START_REQ_LEVEL_SHIFT … #define RS400_DISP1_START_REQ_LEVEL_MASK … #define RS400_DISP1_STOP_REQ_LEVEL_SHIFT … #define RS400_DISP1_STOP_REQ_LEVEL_MASK … #define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT … #define RS400_DISP1_ALLOW_FID_LEVEL_MASK … #define RADEON_PCIE_INDEX … #define RADEON_PCIE_DATA … #define RADEON_PCIE_TX_GART_CNTL … #define RADEON_PCIE_TX_GART_EN … #define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU … #define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO … #define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD … #define RADEON_PCIE_TX_GART_MODE_32_128_CACHE … #define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE … #define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN … #define RADEON_PCIE_TX_GART_INVALIDATE_TLB … #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO … #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI … #define RADEON_PCIE_TX_GART_BASE … #define RADEON_PCIE_TX_GART_START_LO … #define RADEON_PCIE_TX_GART_START_HI … #define RADEON_PCIE_TX_GART_END_LO … #define RADEON_PCIE_TX_GART_END_HI … #define RADEON_PCIE_TX_GART_ERROR … #define RADEON_SCRATCH_REG0 … #define RADEON_SCRATCH_REG1 … #define RADEON_SCRATCH_REG2 … #define RADEON_SCRATCH_REG3 … #define RADEON_SCRATCH_REG4 … #define RADEON_SCRATCH_REG5 … #define RV530_GB_PIPE_SELECT2 … #define RADEON_CP_PACKET_GET_TYPE(h) … #define RADEON_CP_PACKET_GET_COUNT(h) … #define RADEON_CP_PACKET0_GET_ONE_REG_WR(h) … #define RADEON_CP_PACKET3_GET_OPCODE(h) … #define R100_CP_PACKET0_GET_REG(h) … #define R600_CP_PACKET0_GET_REG(h) … #define RADEON_PACKET_TYPE0 … #define RADEON_PACKET_TYPE1 … #define RADEON_PACKET_TYPE2 … #define RADEON_PACKET_TYPE3 … #define RADEON_PACKET3_NOP … #define RADEON_VLINE_STAT … #endif
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