/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie * Alex Deucher * Jerome Glisse */ #ifndef __RADEON_H__ #define __RADEON_H__ /* TODO: Here are things that needs to be done : * - surface allocator & initializer : (bit like scratch reg) should * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings * related to surface * - WB : write back stuff (do it bit like scratch reg things) * - Vblank : look at Jesse's rework and what we should do * - r600/r700: gart & cp * - cs : clean cs ioctl use bitmap & things like that. * - power management stuff * - Barrier in gart code * - Unmappabled vram ? * - TESTING, TESTING, TESTING */ /* Initialization path: * We expect that acceleration initialization might fail for various * reasons even thought we work hard to make it works on most * configurations. In order to still have a working userspace in such * situation the init path must succeed up to the memory controller * initialization point. Failure before this point are considered as * fatal error. Here is the init callchain : * radeon_device_init perform common structure, mutex initialization * asic_init setup the GPU memory layout and perform all * one time initialization (failure in this * function are considered fatal) * asic_startup setup the GPU acceleration, in order to * follow guideline the first thing this * function should do is setting the GPU * memory controller (only MC setup failure * are considered as fatal) */ #include <linux/agp_backend.h> #include <linux/atomic.h> #include <linux/wait.h> #include <linux/list.h> #include <linux/kref.h> #include <linux/interval_tree.h> #include <linux/hashtable.h> #include <linux/dma-fence.h> #ifdef CONFIG_MMU_NOTIFIER #include <linux/mmu_notifier.h> #endif #include <drm/ttm/ttm_bo.h> #include <drm/ttm/ttm_placement.h> #include <drm/ttm/ttm_execbuf_util.h> #include <drm/drm_gem.h> #include <drm/drm_audio_component.h> #include <drm/drm_suballoc.h> #include "radeon_family.h" #include "radeon_mode.h" #include "radeon_reg.h" /* * Modules parameters. */ extern int radeon_no_wb; extern int radeon_modeset; extern int radeon_dynclks; extern int radeon_r4xx_atom; extern int radeon_agpmode; extern int radeon_vram_limit; extern int radeon_gart_size; extern int radeon_benchmarking; extern int radeon_testing; extern int radeon_connector_table; extern int radeon_tv; extern int radeon_audio; extern int radeon_disp_priority; extern int radeon_hw_i2c; extern int radeon_pcie_gen2; extern int radeon_msi; extern int radeon_lockup_timeout; extern int radeon_fastfb; extern int radeon_dpm; extern int radeon_aspm; extern int radeon_runtime_pm; extern int radeon_hard_reset; extern int radeon_vm_size; extern int radeon_vm_block_size; extern int radeon_deep_color; extern int radeon_use_pflipirq; extern int radeon_bapm; extern int radeon_backlight; extern int radeon_auxch; extern int radeon_uvd; extern int radeon_vce; extern int radeon_si_support; extern int radeon_cik_support; /* * Copy from radeon_drv.h so we don't have to include both and have conflicting * symbol; */ #define RADEON_MAX_USEC_TIMEOUT … #define RADEON_FENCE_JIFFIES_TIMEOUT … #define RADEON_USEC_IB_TEST_TIMEOUT … /* RADEON_IB_POOL_SIZE must be a power of 2 */ #define RADEON_IB_POOL_SIZE … #define RADEON_DEBUGFS_MAX_COMPONENTS … #define RADEON_BIOS_NUM_SCRATCH … /* internal ring indices */ /* r1xx+ has gfx CP ring */ #define RADEON_RING_TYPE_GFX_INDEX … /* cayman has 2 compute CP rings */ #define CAYMAN_RING_TYPE_CP1_INDEX … #define CAYMAN_RING_TYPE_CP2_INDEX … /* R600+ has an async dma ring */ #define R600_RING_TYPE_DMA_INDEX … /* cayman add a second async dma ring */ #define CAYMAN_RING_TYPE_DMA1_INDEX … /* R600+ */ #define R600_RING_TYPE_UVD_INDEX … /* TN+ */ #define TN_RING_TYPE_VCE1_INDEX … #define TN_RING_TYPE_VCE2_INDEX … /* max number of rings */ #define RADEON_NUM_RINGS … /* number of hw syncs before falling back on blocking */ #define RADEON_NUM_SYNCS … /* hardcode those limit for now */ #define RADEON_VA_IB_OFFSET … #define RADEON_VA_RESERVED_SIZE … #define RADEON_IB_VM_MAX_SIZE … /* hard reset data */ #define RADEON_ASIC_RESET_DATA … /* reset flags */ #define RADEON_RESET_GFX … #define RADEON_RESET_COMPUTE … #define RADEON_RESET_DMA … #define RADEON_RESET_CP … #define RADEON_RESET_GRBM … #define RADEON_RESET_DMA1 … #define RADEON_RESET_RLC … #define RADEON_RESET_SEM … #define RADEON_RESET_IH … #define RADEON_RESET_VMC … #define RADEON_RESET_MC … #define RADEON_RESET_DISPLAY … /* CG block flags */ #define RADEON_CG_BLOCK_GFX … #define RADEON_CG_BLOCK_MC … #define RADEON_CG_BLOCK_SDMA … #define RADEON_CG_BLOCK_UVD … #define RADEON_CG_BLOCK_VCE … #define RADEON_CG_BLOCK_HDP … #define RADEON_CG_BLOCK_BIF … /* CG flags */ #define RADEON_CG_SUPPORT_GFX_MGCG … #define RADEON_CG_SUPPORT_GFX_MGLS … #define RADEON_CG_SUPPORT_GFX_CGCG … #define RADEON_CG_SUPPORT_GFX_CGLS … #define RADEON_CG_SUPPORT_GFX_CGTS … #define RADEON_CG_SUPPORT_GFX_CGTS_LS … #define RADEON_CG_SUPPORT_GFX_CP_LS … #define RADEON_CG_SUPPORT_GFX_RLC_LS … #define RADEON_CG_SUPPORT_MC_LS … #define RADEON_CG_SUPPORT_MC_MGCG … #define RADEON_CG_SUPPORT_SDMA_LS … #define RADEON_CG_SUPPORT_SDMA_MGCG … #define RADEON_CG_SUPPORT_BIF_LS … #define RADEON_CG_SUPPORT_UVD_MGCG … #define RADEON_CG_SUPPORT_VCE_MGCG … #define RADEON_CG_SUPPORT_HDP_LS … #define RADEON_CG_SUPPORT_HDP_MGCG … /* PG flags */ #define RADEON_PG_SUPPORT_GFX_PG … #define RADEON_PG_SUPPORT_GFX_SMG … #define RADEON_PG_SUPPORT_GFX_DMG … #define RADEON_PG_SUPPORT_UVD … #define RADEON_PG_SUPPORT_VCE … #define RADEON_PG_SUPPORT_CP … #define RADEON_PG_SUPPORT_GDS … #define RADEON_PG_SUPPORT_RLC_SMU_HS … #define RADEON_PG_SUPPORT_SDMA … #define RADEON_PG_SUPPORT_ACP … #define RADEON_PG_SUPPORT_SAMU … /* max cursor sizes (in pixels) */ #define CURSOR_WIDTH … #define CURSOR_HEIGHT … #define CIK_CURSOR_WIDTH … #define CIK_CURSOR_HEIGHT … /* * Errata workarounds. */ enum radeon_pll_errata { … }; struct radeon_device; /* * BIOS. */ bool radeon_get_bios(struct radeon_device *rdev); /* * Dummy page */ struct radeon_dummy_page { … }; int radeon_dummy_page_init(struct radeon_device *rdev); void radeon_dummy_page_fini(struct radeon_device *rdev); /* * Clocks */ struct radeon_clock { … }; /* * Power management */ int radeon_pm_init(struct radeon_device *rdev); int radeon_pm_late_init(struct radeon_device *rdev); void radeon_pm_fini(struct radeon_device *rdev); void radeon_pm_compute_clocks(struct radeon_device *rdev); void radeon_pm_suspend(struct radeon_device *rdev); void radeon_pm_resume(struct radeon_device *rdev); void radeon_combios_get_power_modes(struct radeon_device *rdev); void radeon_atombios_get_power_modes(struct radeon_device *rdev); int radeon_atom_get_clock_dividers(struct radeon_device *rdev, u8 clock_type, u32 clock, bool strobe_mode, struct atom_clock_dividers *dividers); int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, u32 clock, bool strobe_mode, struct atom_mpll_param *mpll_param); void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type, u32 *gpio_value, u32 *gpio_mask); void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, u32 eng_clock, u32 mem_clock); int radeon_atom_get_voltage_step(struct radeon_device *rdev, u8 voltage_type, u16 *voltage_step); int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, u16 voltage_id, u16 *voltage); int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, u16 *voltage, u16 leakage_idx); int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, u16 *leakage_id); int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, u16 *vddc, u16 *vddci, u16 virtual_voltage_id, u16 vbios_voltage_id); int radeon_atom_get_voltage_evv(struct radeon_device *rdev, u16 virtual_voltage_id, u16 *voltage); int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, u8 voltage_type, u16 nominal_voltage, u16 *true_voltage); int radeon_atom_get_min_voltage(struct radeon_device *rdev, u8 voltage_type, u16 *min_voltage); int radeon_atom_get_max_voltage(struct radeon_device *rdev, u8 voltage_type, u16 *max_voltage); int radeon_atom_get_voltage_table(struct radeon_device *rdev, u8 voltage_type, u8 voltage_mode, struct atom_voltage_table *voltage_table); bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, u8 voltage_type, u8 voltage_mode); int radeon_atom_get_svi2_info(struct radeon_device *rdev, u8 voltage_type, u8 *svd_gpio_id, u8 *svc_gpio_id); void radeon_atom_update_memory_dll(struct radeon_device *rdev, u32 mem_clock); void radeon_atom_set_ac_timing(struct radeon_device *rdev, u32 mem_clock); int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, u8 module_index, struct atom_mc_reg_table *reg_table); int radeon_atom_get_memory_info(struct radeon_device *rdev, u8 module_index, struct atom_memory_info *mem_info); int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, bool gddr5, u8 module_index, struct atom_memory_clock_range_table *mclk_range_table); int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, u16 voltage_id, u16 *voltage); void rs690_pm_info(struct radeon_device *rdev); extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, unsigned *bankh, unsigned *mtaspect, unsigned *tile_split); /* * Fences. */ struct radeon_fence_driver { … }; struct radeon_fence { … }; int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); void radeon_fence_driver_init(struct radeon_device *rdev); void radeon_fence_driver_fini(struct radeon_device *rdev); void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); void radeon_fence_process(struct radeon_device *rdev, int ring); bool radeon_fence_signaled(struct radeon_fence *fence); long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout); int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); int radeon_fence_wait_next(struct radeon_device *rdev, int ring); int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); int radeon_fence_wait_any(struct radeon_device *rdev, struct radeon_fence **fences, bool intr); struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); void radeon_fence_unref(struct radeon_fence **fence); unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); void radeon_fence_note_sync(struct radeon_fence *fence, int ring); static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, struct radeon_fence *b) { … } static inline bool radeon_fence_is_earlier(struct radeon_fence *a, struct radeon_fence *b) { … } /* * Tiling registers */ struct radeon_surface_reg { … }; #define RADEON_GEM_MAX_SURFACES … /* * TTM. */ struct radeon_mman { … }; struct radeon_bo_list { … }; /* bo virtual address in a specific vm */ struct radeon_bo_va { … }; struct radeon_bo { … }; #define gem_to_radeon_bo(gobj) … struct radeon_sa_manager { … }; /* * GEM objects. */ struct radeon_gem { … }; extern const struct drm_gem_object_funcs radeon_gem_object_funcs; int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tiled); int radeon_gem_init(struct radeon_device *rdev); void radeon_gem_fini(struct radeon_device *rdev); int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, int alignment, int initial_domain, u32 flags, bool kernel, struct drm_gem_object **obj); int radeon_mode_dumb_create(struct drm_file *file_priv, struct drm_device *dev, struct drm_mode_create_dumb *args); int radeon_mode_dumb_mmap(struct drm_file *filp, struct drm_device *dev, uint32_t handle, uint64_t *offset_p); /* * Semaphores. */ struct radeon_semaphore { … }; int radeon_semaphore_create(struct radeon_device *rdev, struct radeon_semaphore **semaphore); bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, struct radeon_semaphore *semaphore); bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, struct radeon_semaphore *semaphore); void radeon_semaphore_free(struct radeon_device *rdev, struct radeon_semaphore **semaphore, struct radeon_fence *fence); /* * Synchronization */ struct radeon_sync { … }; void radeon_sync_create(struct radeon_sync *sync); void radeon_sync_fence(struct radeon_sync *sync, struct radeon_fence *fence); int radeon_sync_resv(struct radeon_device *rdev, struct radeon_sync *sync, struct dma_resv *resv, bool shared); int radeon_sync_rings(struct radeon_device *rdev, struct radeon_sync *sync, int waiting_ring); void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, struct radeon_fence *fence); /* * GART structures, functions & helpers */ struct radeon_mc; #define RADEON_GPU_PAGE_SIZE … #define RADEON_GPU_PAGE_MASK … #define RADEON_GPU_PAGE_SHIFT … #define RADEON_GPU_PAGE_ALIGN(a) … #define RADEON_GART_PAGE_DUMMY … #define RADEON_GART_PAGE_VALID … #define RADEON_GART_PAGE_READ … #define RADEON_GART_PAGE_WRITE … #define RADEON_GART_PAGE_SNOOP … struct radeon_gart { … }; int radeon_gart_table_ram_alloc(struct radeon_device *rdev); void radeon_gart_table_ram_free(struct radeon_device *rdev); int radeon_gart_table_vram_alloc(struct radeon_device *rdev); void radeon_gart_table_vram_free(struct radeon_device *rdev); int radeon_gart_table_vram_pin(struct radeon_device *rdev); void radeon_gart_table_vram_unpin(struct radeon_device *rdev); int radeon_gart_init(struct radeon_device *rdev); void radeon_gart_fini(struct radeon_device *rdev); void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, int pages); int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, int pages, struct page **pagelist, dma_addr_t *dma_addr, uint32_t flags); /* * GPU MC structures, functions & helpers */ struct radeon_mc { … }; bool radeon_combios_sideport_present(struct radeon_device *rdev); bool radeon_atombios_sideport_present(struct radeon_device *rdev); /* * GPU scratch registers structures, functions & helpers */ struct radeon_scratch { … }; int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); /* * GPU doorbell structures, functions & helpers */ #define RADEON_MAX_DOORBELLS … struct radeon_doorbell { … }; int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); /* * IRQS. */ struct radeon_flip_work { … }; struct r500_irq_stat_regs { … }; struct r600_irq_stat_regs { … }; struct evergreen_irq_stat_regs { … }; struct cik_irq_stat_regs { … }; radeon_irq_stat_regs; struct radeon_irq { … }; int radeon_irq_kms_init(struct radeon_device *rdev); void radeon_irq_kms_fini(struct radeon_device *rdev); void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); /* * CP & rings. */ struct radeon_ib { … }; struct radeon_ring { … }; struct radeon_mec { … }; /* * VM */ /* maximum number of VMIDs */ #define RADEON_NUM_VM … /* number of entries in page table */ #define RADEON_VM_PTE_COUNT … /* PTBs (Page Table Blocks) need to be aligned to 32K */ #define RADEON_VM_PTB_ALIGN_SIZE … #define RADEON_VM_PTB_ALIGN_MASK … #define RADEON_VM_PTB_ALIGN(a) … #define R600_PTE_VALID … #define R600_PTE_SYSTEM … #define R600_PTE_SNOOPED … #define R600_PTE_READABLE … #define R600_PTE_WRITEABLE … /* PTE (Page Table Entry) fragment field for different page sizes */ #define R600_PTE_FRAG_4KB … #define R600_PTE_FRAG_64KB … #define R600_PTE_FRAG_256KB … /* flags needed to be set so we can copy directly from the GART table */ #define R600_PTE_GART_MASK … struct radeon_vm_pt { … }; struct radeon_vm_id { … }; struct radeon_vm { … }; struct radeon_vm_manager { … }; /* * file private structure */ struct radeon_fpriv { … }; /* * R6xx+ IH ring */ struct r600_ih { … }; /* * RLC stuff */ #include "clearstate_defs.h" struct radeon_rlc { … }; int radeon_ib_get(struct radeon_device *rdev, int ring, struct radeon_ib *ib, struct radeon_vm *vm, unsigned size); void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, struct radeon_ib *const_ib, bool hdp_flush); int radeon_ib_pool_init(struct radeon_device *rdev); void radeon_ib_pool_fini(struct radeon_device *rdev); int radeon_ib_ring_tests(struct radeon_device *rdev); /* Ring access between begin & end cannot sleep */ bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, struct radeon_ring *ring); void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, bool hdp_flush); void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, bool hdp_flush); void radeon_ring_undo(struct radeon_ring *ring); void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); void radeon_ring_lockup_update(struct radeon_device *rdev, struct radeon_ring *ring); bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, uint32_t **data); int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, unsigned size, uint32_t *data); int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, unsigned rptr_offs, u32 nop); void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); /* r600 async dma */ void r600_dma_stop(struct radeon_device *rdev); int r600_dma_resume(struct radeon_device *rdev); void r600_dma_fini(struct radeon_device *rdev); void cayman_dma_stop(struct radeon_device *rdev); int cayman_dma_resume(struct radeon_device *rdev); void cayman_dma_fini(struct radeon_device *rdev); /* * CS. */ struct radeon_cs_chunk { … }; struct radeon_cs_parser { … }; static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) { … } struct radeon_cs_packet { … }; radeon_packet0_check_t; /* * AGP */ struct radeon_agp_mode { … }; struct radeon_agp_info { … }; struct radeon_agp_head { … }; #if IS_ENABLED(CONFIG_AGP) struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev); #else static inline struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev) { return NULL; } #endif int radeon_agp_init(struct radeon_device *rdev); void radeon_agp_resume(struct radeon_device *rdev); void radeon_agp_suspend(struct radeon_device *rdev); void radeon_agp_fini(struct radeon_device *rdev); /* * Writeback */ struct radeon_wb { … }; #define RADEON_WB_SCRATCH_OFFSET … #define RADEON_WB_RING0_NEXT_RPTR … #define RADEON_WB_CP_RPTR_OFFSET … #define RADEON_WB_CP1_RPTR_OFFSET … #define RADEON_WB_CP2_RPTR_OFFSET … #define R600_WB_DMA_RPTR_OFFSET … #define R600_WB_IH_WPTR_OFFSET … #define CAYMAN_WB_DMA1_RPTR_OFFSET … #define R600_WB_EVENT_OFFSET … #define CIK_WB_CP1_WPTR_OFFSET … #define CIK_WB_CP2_WPTR_OFFSET … #define R600_WB_DMA_RING_TEST_OFFSET … #define CAYMAN_WB_DMA1_RING_TEST_OFFSET … /** * struct radeon_pm - power management datas * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) * @sclk: GPU clock Mhz (core bandwidth depends of this clock) * @needed_bandwidth: current bandwidth needs * * It keeps track of various data needed to take powermanagement decision. * Bandwidth need is used to determine minimun clock of the GPU and memory. * Equation between gpu/memory clock and available bandwidth is hw dependent * (type of memory, bus size, efficiency, ...) */ enum radeon_pm_method { … }; enum radeon_dynpm_state { … }; enum radeon_dynpm_action { … }; enum radeon_voltage_type { … }; enum radeon_pm_state_type { … }; enum radeon_pm_profile_type { … }; #define PM_PROFILE_DEFAULT_IDX … #define PM_PROFILE_LOW_SH_IDX … #define PM_PROFILE_MID_SH_IDX … #define PM_PROFILE_HIGH_SH_IDX … #define PM_PROFILE_LOW_MH_IDX … #define PM_PROFILE_MID_MH_IDX … #define PM_PROFILE_HIGH_MH_IDX … #define PM_PROFILE_MAX … struct radeon_pm_profile { … }; enum radeon_int_thermal_type { … }; struct radeon_voltage { … }; /* clock mode flags */ #define RADEON_PM_MODE_NO_DISPLAY … struct radeon_pm_clock_info { … }; /* state flags */ #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY … struct radeon_power_state { … }; /* * Some modes are overclocked by very low value, accept them */ #define RADEON_MODE_OVERCLOCK_MARGIN … enum radeon_dpm_auto_throttle_src { … }; enum radeon_dpm_event_src { … }; #define RADEON_MAX_VCE_LEVELS … enum radeon_vce_level { … }; struct radeon_ps { … }; struct radeon_dpm_thermal { … }; enum radeon_clk_action { … }; struct radeon_blacklist_clocks { … }; struct radeon_clock_and_voltage_limits { … }; struct radeon_clock_array { … }; struct radeon_clock_voltage_dependency_entry { … }; struct radeon_clock_voltage_dependency_table { … }; radeon_cac_leakage_entry; struct radeon_cac_leakage_table { … }; struct radeon_phase_shedding_limits_entry { … }; struct radeon_phase_shedding_limits_table { … }; struct radeon_uvd_clock_voltage_dependency_entry { … }; struct radeon_uvd_clock_voltage_dependency_table { … }; struct radeon_vce_clock_voltage_dependency_entry { … }; struct radeon_vce_clock_voltage_dependency_table { … }; struct radeon_ppm_table { … }; struct radeon_cac_tdp_table { … }; struct radeon_dpm_dynamic_state { … }; struct radeon_dpm_fan { … }; enum radeon_pcie_gen { … }; enum radeon_dpm_forced_level { … }; struct radeon_vce_state { … }; struct radeon_dpm { … }; void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); struct radeon_pm { … }; #define RADEON_PCIE_SPEED_25 … #define RADEON_PCIE_SPEED_50 … #define RADEON_PCIE_SPEED_80 … int radeon_pm_get_type_index(struct radeon_device *rdev, enum radeon_pm_state_type ps_type, int instance); /* * UVD */ #define RADEON_DEFAULT_UVD_HANDLES … #define RADEON_MAX_UVD_HANDLES … #define RADEON_UVD_STACK_SIZE … #define RADEON_UVD_HEAP_SIZE … #define RADEON_UVD_SESSION_SIZE … struct radeon_uvd { … }; int radeon_uvd_init(struct radeon_device *rdev); void radeon_uvd_fini(struct radeon_device *rdev); int radeon_uvd_suspend(struct radeon_device *rdev); int radeon_uvd_resume(struct radeon_device *rdev); int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, uint32_t handle, struct radeon_fence **fence); int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, uint32_t handle, struct radeon_fence **fence); void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, uint32_t allowed_domains); void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp); int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); void radeon_uvd_note_usage(struct radeon_device *rdev); int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, unsigned vclk, unsigned dclk, unsigned vco_min, unsigned vco_max, unsigned fb_factor, unsigned fb_mask, unsigned pd_min, unsigned pd_max, unsigned pd_even, unsigned *optimal_fb_div, unsigned *optimal_vclk_div, unsigned *optimal_dclk_div); int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, unsigned cg_upll_func_cntl); /* * VCE */ #define RADEON_MAX_VCE_HANDLES … struct radeon_vce { … }; int radeon_vce_init(struct radeon_device *rdev); void radeon_vce_fini(struct radeon_device *rdev); int radeon_vce_suspend(struct radeon_device *rdev); int radeon_vce_resume(struct radeon_device *rdev); int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, uint32_t handle, struct radeon_fence **fence); int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, uint32_t handle, struct radeon_fence **fence); void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); void radeon_vce_note_usage(struct radeon_device *rdev); int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); int radeon_vce_cs_parse(struct radeon_cs_parser *p); bool radeon_vce_semaphore_emit(struct radeon_device *rdev, struct radeon_ring *ring, struct radeon_semaphore *semaphore, bool emit_wait); void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); void radeon_vce_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); struct r600_audio_pin { … }; struct r600_audio { … }; /* * Benchmarking */ void radeon_benchmark(struct radeon_device *rdev, int test_number); /* * Testing */ void radeon_test_moves(struct radeon_device *rdev); void radeon_test_ring_sync(struct radeon_device *rdev, struct radeon_ring *cpA, struct radeon_ring *cpB); void radeon_test_syncing(struct radeon_device *rdev); /* * MMU Notifier */ #if defined(CONFIG_MMU_NOTIFIER) int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); void radeon_mn_unregister(struct radeon_bo *bo); #else static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr) { return -ENODEV; } static inline void radeon_mn_unregister(struct radeon_bo *bo) {} #endif /* * Debugfs */ void radeon_debugfs_fence_init(struct radeon_device *rdev); void radeon_gem_debugfs_init(struct radeon_device *rdev); /* * ASIC ring specific functions. */ struct radeon_asic_ring { … }; /* * ASIC specific functions. */ struct radeon_asic { … }; /* * Asic structures */ struct r100_asic { … }; struct r300_asic { … }; struct r600_asic { … }; struct rv770_asic { … }; struct evergreen_asic { … }; struct cayman_asic { … }; struct si_asic { … }; struct cik_asic { … }; radeon_asic_config; /* * asic initizalization from radeon_asic.c */ void radeon_agp_disable(struct radeon_device *rdev); int radeon_asic_init(struct radeon_device *rdev); /* * IOCTL. */ int radeon_gem_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_gem_create_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_gem_va_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_gem_op_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); /* VRAM scratch page for HDP bug, default vram page */ struct r600_vram_scratch { … }; /* * ACPI */ struct radeon_atif_notification_cfg { … }; struct radeon_atif_notifications { … }; struct radeon_atif_functions { … }; struct radeon_atif { … }; struct radeon_atcs_functions { … }; struct radeon_atcs { … }; /* * Core structure, functions and helpers. */ radeon_rreg_t; radeon_wreg_t; struct radeon_device { … }; bool radeon_is_px(struct drm_device *dev); int radeon_device_init(struct radeon_device *rdev, struct drm_device *ddev, struct pci_dev *pdev, uint32_t flags); void radeon_device_fini(struct radeon_device *rdev); int radeon_gpu_wait_for_idle(struct radeon_device *rdev); #define RADEON_MIN_MMIO_SIZE … uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, bool always_indirect) { … } static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, bool always_indirect) { … } u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); /* * Cast helper */ extern const struct dma_fence_ops radeon_fence_ops; static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f) { … } /* * Registers read & write functions. */ #define RREG8(reg) … #define WREG8(reg, v) … #define RREG16(reg) … #define WREG16(reg, v) … #define RREG32(reg) … #define RREG32_IDX(reg) … #define DREG32(reg) … #define WREG32(reg, v) … #define WREG32_IDX(reg, v) … #define REG_SET(FIELD, v) … #define REG_GET(FIELD, v) … #define RREG32_PLL(reg) … #define WREG32_PLL(reg, v) … #define RREG32_MC(reg) … #define WREG32_MC(reg, v) … #define RREG32_PCIE(reg) … #define WREG32_PCIE(reg, v) … #define RREG32_PCIE_PORT(reg) … #define WREG32_PCIE_PORT(reg, v) … #define RREG32_SMC(reg) … #define WREG32_SMC(reg, v) … #define RREG32_RCU(reg) … #define WREG32_RCU(reg, v) … #define RREG32_CG(reg) … #define WREG32_CG(reg, v) … #define RREG32_PIF_PHY0(reg) … #define WREG32_PIF_PHY0(reg, v) … #define RREG32_PIF_PHY1(reg) … #define WREG32_PIF_PHY1(reg, v) … #define RREG32_UVD_CTX(reg) … #define WREG32_UVD_CTX(reg, v) … #define RREG32_DIDT(reg) … #define WREG32_DIDT(reg, v) … #define WREG32_P(reg, val, mask) … #define WREG32_AND(reg, and) … #define WREG32_OR(reg, or) … #define WREG32_PLL_P(reg, val, mask) … #define WREG32_SMC_P(reg, val, mask) … #define DREG32_SYS(sqf, rdev, reg) … #define RREG32_IO(reg) … #define WREG32_IO(reg, v) … #define RDOORBELL32(index) … #define WDOORBELL32(index, v) … /* * Indirect registers accessors. * They used to be inlined, but this increases code size by ~65 kbytes. * Since each performs a pair of MMIO ops * within a spin_lock_irqsave/spin_unlock_irqrestore region, * the cost of call+ret is almost negligible. MMIO and locking * costs several dozens of cycles each at best, call+ret is ~5 cycles. */ uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); void r100_pll_errata_after_index(struct radeon_device *rdev); /* * ASICs helpers. */ #define ASIC_IS_RN50(rdev) … #define ASIC_IS_RV100(rdev) … #define ASIC_IS_R300(rdev) … #define ASIC_IS_X2(rdev) … #define ASIC_IS_AVIVO(rdev) … #define ASIC_IS_DCE2(rdev) … #define ASIC_IS_DCE3(rdev) … #define ASIC_IS_DCE32(rdev) … #define ASIC_IS_DCE4(rdev) … #define ASIC_IS_DCE41(rdev) … #define ASIC_IS_DCE5(rdev) … #define ASIC_IS_DCE6(rdev) … #define ASIC_IS_DCE61(rdev) … #define ASIC_IS_DCE64(rdev) … #define ASIC_IS_NODCE(rdev) … #define ASIC_IS_DCE8(rdev) … #define ASIC_IS_DCE81(rdev) … #define ASIC_IS_DCE82(rdev) … #define ASIC_IS_DCE83(rdev) … #define ASIC_IS_LOMBOK(rdev) … /* * BIOS helpers. */ #define RBIOS8(i) … #define RBIOS16(i) … #define RBIOS32(i) … int radeon_combios_init(struct radeon_device *rdev); void radeon_combios_fini(struct radeon_device *rdev); int radeon_atombios_init(struct radeon_device *rdev); void radeon_atombios_fini(struct radeon_device *rdev); /* * RING helpers. */ /** * radeon_ring_write - write a value to the ring * * @ring: radeon_ring structure holding ring information * @v: dword (dw) value to write * * Write a value to the requested ring buffer (all asics). */ static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) { … } /* * ASICs macro. */ #define radeon_init(rdev) … #define radeon_fini(rdev) … #define radeon_resume(rdev) … #define radeon_suspend(rdev) … #define radeon_cs_parse(rdev, r, p) … #define radeon_vga_set_state(rdev, state) … #define radeon_asic_reset(rdev) … #define radeon_gart_tlb_flush(rdev) … #define radeon_gart_get_page_entry(a, f) … #define radeon_gart_set_page(rdev, i, e) … #define radeon_asic_vm_init(rdev) … #define radeon_asic_vm_fini(rdev) … #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) … #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) … #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) … #define radeon_asic_vm_pad_ib(rdev, ib) … #define radeon_ring_start(rdev, r, cp) … #define radeon_ring_test(rdev, r, cp) … #define radeon_ib_test(rdev, r, cp) … #define radeon_ring_ib_execute(rdev, r, ib) … #define radeon_ring_ib_parse(rdev, r, ib) … #define radeon_ring_is_lockup(rdev, r, cp) … #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) … #define radeon_ring_get_rptr(rdev, r) … #define radeon_ring_get_wptr(rdev, r) … #define radeon_ring_set_wptr(rdev, r) … #define radeon_irq_set(rdev) … #define radeon_irq_process(rdev) … #define radeon_get_vblank_counter(rdev, crtc) … #define radeon_set_backlight_level(rdev, e, l) … #define radeon_get_backlight_level(rdev, e) … #define radeon_hdmi_enable(rdev, e, b) … #define radeon_hdmi_setmode(rdev, e, m) … #define radeon_fence_ring_emit(rdev, r, fence) … #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) … #define radeon_copy_blit(rdev, s, d, np, resv) … #define radeon_copy_dma(rdev, s, d, np, resv) … #define radeon_copy(rdev, s, d, np, resv) … #define radeon_copy_blit_ring_index(rdev) … #define radeon_copy_dma_ring_index(rdev) … #define radeon_copy_ring_index(rdev) … #define radeon_get_engine_clock(rdev) … #define radeon_set_engine_clock(rdev, e) … #define radeon_get_memory_clock(rdev) … #define radeon_set_memory_clock(rdev, e) … #define radeon_get_pcie_lanes(rdev) … #define radeon_set_pcie_lanes(rdev, l) … #define radeon_set_clock_gating(rdev, e) … #define radeon_set_uvd_clocks(rdev, v, d) … #define radeon_set_vce_clocks(rdev, ev, ec) … #define radeon_get_temperature(rdev) … #define radeon_set_surface_reg(rdev, r, f, p, o, s) … #define radeon_clear_surface_reg(rdev, r) … #define radeon_bandwidth_update(rdev) … #define radeon_hpd_init(rdev) … #define radeon_hpd_fini(rdev) … #define radeon_hpd_sense(rdev, h) … #define radeon_hpd_set_polarity(rdev, h) … #define radeon_gui_idle(rdev) … #define radeon_pm_misc(rdev) … #define radeon_pm_prepare(rdev) … #define radeon_pm_finish(rdev) … #define radeon_pm_init_profile(rdev) … #define radeon_pm_get_dynpm_state(rdev) … #define radeon_page_flip(rdev, crtc, base, async) … #define radeon_page_flip_pending(rdev, crtc) … #define radeon_wait_for_vblank(rdev, crtc) … #define radeon_mc_wait_for_idle(rdev) … #define radeon_get_xclk(rdev) … #define radeon_get_gpu_clock_counter(rdev) … #define radeon_get_allowed_info_register(rdev, r, v) … #define radeon_dpm_init(rdev) … #define radeon_dpm_setup_asic(rdev) … #define radeon_dpm_enable(rdev) … #define radeon_dpm_late_enable(rdev) … #define radeon_dpm_disable(rdev) … #define radeon_dpm_pre_set_power_state(rdev) … #define radeon_dpm_set_power_state(rdev) … #define radeon_dpm_post_set_power_state(rdev) … #define radeon_dpm_display_configuration_changed(rdev) … #define radeon_dpm_fini(rdev) … #define radeon_dpm_get_sclk(rdev, l) … #define radeon_dpm_get_mclk(rdev, l) … #define radeon_dpm_print_power_state(rdev, ps) … #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) … #define radeon_dpm_force_performance_level(rdev, l) … #define radeon_dpm_vblank_too_short(rdev) … #define radeon_dpm_powergate_uvd(rdev, g) … #define radeon_dpm_enable_bapm(rdev, e) … #define radeon_dpm_get_current_sclk(rdev) … #define radeon_dpm_get_current_mclk(rdev) … /* Common functions */ /* AGP */ extern int radeon_gpu_reset(struct radeon_device *rdev); extern void radeon_pci_config_reset(struct radeon_device *rdev); extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); extern void radeon_agp_disable(struct radeon_device *rdev); extern int radeon_modeset_init(struct radeon_device *rdev); extern void radeon_modeset_fini(struct radeon_device *rdev); extern bool radeon_card_posted(struct radeon_device *rdev); extern void radeon_update_bandwidth_info(struct radeon_device *rdev); extern void radeon_update_display_priority(struct radeon_device *rdev); extern bool radeon_boot_test_post_card(struct radeon_device *rdev); extern void radeon_scratch_init(struct radeon_device *rdev); extern void radeon_wb_fini(struct radeon_device *rdev); extern int radeon_wb_init(struct radeon_device *rdev); extern void radeon_wb_disable(struct radeon_device *rdev); extern void radeon_surface_init(struct radeon_device *rdev); extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); extern int radeon_ttm_tt_set_userptr(struct radeon_device *rdev, struct ttm_tt *ttm, uint64_t addr, uint32_t flags); extern bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev, struct ttm_tt *ttm); extern bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev, struct ttm_tt *ttm); bool radeon_ttm_tt_is_bound(struct ttm_device *bdev, struct ttm_tt *ttm); extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon, bool freeze); extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); extern void radeon_program_register_sequence(struct radeon_device *rdev, const u32 *registers, const u32 array_size); struct radeon_device *radeon_get_rdev(struct ttm_device *bdev); /* KMS */ u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc); int radeon_enable_vblank_kms(struct drm_crtc *crtc); void radeon_disable_vblank_kms(struct drm_crtc *crtc); /* * vm */ int radeon_vm_manager_init(struct radeon_device *rdev); void radeon_vm_manager_fini(struct radeon_device *rdev); int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, struct radeon_vm *vm, struct list_head *head); struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, struct radeon_vm *vm, int ring); void radeon_vm_flush(struct radeon_device *rdev, struct radeon_vm *vm, int ring, struct radeon_fence *fence); void radeon_vm_fence(struct radeon_device *rdev, struct radeon_vm *vm, struct radeon_fence *fence); uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); int radeon_vm_update_page_directory(struct radeon_device *rdev, struct radeon_vm *vm); int radeon_vm_clear_freed(struct radeon_device *rdev, struct radeon_vm *vm); int radeon_vm_clear_invalids(struct radeon_device *rdev, struct radeon_vm *vm); int radeon_vm_bo_update(struct radeon_device *rdev, struct radeon_bo_va *bo_va, struct ttm_resource *mem); void radeon_vm_bo_invalidate(struct radeon_device *rdev, struct radeon_bo *bo); struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, struct radeon_bo *bo); struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, struct radeon_vm *vm, struct radeon_bo *bo); int radeon_vm_bo_set_addr(struct radeon_device *rdev, struct radeon_bo_va *bo_va, uint64_t offset, uint32_t flags); void radeon_vm_bo_rmv(struct radeon_device *rdev, struct radeon_bo_va *bo_va); /* audio */ void r600_audio_update_hdmi(struct work_struct *work); struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); void r600_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin, u8 enable_mask); void dce6_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin, u8 enable_mask); /* * R600 vram scratch functions */ int r600_vram_scratch_init(struct radeon_device *rdev); void r600_vram_scratch_fini(struct radeon_device *rdev); /* * r600 cs checking helper */ unsigned r600_mip_minify(unsigned size, unsigned level); bool r600_fmt_is_valid_color(u32 format); bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); int r600_fmt_get_blocksize(u32 format); int r600_fmt_get_nblocksx(u32 format, u32 w); int r600_fmt_get_nblocksy(u32 format, u32 h); /* * r600 functions used by radeon_encoder.c */ struct radeon_hdmi_acr { … }; extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, u32 tiling_pipe_num, u32 max_rb_num, u32 total_max_rb_num, u32 enabled_rb_mask); /* * evergreen functions used by radeon_encoder.c */ extern int ni_init_microcode(struct radeon_device *rdev); extern int ni_mc_load_microcode(struct radeon_device *rdev); /* radeon_acpi.c */ #if defined(CONFIG_ACPI) extern int radeon_acpi_init(struct radeon_device *rdev); extern void radeon_acpi_fini(struct radeon_device *rdev); extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, u8 perf_req, bool advertise); extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); #else static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } static inline void radeon_acpi_fini(struct radeon_device *rdev) { } #endif int radeon_cs_packet_parse(struct radeon_cs_parser *p, struct radeon_cs_packet *pkt, unsigned idx); bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); void radeon_cs_dump_packet(struct radeon_cs_parser *p, struct radeon_cs_packet *pkt); int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, struct radeon_bo_list **cs_reloc, int nomm); int r600_cs_common_vline_parse(struct radeon_cs_parser *p, uint32_t *vline_start_end, uint32_t *vline_status); /* interrupt control register helpers */ void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev, u32 reg, u32 mask, bool enable, const char *name, unsigned n); /* Audio component binding */ void radeon_audio_component_init(struct radeon_device *rdev); void radeon_audio_component_fini(struct radeon_device *rdev); #include "radeon_object.h" #endif
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