linux/drivers/gpu/drm/radeon/rs600d.h

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#ifndef __RS600D_H__
#define __RS600D_H__

/* Registers */
#define R_000040_GEN_INT_CNTL
#define S_000040_SCRATCH_INT_MASK(x)
#define G_000040_SCRATCH_INT_MASK(x)
#define C_000040_SCRATCH_INT_MASK
#define S_000040_GUI_IDLE_MASK(x)
#define G_000040_GUI_IDLE_MASK(x)
#define C_000040_GUI_IDLE_MASK
#define S_000040_DMA_VIPH1_INT_EN(x)
#define G_000040_DMA_VIPH1_INT_EN(x)
#define C_000040_DMA_VIPH1_INT_EN
#define S_000040_DMA_VIPH2_INT_EN(x)
#define G_000040_DMA_VIPH2_INT_EN(x)
#define C_000040_DMA_VIPH2_INT_EN
#define S_000040_DMA_VIPH3_INT_EN(x)
#define G_000040_DMA_VIPH3_INT_EN(x)
#define C_000040_DMA_VIPH3_INT_EN
#define S_000040_I2C_INT_EN(x)
#define G_000040_I2C_INT_EN(x)
#define C_000040_I2C_INT_EN
#define S_000040_GUI_IDLE(x)
#define G_000040_GUI_IDLE(x)
#define C_000040_GUI_IDLE
#define S_000040_VIPH_INT_EN(x)
#define G_000040_VIPH_INT_EN(x)
#define C_000040_VIPH_INT_EN
#define S_000040_SW_INT_EN(x)
#define G_000040_SW_INT_EN(x)
#define C_000040_SW_INT_EN
#define S_000040_GEYSERVILLE(x)
#define G_000040_GEYSERVILLE(x)
#define C_000040_GEYSERVILLE
#define S_000040_HDCP_AUTHORIZED_INT(x)
#define G_000040_HDCP_AUTHORIZED_INT(x)
#define C_000040_HDCP_AUTHORIZED_INT
#define S_000040_DVI_I2C_INT(x)
#define G_000040_DVI_I2C_INT(x)
#define C_000040_DVI_I2C_INT
#define S_000040_GUIDMA(x)
#define G_000040_GUIDMA(x)
#define C_000040_GUIDMA
#define S_000040_VIDDMA(x)
#define G_000040_VIDDMA(x)
#define C_000040_VIDDMA
#define R_000044_GEN_INT_STATUS
#define S_000044_DISPLAY_INT_STAT(x)
#define G_000044_DISPLAY_INT_STAT(x)
#define C_000044_DISPLAY_INT_STAT
#define S_000044_VGA_INT_STAT(x)
#define G_000044_VGA_INT_STAT(x)
#define C_000044_VGA_INT_STAT
#define S_000044_CAP0_INT_ACTIVE(x)
#define G_000044_CAP0_INT_ACTIVE(x)
#define C_000044_CAP0_INT_ACTIVE
#define S_000044_DMA_VIPH0_INT(x)
#define G_000044_DMA_VIPH0_INT(x)
#define C_000044_DMA_VIPH0_INT
#define S_000044_DMA_VIPH1_INT(x)
#define G_000044_DMA_VIPH1_INT(x)
#define C_000044_DMA_VIPH1_INT
#define S_000044_DMA_VIPH2_INT(x)
#define G_000044_DMA_VIPH2_INT(x)
#define C_000044_DMA_VIPH2_INT
#define S_000044_DMA_VIPH3_INT(x)
#define G_000044_DMA_VIPH3_INT(x)
#define C_000044_DMA_VIPH3_INT
#define S_000044_MC_PROBE_FAULT_STAT(x)
#define G_000044_MC_PROBE_FAULT_STAT(x)
#define C_000044_MC_PROBE_FAULT_STAT
#define S_000044_I2C_INT(x)
#define G_000044_I2C_INT(x)
#define C_000044_I2C_INT
#define S_000044_SCRATCH_INT_STAT(x)
#define G_000044_SCRATCH_INT_STAT(x)
#define C_000044_SCRATCH_INT_STAT
#define S_000044_GUI_IDLE_STAT(x)
#define G_000044_GUI_IDLE_STAT(x)
#define C_000044_GUI_IDLE_STAT
#define S_000044_ATI_OVERDRIVE_INT_STAT(x)
#define G_000044_ATI_OVERDRIVE_INT_STAT(x)
#define C_000044_ATI_OVERDRIVE_INT_STAT
#define S_000044_MC_PROTECTION_FAULT_STAT(x)
#define G_000044_MC_PROTECTION_FAULT_STAT(x)
#define C_000044_MC_PROTECTION_FAULT_STAT
#define S_000044_RBBM_READ_INT_STAT(x)
#define G_000044_RBBM_READ_INT_STAT(x)
#define C_000044_RBBM_READ_INT_STAT
#define S_000044_CB_CONTEXT_SWITCH_STAT(x)
#define G_000044_CB_CONTEXT_SWITCH_STAT(x)
#define C_000044_CB_CONTEXT_SWITCH_STAT
#define S_000044_VIPH_INT(x)
#define G_000044_VIPH_INT(x)
#define C_000044_VIPH_INT
#define S_000044_SW_INT(x)
#define G_000044_SW_INT(x)
#define C_000044_SW_INT
#define S_000044_SW_INT_SET(x)
#define G_000044_SW_INT_SET(x)
#define C_000044_SW_INT_SET
#define S_000044_IDCT_INT_STAT(x)
#define G_000044_IDCT_INT_STAT(x)
#define C_000044_IDCT_INT_STAT
#define S_000044_GUIDMA_STAT(x)
#define G_000044_GUIDMA_STAT(x)
#define C_000044_GUIDMA_STAT
#define S_000044_VIDDMA_STAT(x)
#define G_000044_VIDDMA_STAT(x)
#define C_000044_VIDDMA_STAT
#define R_00004C_BUS_CNTL
#define S_00004C_BUS_MASTER_DIS(x)
#define G_00004C_BUS_MASTER_DIS(x)
#define C_00004C_BUS_MASTER_DIS
#define S_00004C_BUS_MSI_REARM(x)
#define G_00004C_BUS_MSI_REARM(x)
#define C_00004C_BUS_MSI_REARM
#define R_000070_MC_IND_INDEX
#define S_000070_MC_IND_ADDR(x)
#define G_000070_MC_IND_ADDR(x)
#define C_000070_MC_IND_ADDR
#define S_000070_MC_IND_SEQ_RBS_0(x)
#define G_000070_MC_IND_SEQ_RBS_0(x)
#define C_000070_MC_IND_SEQ_RBS_0
#define S_000070_MC_IND_SEQ_RBS_1(x)
#define G_000070_MC_IND_SEQ_RBS_1(x)
#define C_000070_MC_IND_SEQ_RBS_1
#define S_000070_MC_IND_SEQ_RBS_2(x)
#define G_000070_MC_IND_SEQ_RBS_2(x)
#define C_000070_MC_IND_SEQ_RBS_2
#define S_000070_MC_IND_SEQ_RBS_3(x)
#define G_000070_MC_IND_SEQ_RBS_3(x)
#define C_000070_MC_IND_SEQ_RBS_3
#define S_000070_MC_IND_AIC_RBS(x)
#define G_000070_MC_IND_AIC_RBS(x)
#define C_000070_MC_IND_AIC_RBS
#define S_000070_MC_IND_CITF_ARB0(x)
#define G_000070_MC_IND_CITF_ARB0(x)
#define C_000070_MC_IND_CITF_ARB0
#define S_000070_MC_IND_CITF_ARB1(x)
#define G_000070_MC_IND_CITF_ARB1(x)
#define C_000070_MC_IND_CITF_ARB1
#define S_000070_MC_IND_WR_EN(x)
#define G_000070_MC_IND_WR_EN(x)
#define C_000070_MC_IND_WR_EN
#define S_000070_MC_IND_RD_INV(x)
#define G_000070_MC_IND_RD_INV(x)
#define C_000070_MC_IND_RD_INV
#define R_000074_MC_IND_DATA
#define S_000074_MC_IND_DATA(x)
#define G_000074_MC_IND_DATA(x)
#define C_000074_MC_IND_DATA
#define R_0000F0_RBBM_SOFT_RESET
#define S_0000F0_SOFT_RESET_CP(x)
#define G_0000F0_SOFT_RESET_CP(x)
#define C_0000F0_SOFT_RESET_CP
#define S_0000F0_SOFT_RESET_HI(x)
#define G_0000F0_SOFT_RESET_HI(x)
#define C_0000F0_SOFT_RESET_HI
#define S_0000F0_SOFT_RESET_VAP(x)
#define G_0000F0_SOFT_RESET_VAP(x)
#define C_0000F0_SOFT_RESET_VAP
#define S_0000F0_SOFT_RESET_RE(x)
#define G_0000F0_SOFT_RESET_RE(x)
#define C_0000F0_SOFT_RESET_RE
#define S_0000F0_SOFT_RESET_PP(x)
#define G_0000F0_SOFT_RESET_PP(x)
#define C_0000F0_SOFT_RESET_PP
#define S_0000F0_SOFT_RESET_E2(x)
#define G_0000F0_SOFT_RESET_E2(x)
#define C_0000F0_SOFT_RESET_E2
#define S_0000F0_SOFT_RESET_RB(x)
#define G_0000F0_SOFT_RESET_RB(x)
#define C_0000F0_SOFT_RESET_RB
#define S_0000F0_SOFT_RESET_HDP(x)
#define G_0000F0_SOFT_RESET_HDP(x)
#define C_0000F0_SOFT_RESET_HDP
#define S_0000F0_SOFT_RESET_MC(x)
#define G_0000F0_SOFT_RESET_MC(x)
#define C_0000F0_SOFT_RESET_MC
#define S_0000F0_SOFT_RESET_AIC(x)
#define G_0000F0_SOFT_RESET_AIC(x)
#define C_0000F0_SOFT_RESET_AIC
#define S_0000F0_SOFT_RESET_VIP(x)
#define G_0000F0_SOFT_RESET_VIP(x)
#define C_0000F0_SOFT_RESET_VIP
#define S_0000F0_SOFT_RESET_DISP(x)
#define G_0000F0_SOFT_RESET_DISP(x)
#define C_0000F0_SOFT_RESET_DISP
#define S_0000F0_SOFT_RESET_CG(x)
#define G_0000F0_SOFT_RESET_CG(x)
#define C_0000F0_SOFT_RESET_CG
#define S_0000F0_SOFT_RESET_GA(x)
#define G_0000F0_SOFT_RESET_GA(x)
#define C_0000F0_SOFT_RESET_GA
#define S_0000F0_SOFT_RESET_IDCT(x)
#define G_0000F0_SOFT_RESET_IDCT(x)
#define C_0000F0_SOFT_RESET_IDCT
#define R_000134_HDP_FB_LOCATION
#define S_000134_HDP_FB_START(x)
#define G_000134_HDP_FB_START(x)
#define C_000134_HDP_FB_START
#define R_0007C0_CP_STAT
#define S_0007C0_MRU_BUSY(x)
#define G_0007C0_MRU_BUSY(x)
#define C_0007C0_MRU_BUSY
#define S_0007C0_MWU_BUSY(x)
#define G_0007C0_MWU_BUSY(x)
#define C_0007C0_MWU_BUSY
#define S_0007C0_RSIU_BUSY(x)
#define G_0007C0_RSIU_BUSY(x)
#define C_0007C0_RSIU_BUSY
#define S_0007C0_RCIU_BUSY(x)
#define G_0007C0_RCIU_BUSY(x)
#define C_0007C0_RCIU_BUSY
#define S_0007C0_CSF_PRIMARY_BUSY(x)
#define G_0007C0_CSF_PRIMARY_BUSY(x)
#define C_0007C0_CSF_PRIMARY_BUSY
#define S_0007C0_CSF_INDIRECT_BUSY(x)
#define G_0007C0_CSF_INDIRECT_BUSY(x)
#define C_0007C0_CSF_INDIRECT_BUSY
#define S_0007C0_CSQ_PRIMARY_BUSY(x)
#define G_0007C0_CSQ_PRIMARY_BUSY(x)
#define C_0007C0_CSQ_PRIMARY_BUSY
#define S_0007C0_CSQ_INDIRECT_BUSY(x)
#define G_0007C0_CSQ_INDIRECT_BUSY(x)
#define C_0007C0_CSQ_INDIRECT_BUSY
#define S_0007C0_CSI_BUSY(x)
#define G_0007C0_CSI_BUSY(x)
#define C_0007C0_CSI_BUSY
#define S_0007C0_CSF_INDIRECT2_BUSY(x)
#define G_0007C0_CSF_INDIRECT2_BUSY(x)
#define C_0007C0_CSF_INDIRECT2_BUSY
#define S_0007C0_CSQ_INDIRECT2_BUSY(x)
#define G_0007C0_CSQ_INDIRECT2_BUSY(x)
#define C_0007C0_CSQ_INDIRECT2_BUSY
#define S_0007C0_GUIDMA_BUSY(x)
#define G_0007C0_GUIDMA_BUSY(x)
#define C_0007C0_GUIDMA_BUSY
#define S_0007C0_VIDDMA_BUSY(x)
#define G_0007C0_VIDDMA_BUSY(x)
#define C_0007C0_VIDDMA_BUSY
#define S_0007C0_CMDSTRM_BUSY(x)
#define G_0007C0_CMDSTRM_BUSY(x)
#define C_0007C0_CMDSTRM_BUSY
#define S_0007C0_CP_BUSY(x)
#define G_0007C0_CP_BUSY(x)
#define C_0007C0_CP_BUSY
#define R_000E40_RBBM_STATUS
#define S_000E40_CMDFIFO_AVAIL(x)
#define G_000E40_CMDFIFO_AVAIL(x)
#define C_000E40_CMDFIFO_AVAIL
#define S_000E40_HIRQ_ON_RBB(x)
#define G_000E40_HIRQ_ON_RBB(x)
#define C_000E40_HIRQ_ON_RBB
#define S_000E40_CPRQ_ON_RBB(x)
#define G_000E40_CPRQ_ON_RBB(x)
#define C_000E40_CPRQ_ON_RBB
#define S_000E40_CFRQ_ON_RBB(x)
#define G_000E40_CFRQ_ON_RBB(x)
#define C_000E40_CFRQ_ON_RBB
#define S_000E40_HIRQ_IN_RTBUF(x)
#define G_000E40_HIRQ_IN_RTBUF(x)
#define C_000E40_HIRQ_IN_RTBUF
#define S_000E40_CPRQ_IN_RTBUF(x)
#define G_000E40_CPRQ_IN_RTBUF(x)
#define C_000E40_CPRQ_IN_RTBUF
#define S_000E40_CFRQ_IN_RTBUF(x)
#define G_000E40_CFRQ_IN_RTBUF(x)
#define C_000E40_CFRQ_IN_RTBUF
#define S_000E40_CF_PIPE_BUSY(x)
#define G_000E40_CF_PIPE_BUSY(x)
#define C_000E40_CF_PIPE_BUSY
#define S_000E40_ENG_EV_BUSY(x)
#define G_000E40_ENG_EV_BUSY(x)
#define C_000E40_ENG_EV_BUSY
#define S_000E40_CP_CMDSTRM_BUSY(x)
#define G_000E40_CP_CMDSTRM_BUSY(x)
#define C_000E40_CP_CMDSTRM_BUSY
#define S_000E40_E2_BUSY(x)
#define G_000E40_E2_BUSY(x)
#define C_000E40_E2_BUSY
#define S_000E40_RB2D_BUSY(x)
#define G_000E40_RB2D_BUSY(x)
#define C_000E40_RB2D_BUSY
#define S_000E40_RB3D_BUSY(x)
#define G_000E40_RB3D_BUSY(x)
#define C_000E40_RB3D_BUSY
#define S_000E40_VAP_BUSY(x)
#define G_000E40_VAP_BUSY(x)
#define C_000E40_VAP_BUSY
#define S_000E40_RE_BUSY(x)
#define G_000E40_RE_BUSY(x)
#define C_000E40_RE_BUSY
#define S_000E40_TAM_BUSY(x)
#define G_000E40_TAM_BUSY(x)
#define C_000E40_TAM_BUSY
#define S_000E40_TDM_BUSY(x)
#define G_000E40_TDM_BUSY(x)
#define C_000E40_TDM_BUSY
#define S_000E40_PB_BUSY(x)
#define G_000E40_PB_BUSY(x)
#define C_000E40_PB_BUSY
#define S_000E40_TIM_BUSY(x)
#define G_000E40_TIM_BUSY(x)
#define C_000E40_TIM_BUSY
#define S_000E40_GA_BUSY(x)
#define G_000E40_GA_BUSY(x)
#define C_000E40_GA_BUSY
#define S_000E40_CBA2D_BUSY(x)
#define G_000E40_CBA2D_BUSY(x)
#define C_000E40_CBA2D_BUSY
#define S_000E40_GUI_ACTIVE(x)
#define G_000E40_GUI_ACTIVE(x)
#define C_000E40_GUI_ACTIVE
#define R_0060A4_D1CRTC_STATUS_FRAME_COUNT
#define S_0060A4_D1CRTC_FRAME_COUNT(x)
#define G_0060A4_D1CRTC_FRAME_COUNT(x)
#define C_0060A4_D1CRTC_FRAME_COUNT
#define R_006534_D1MODE_VBLANK_STATUS
#define S_006534_D1MODE_VBLANK_OCCURRED(x)
#define G_006534_D1MODE_VBLANK_OCCURRED(x)
#define C_006534_D1MODE_VBLANK_OCCURRED
#define S_006534_D1MODE_VBLANK_ACK(x)
#define G_006534_D1MODE_VBLANK_ACK(x)
#define C_006534_D1MODE_VBLANK_ACK
#define S_006534_D1MODE_VBLANK_STAT(x)
#define G_006534_D1MODE_VBLANK_STAT(x)
#define C_006534_D1MODE_VBLANK_STAT
#define S_006534_D1MODE_VBLANK_INTERRUPT(x)
#define G_006534_D1MODE_VBLANK_INTERRUPT(x)
#define C_006534_D1MODE_VBLANK_INTERRUPT
#define R_006540_DxMODE_INT_MASK
#define S_006540_D1MODE_VBLANK_INT_MASK(x)
#define G_006540_D1MODE_VBLANK_INT_MASK(x)
#define C_006540_D1MODE_VBLANK_INT_MASK
#define S_006540_D1MODE_VLINE_INT_MASK(x)
#define G_006540_D1MODE_VLINE_INT_MASK(x)
#define C_006540_D1MODE_VLINE_INT_MASK
#define S_006540_D2MODE_VBLANK_INT_MASK(x)
#define G_006540_D2MODE_VBLANK_INT_MASK(x)
#define C_006540_D2MODE_VBLANK_INT_MASK
#define S_006540_D2MODE_VLINE_INT_MASK(x)
#define G_006540_D2MODE_VLINE_INT_MASK(x)
#define C_006540_D2MODE_VLINE_INT_MASK
#define S_006540_D1MODE_VBLANK_CP_SEL(x)
#define G_006540_D1MODE_VBLANK_CP_SEL(x)
#define C_006540_D1MODE_VBLANK_CP_SEL
#define S_006540_D2MODE_VBLANK_CP_SEL(x)
#define G_006540_D2MODE_VBLANK_CP_SEL(x)
#define C_006540_D2MODE_VBLANK_CP_SEL
#define R_0068A4_D2CRTC_STATUS_FRAME_COUNT
#define S_0068A4_D2CRTC_FRAME_COUNT(x)
#define G_0068A4_D2CRTC_FRAME_COUNT(x)
#define C_0068A4_D2CRTC_FRAME_COUNT
#define R_006D34_D2MODE_VBLANK_STATUS
#define S_006D34_D2MODE_VBLANK_OCCURRED(x)
#define G_006D34_D2MODE_VBLANK_OCCURRED(x)
#define C_006D34_D2MODE_VBLANK_OCCURRED
#define S_006D34_D2MODE_VBLANK_ACK(x)
#define G_006D34_D2MODE_VBLANK_ACK(x)
#define C_006D34_D2MODE_VBLANK_ACK
#define S_006D34_D2MODE_VBLANK_STAT(x)
#define G_006D34_D2MODE_VBLANK_STAT(x)
#define C_006D34_D2MODE_VBLANK_STAT
#define S_006D34_D2MODE_VBLANK_INTERRUPT(x)
#define G_006D34_D2MODE_VBLANK_INTERRUPT(x)
#define C_006D34_D2MODE_VBLANK_INTERRUPT
#define R_007EDC_DISP_INTERRUPT_STATUS
#define S_007EDC_LB_D1_VBLANK_INTERRUPT(x)
#define G_007EDC_LB_D1_VBLANK_INTERRUPT(x)
#define C_007EDC_LB_D1_VBLANK_INTERRUPT
#define S_007EDC_LB_D2_VBLANK_INTERRUPT(x)
#define G_007EDC_LB_D2_VBLANK_INTERRUPT(x)
#define C_007EDC_LB_D2_VBLANK_INTERRUPT
#define S_007EDC_DACA_AUTODETECT_INTERRUPT(x)
#define G_007EDC_DACA_AUTODETECT_INTERRUPT(x)
#define C_007EDC_DACA_AUTODETECT_INTERRUPT
#define S_007EDC_DACB_AUTODETECT_INTERRUPT(x)
#define G_007EDC_DACB_AUTODETECT_INTERRUPT(x)
#define C_007EDC_DACB_AUTODETECT_INTERRUPT
#define S_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x)
#define G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x)
#define C_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT
#define S_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x)
#define G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x)
#define C_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT
#define R_007828_DACA_AUTODETECT_CONTROL
#define S_007828_DACA_AUTODETECT_MODE(x)
#define G_007828_DACA_AUTODETECT_MODE(x)
#define C_007828_DACA_AUTODETECT_MODE
#define S_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x)
#define G_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x)
#define C_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER
#define S_007828_DACA_AUTODETECT_CHECK_MASK(x)
#define G_007828_DACA_AUTODETECT_CHECK_MASK(x)
#define C_007828_DACA_AUTODETECT_CHECK_MASK
#define R_007838_DACA_AUTODETECT_INT_CONTROL
#define S_007838_DACA_AUTODETECT_ACK(x)
#define C_007838_DACA_DACA_AUTODETECT_ACK
#define S_007838_DACA_AUTODETECT_INT_ENABLE(x)
#define G_007838_DACA_AUTODETECT_INT_ENABLE(x)
#define C_007838_DACA_AUTODETECT_INT_ENABLE
#define R_007A28_DACB_AUTODETECT_CONTROL
#define S_007A28_DACB_AUTODETECT_MODE(x)
#define G_007A28_DACB_AUTODETECT_MODE(x)
#define C_007A28_DACB_AUTODETECT_MODE
#define S_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x)
#define G_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x)
#define C_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER
#define S_007A28_DACB_AUTODETECT_CHECK_MASK(x)
#define G_007A28_DACB_AUTODETECT_CHECK_MASK(x)
#define C_007A28_DACB_AUTODETECT_CHECK_MASK
#define R_007A38_DACB_AUTODETECT_INT_CONTROL
#define S_007A38_DACB_AUTODETECT_ACK(x)
#define C_007A38_DACB_DACA_AUTODETECT_ACK
#define S_007A38_DACB_AUTODETECT_INT_ENABLE(x)
#define G_007A38_DACB_AUTODETECT_INT_ENABLE(x)
#define C_007A38_DACB_AUTODETECT_INT_ENABLE
#define R_007D00_DC_HOT_PLUG_DETECT1_CONTROL
#define S_007D00_DC_HOT_PLUG_DETECT1_EN(x)
#define G_007D00_DC_HOT_PLUG_DETECT1_EN(x)
#define C_007D00_DC_HOT_PLUG_DETECT1_EN
#define R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS
#define S_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x)
#define G_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x)
#define C_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS
#define S_007D04_DC_HOT_PLUG_DETECT1_SENSE(x)
#define G_007D04_DC_HOT_PLUG_DETECT1_SENSE(x)
#define C_007D04_DC_HOT_PLUG_DETECT1_SENSE
#define R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL
#define S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(x)
#define C_007D08_DC_HOT_PLUG_DETECT1_INT_ACK
#define S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x)
#define G_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x)
#define C_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY
#define S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x)
#define G_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x)
#define C_007D08_DC_HOT_PLUG_DETECT1_INT_EN
#define R_007D10_DC_HOT_PLUG_DETECT2_CONTROL
#define S_007D10_DC_HOT_PLUG_DETECT2_EN(x)
#define G_007D10_DC_HOT_PLUG_DETECT2_EN(x)
#define C_007D10_DC_HOT_PLUG_DETECT2_EN
#define R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS
#define S_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x)
#define G_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x)
#define C_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS
#define S_007D14_DC_HOT_PLUG_DETECT2_SENSE(x)
#define G_007D14_DC_HOT_PLUG_DETECT2_SENSE(x)
#define C_007D14_DC_HOT_PLUG_DETECT2_SENSE
#define R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL
#define S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(x)
#define C_007D18_DC_HOT_PLUG_DETECT2_INT_ACK
#define S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x)
#define G_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x)
#define C_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY
#define S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x)
#define G_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x)
#define C_007D18_DC_HOT_PLUG_DETECT2_INT_EN
#define R_007404_HDMI0_STATUS
#define S_007404_HDMI0_AZ_FORMAT_WTRIG(x)
#define G_007404_HDMI0_AZ_FORMAT_WTRIG(x)
#define C_007404_HDMI0_AZ_FORMAT_WTRIG
#define S_007404_HDMI0_AZ_FORMAT_WTRIG_INT(x)
#define G_007404_HDMI0_AZ_FORMAT_WTRIG_INT(x)
#define C_007404_HDMI0_AZ_FORMAT_WTRIG_INT
#define R_007408_HDMI0_AUDIO_PACKET_CONTROL
#define S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(x)
#define G_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(x)
#define C_007408_HDMI0_AZ_FORMAT_WTRIG_MASK
#define S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(x)
#define G_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(x)
#define C_007408_HDMI0_AZ_FORMAT_WTRIG_ACK

/* MC registers */
#define R_000000_MC_STATUS
#define S_000000_MC_IDLE(x)
#define G_000000_MC_IDLE(x)
#define C_000000_MC_IDLE
#define R_000004_MC_FB_LOCATION
#define S_000004_MC_FB_START(x)
#define G_000004_MC_FB_START(x)
#define C_000004_MC_FB_START
#define S_000004_MC_FB_TOP(x)
#define G_000004_MC_FB_TOP(x)
#define C_000004_MC_FB_TOP
#define R_000005_MC_AGP_LOCATION
#define S_000005_MC_AGP_START(x)
#define G_000005_MC_AGP_START(x)
#define C_000005_MC_AGP_START
#define S_000005_MC_AGP_TOP(x)
#define G_000005_MC_AGP_TOP(x)
#define C_000005_MC_AGP_TOP
#define R_000006_AGP_BASE
#define S_000006_AGP_BASE_ADDR(x)
#define G_000006_AGP_BASE_ADDR(x)
#define C_000006_AGP_BASE_ADDR
#define R_000007_AGP_BASE_2
#define S_000007_AGP_BASE_ADDR_2(x)
#define G_000007_AGP_BASE_ADDR_2(x)
#define C_000007_AGP_BASE_ADDR_2
#define R_000009_MC_CNTL1
#define S_000009_ENABLE_PAGE_TABLES(x)
#define G_000009_ENABLE_PAGE_TABLES(x)
#define C_000009_ENABLE_PAGE_TABLES
/* FIXME don't know the various field size need feedback from AMD */
#define R_000100_MC_PT0_CNTL
#define S_000100_ENABLE_PT(x)
#define G_000100_ENABLE_PT(x)
#define C_000100_ENABLE_PT
#define S_000100_EFFECTIVE_L2_CACHE_SIZE(x)
#define G_000100_EFFECTIVE_L2_CACHE_SIZE(x)
#define C_000100_EFFECTIVE_L2_CACHE_SIZE
#define S_000100_EFFECTIVE_L2_QUEUE_SIZE(x)
#define G_000100_EFFECTIVE_L2_QUEUE_SIZE(x)
#define C_000100_EFFECTIVE_L2_QUEUE_SIZE
#define S_000100_INVALIDATE_ALL_L1_TLBS(x)
#define G_000100_INVALIDATE_ALL_L1_TLBS(x)
#define C_000100_INVALIDATE_ALL_L1_TLBS
#define S_000100_INVALIDATE_L2_CACHE(x)
#define G_000100_INVALIDATE_L2_CACHE(x)
#define C_000100_INVALIDATE_L2_CACHE
#define R_000102_MC_PT0_CONTEXT0_CNTL
#define S_000102_ENABLE_PAGE_TABLE(x)
#define G_000102_ENABLE_PAGE_TABLE(x)
#define C_000102_ENABLE_PAGE_TABLE
#define S_000102_PAGE_TABLE_DEPTH(x)
#define G_000102_PAGE_TABLE_DEPTH(x)
#define C_000102_PAGE_TABLE_DEPTH
#define V_000102_PAGE_TABLE_FLAT
/* R600 documentation suggest that this should be a number of pages */
#define R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR
#define R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR
#define R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR
#define R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR
#define R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR
#define R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR
#define R_00016C_MC_PT0_CLIENT0_CNTL
#define S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x)
#define G_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x)
#define C_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE
#define S_00016C_TRANSLATION_MODE_OVERRIDE(x)
#define G_00016C_TRANSLATION_MODE_OVERRIDE(x)
#define C_00016C_TRANSLATION_MODE_OVERRIDE
#define S_00016C_SYSTEM_ACCESS_MODE_MASK(x)
#define G_00016C_SYSTEM_ACCESS_MODE_MASK(x)
#define C_00016C_SYSTEM_ACCESS_MODE_MASK
#define V_00016C_SYSTEM_ACCESS_MODE_PA_ONLY
#define V_00016C_SYSTEM_ACCESS_MODE_USE_SYS_MAP
#define V_00016C_SYSTEM_ACCESS_MODE_IN_SYS
#define V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS
#define S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x)
#define G_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x)
#define C_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS
#define V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH
#define V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE
#define S_00016C_EFFECTIVE_L1_CACHE_SIZE(x)
#define G_00016C_EFFECTIVE_L1_CACHE_SIZE(x)
#define C_00016C_EFFECTIVE_L1_CACHE_SIZE
#define S_00016C_ENABLE_FRAGMENT_PROCESSING(x)
#define G_00016C_ENABLE_FRAGMENT_PROCESSING(x)
#define C_00016C_ENABLE_FRAGMENT_PROCESSING
#define S_00016C_EFFECTIVE_L1_QUEUE_SIZE(x)
#define G_00016C_EFFECTIVE_L1_QUEUE_SIZE(x)
#define C_00016C_EFFECTIVE_L1_QUEUE_SIZE
#define S_00016C_INVALIDATE_L1_TLB(x)
#define G_00016C_INVALIDATE_L1_TLB(x)
#define C_00016C_INVALIDATE_L1_TLB

#define R_006548_D1MODE_PRIORITY_A_CNT
#define S_006548_D1MODE_PRIORITY_MARK_A(x)
#define G_006548_D1MODE_PRIORITY_MARK_A(x)
#define C_006548_D1MODE_PRIORITY_MARK_A
#define S_006548_D1MODE_PRIORITY_A_OFF(x)
#define G_006548_D1MODE_PRIORITY_A_OFF(x)
#define C_006548_D1MODE_PRIORITY_A_OFF
#define S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x)
#define G_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x)
#define C_006548_D1MODE_PRIORITY_A_ALWAYS_ON
#define S_006548_D1MODE_PRIORITY_A_FORCE_MASK(x)
#define G_006548_D1MODE_PRIORITY_A_FORCE_MASK(x)
#define C_006548_D1MODE_PRIORITY_A_FORCE_MASK
#define R_00654C_D1MODE_PRIORITY_B_CNT
#define S_00654C_D1MODE_PRIORITY_MARK_B(x)
#define G_00654C_D1MODE_PRIORITY_MARK_B(x)
#define C_00654C_D1MODE_PRIORITY_MARK_B
#define S_00654C_D1MODE_PRIORITY_B_OFF(x)
#define G_00654C_D1MODE_PRIORITY_B_OFF(x)
#define C_00654C_D1MODE_PRIORITY_B_OFF
#define S_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x)
#define G_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x)
#define C_00654C_D1MODE_PRIORITY_B_ALWAYS_ON
#define S_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x)
#define G_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x)
#define C_00654C_D1MODE_PRIORITY_B_FORCE_MASK
#define R_006D48_D2MODE_PRIORITY_A_CNT
#define S_006D48_D2MODE_PRIORITY_MARK_A(x)
#define G_006D48_D2MODE_PRIORITY_MARK_A(x)
#define C_006D48_D2MODE_PRIORITY_MARK_A
#define S_006D48_D2MODE_PRIORITY_A_OFF(x)
#define G_006D48_D2MODE_PRIORITY_A_OFF(x)
#define C_006D48_D2MODE_PRIORITY_A_OFF
#define S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x)
#define G_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x)
#define C_006D48_D2MODE_PRIORITY_A_ALWAYS_ON
#define S_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x)
#define G_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x)
#define C_006D48_D2MODE_PRIORITY_A_FORCE_MASK
#define R_006D4C_D2MODE_PRIORITY_B_CNT
#define S_006D4C_D2MODE_PRIORITY_MARK_B(x)
#define G_006D4C_D2MODE_PRIORITY_MARK_B(x)
#define C_006D4C_D2MODE_PRIORITY_MARK_B
#define S_006D4C_D2MODE_PRIORITY_B_OFF(x)
#define G_006D4C_D2MODE_PRIORITY_B_OFF(x)
#define C_006D4C_D2MODE_PRIORITY_B_OFF
#define S_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x)
#define G_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x)
#define C_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON
#define S_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x)
#define G_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x)
#define C_006D4C_D2MODE_PRIORITY_B_FORCE_MASK

/* PLL regs */
#define GENERAL_PWRMGT
#define GLOBAL_PWRMGT_EN
#define MOBILE_SU
#define DYN_PWRMGT_SCLK_LENGTH
#define NORMAL_POWER_SCLK_HILEN(x)
#define NORMAL_POWER_SCLK_LOLEN(x)
#define REDUCED_POWER_SCLK_HILEN(x)
#define REDUCED_POWER_SCLK_LOLEN(x)
#define POWER_D1_SCLK_HILEN(x)
#define POWER_D1_SCLK_LOLEN(x)
#define STATIC_SCREEN_HILEN(x)
#define STATIC_SCREEN_LOLEN(x)
#define DYN_SCLK_VOL_CNTL
#define IO_CG_VOLTAGE_DROP
#define VOLTAGE_DROP_SYNC
#define VOLTAGE_DELAY_SEL(x)
#define HDP_DYN_CNTL
#define HDP_FORCEON
#define MC_HOST_DYN_CNTL
#define MC_HOST_FORCEON
#define DYN_BACKBIAS_CNTL
#define IO_CG_BACKBIAS_EN

/* mmreg */
#define DOUT_POWER_MANAGEMENT_CNTL
#define PWRDN_WAIT_BUSY_OFF
#define PWRDN_WAIT_PWRSEQ_OFF
#define PWRDN_WAIT_PPLL_OFF
#define PWRUP_WAIT_PPLL_ON
#define PWRUP_WAIT_MEM_INIT_DONE
#define PM_ASSERT_RESET
#define PM_PWRDN_PPLL

#endif