/* * Copyright 2009 Advanced Micro Devices, Inc. * Copyright 2009 Red Hat Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie * Alex Deucher * Jerome Glisse */ #ifndef RV770_H #define RV770_H #define R7XX_MAX_SH_GPRS … #define R7XX_MAX_TEMP_GPRS … #define R7XX_MAX_SH_THREADS … #define R7XX_MAX_SH_STACK_ENTRIES … #define R7XX_MAX_BACKENDS … #define R7XX_MAX_BACKENDS_MASK … #define R7XX_MAX_SIMDS … #define R7XX_MAX_SIMDS_MASK … #define R7XX_MAX_PIPES … #define R7XX_MAX_PIPES_MASK … /* discrete uvd clocks */ #define CG_UPLL_FUNC_CNTL … #define UPLL_RESET_MASK … #define UPLL_SLEEP_MASK … #define UPLL_BYPASS_EN_MASK … #define UPLL_CTLREQ_MASK … #define UPLL_REF_DIV(x) … #define UPLL_REF_DIV_MASK … #define UPLL_CTLACK_MASK … #define UPLL_CTLACK2_MASK … #define CG_UPLL_FUNC_CNTL_2 … #define UPLL_SW_HILEN(x) … #define UPLL_SW_LOLEN(x) … #define UPLL_SW_HILEN2(x) … #define UPLL_SW_LOLEN2(x) … #define UPLL_SW_MASK … #define VCLK_SRC_SEL(x) … #define VCLK_SRC_SEL_MASK … #define DCLK_SRC_SEL(x) … #define DCLK_SRC_SEL_MASK … #define CG_UPLL_FUNC_CNTL_3 … #define UPLL_FB_DIV(x) … #define UPLL_FB_DIV_MASK … /* pm registers */ #define SMC_SRAM_ADDR … #define SMC_SRAM_AUTO_INC_DIS … #define SMC_SRAM_DATA … #define SMC_IO … #define SMC_RST_N … #define SMC_STOP_MODE … #define SMC_CLK_EN … #define SMC_MSG … #define HOST_SMC_MSG(x) … #define HOST_SMC_MSG_MASK … #define HOST_SMC_MSG_SHIFT … #define HOST_SMC_RESP(x) … #define HOST_SMC_RESP_MASK … #define HOST_SMC_RESP_SHIFT … #define SMC_HOST_MSG(x) … #define SMC_HOST_MSG_MASK … #define SMC_HOST_MSG_SHIFT … #define SMC_HOST_RESP(x) … #define SMC_HOST_RESP_MASK … #define SMC_HOST_RESP_SHIFT … #define SMC_ISR_FFD8_FFDB … #define CG_SPLL_FUNC_CNTL … #define SPLL_RESET … #define SPLL_SLEEP … #define SPLL_DIVEN … #define SPLL_BYPASS_EN … #define SPLL_REF_DIV(x) … #define SPLL_REF_DIV_MASK … #define SPLL_HILEN(x) … #define SPLL_HILEN_MASK … #define SPLL_LOLEN(x) … #define SPLL_LOLEN_MASK … #define CG_SPLL_FUNC_CNTL_2 … #define SCLK_MUX_SEL(x) … #define SCLK_MUX_SEL_MASK … #define SCLK_MUX_UPDATE … #define CG_SPLL_FUNC_CNTL_3 … #define SPLL_FB_DIV(x) … #define SPLL_FB_DIV_MASK … #define SPLL_DITHEN … #define CG_SPLL_STATUS … #define SPLL_CHG_STATUS … #define SPLL_CNTL_MODE … #define SPLL_DIV_SYNC … #define MPLL_CNTL_MODE … #define MPLL_MCLK_SEL … #define RV730_MPLL_MCLK_SEL … #define MPLL_AD_FUNC_CNTL … #define CLKF(x) … #define CLKF_MASK … #define CLKR(x) … #define CLKR_MASK … #define CLKFRAC(x) … #define CLKFRAC_MASK … #define YCLK_POST_DIV(x) … #define YCLK_POST_DIV_MASK … #define IBIAS(x) … #define IBIAS_MASK … #define RESET … #define PDNB … #define MPLL_AD_FUNC_CNTL_2 … #define BYPASS … #define BIAS_GEN_PDNB … #define RESET_EN … #define VCO_MODE … #define MPLL_DQ_FUNC_CNTL … #define MPLL_DQ_FUNC_CNTL_2 … #define GENERAL_PWRMGT … #define GLOBAL_PWRMGT_EN … #define STATIC_PM_EN … #define THERMAL_PROTECTION_DIS … #define THERMAL_PROTECTION_TYPE … #define ENABLE_GEN2PCIE … #define ENABLE_GEN2XSP … #define SW_SMIO_INDEX(x) … #define SW_SMIO_INDEX_MASK … #define SW_SMIO_INDEX_SHIFT … #define LOW_VOLT_D2_ACPI … #define LOW_VOLT_D3_ACPI … #define VOLT_PWRMGT_EN … #define BACKBIAS_PAD_EN … #define BACKBIAS_VALUE … #define DYN_SPREAD_SPECTRUM_EN … #define AC_DC_SW … #define CG_TPC … #define SCLK_PWRMGT_CNTL … #define SCLK_PWRMGT_OFF … #define SCLK_LOW_D1 … #define FIR_RESET … #define FIR_FORCE_TREND_SEL … #define FIR_TREND_MODE … #define DYN_GFX_CLK_OFF_EN … #define GFX_CLK_FORCE_ON … #define GFX_CLK_REQUEST_OFF … #define GFX_CLK_FORCE_OFF … #define GFX_CLK_OFF_ACPI_D1 … #define GFX_CLK_OFF_ACPI_D2 … #define GFX_CLK_OFF_ACPI_D3 … #define MCLK_PWRMGT_CNTL … #define DLL_SPEED(x) … #define DLL_SPEED_MASK … #define MPLL_PWRMGT_OFF … #define DLL_READY … #define MC_INT_CNTL … #define MRDCKA0_SLEEP … #define MRDCKA1_SLEEP … #define MRDCKB0_SLEEP … #define MRDCKB1_SLEEP … #define MRDCKC0_SLEEP … #define MRDCKC1_SLEEP … #define MRDCKD0_SLEEP … #define MRDCKD1_SLEEP … #define MRDCKA0_RESET … #define MRDCKA1_RESET … #define MRDCKB0_RESET … #define MRDCKB1_RESET … #define MRDCKC0_RESET … #define MRDCKC1_RESET … #define MRDCKD0_RESET … #define MRDCKD1_RESET … #define DLL_READY_READ … #define USE_DISPLAY_GAP … #define USE_DISPLAY_URGENT_NORMAL … #define MPLL_TURNOFF_D2 … #define DLL_CNTL … #define MRDCKA0_BYPASS … #define MRDCKA1_BYPASS … #define MRDCKB0_BYPASS … #define MRDCKB1_BYPASS … #define MRDCKC0_BYPASS … #define MRDCKC1_BYPASS … #define MRDCKD0_BYPASS … #define MRDCKD1_BYPASS … #define MPLL_TIME … #define MPLL_LOCK_TIME(x) … #define MPLL_LOCK_TIME_MASK … #define MPLL_RESET_TIME(x) … #define MPLL_RESET_TIME_MASK … #define CG_CLKPIN_CNTL … #define MUX_TCLK_TO_XCLK … #define XTALIN_DIVIDE … #define TARGET_AND_CURRENT_PROFILE_INDEX … #define CURRENT_PROFILE_INDEX_MASK … #define CURRENT_PROFILE_INDEX_SHIFT … #define S0_VID_LOWER_SMIO_CNTL … #define S1_VID_LOWER_SMIO_CNTL … #define S2_VID_LOWER_SMIO_CNTL … #define S3_VID_LOWER_SMIO_CNTL … #define CG_FTV … #define CG_FFCT_0 … #define UTC_0(x) … #define UTC_0_MASK … #define DTC_0(x) … #define DTC_0_MASK … #define CG_BSP … #define BSP(x) … #define BSP_MASK … #define BSU(x) … #define BSU_MASK … #define CG_AT … #define CG_R(x) … #define CG_R_MASK … #define CG_L(x) … #define CG_L_MASK … #define CG_GIT … #define CG_GICST(x) … #define CG_GICST_MASK … #define CG_GIPOT(x) … #define CG_GIPOT_MASK … #define CG_SSP … #define SST(x) … #define SST_MASK … #define SSTU(x) … #define SSTU_MASK … #define CG_DISPLAY_GAP_CNTL … #define DISP1_GAP(x) … #define DISP1_GAP_MASK … #define DISP2_GAP(x) … #define DISP2_GAP_MASK … #define VBI_TIMER_COUNT(x) … #define VBI_TIMER_COUNT_MASK … #define VBI_TIMER_UNIT(x) … #define VBI_TIMER_UNIT_MASK … #define DISP1_GAP_MCHG(x) … #define DISP1_GAP_MCHG_MASK … #define DISP2_GAP_MCHG(x) … #define DISP2_GAP_MCHG_MASK … #define CG_SPLL_SPREAD_SPECTRUM … #define SSEN … #define CLKS(x) … #define CLKS_MASK … #define CG_SPLL_SPREAD_SPECTRUM_2 … #define CLKV(x) … #define CLKV_MASK … #define CG_MPLL_SPREAD_SPECTRUM … #define CG_UPLL_SPREAD_SPECTRUM … #define SSEN_MASK … #define CG_CGTT_LOCAL_0 … #define CG_CGTT_LOCAL_1 … #define BIOS_SCRATCH_4 … #define MC_SEQ_MISC0 … #define MC_SEQ_MISC0_GDDR5_SHIFT … #define MC_SEQ_MISC0_GDDR5_MASK … #define MC_SEQ_MISC0_GDDR5_VALUE … #define MC_ARB_SQM_RATIO … #define STATE0(x) … #define STATE0_MASK … #define STATE1(x) … #define STATE1_MASK … #define STATE2(x) … #define STATE2_MASK … #define STATE3(x) … #define STATE3_MASK … #define MC_ARB_RFSH_RATE … #define POWERMODE0(x) … #define POWERMODE0_MASK … #define POWERMODE1(x) … #define POWERMODE1_MASK … #define POWERMODE2(x) … #define POWERMODE2_MASK … #define POWERMODE3(x) … #define POWERMODE3_MASK … #define CGTS_SM_CTRL_REG … /* Registers */ #define CB_COLOR0_BASE … #define CB_COLOR1_BASE … #define CB_COLOR2_BASE … #define CB_COLOR3_BASE … #define CB_COLOR4_BASE … #define CB_COLOR5_BASE … #define CB_COLOR6_BASE … #define CB_COLOR7_BASE … #define CB_COLOR7_FRAG … #define CC_GC_SHADER_PIPE_CONFIG … #define CC_RB_BACKEND_DISABLE … #define BACKEND_DISABLE(x) … #define CC_SYS_RB_BACKEND_DISABLE … #define CGTS_SYS_TCC_DISABLE … #define CGTS_TCC_DISABLE … #define CGTS_USER_SYS_TCC_DISABLE … #define CGTS_USER_TCC_DISABLE … #define CONFIG_MEMSIZE … #define CP_ME_CNTL … #define CP_ME_HALT … #define CP_PFP_HALT … #define CP_ME_RAM_DATA … #define CP_ME_RAM_RADDR … #define CP_ME_RAM_WADDR … #define CP_MEQ_THRESHOLDS … #define STQ_SPLIT(x) … #define CP_PERFMON_CNTL … #define CP_PFP_UCODE_ADDR … #define CP_PFP_UCODE_DATA … #define CP_QUEUE_THRESHOLDS … #define ROQ_IB1_START(x) … #define ROQ_IB2_START(x) … #define CP_RB_CNTL … #define RB_BUFSZ(x) … #define RB_BLKSZ(x) … #define RB_NO_UPDATE … #define RB_RPTR_WR_ENA … #define BUF_SWAP_32BIT … #define CP_RB_RPTR … #define CP_RB_RPTR_ADDR … #define CP_RB_RPTR_ADDR_HI … #define CP_RB_RPTR_WR … #define CP_RB_WPTR … #define CP_RB_WPTR_ADDR … #define CP_RB_WPTR_ADDR_HI … #define CP_RB_WPTR_DELAY … #define CP_SEM_WAIT_TIMER … #define DB_DEBUG3 … #define DB_CLK_OFF_DELAY(x) … #define DB_DEBUG4 … #define DISABLE_TILE_COVERED_FOR_PS_ITER … #define DCP_TILING_CONFIG … #define PIPE_TILING(x) … #define BANK_TILING(x) … #define GROUP_SIZE(x) … #define ROW_TILING(x) … #define BANK_SWAPS(x) … #define SAMPLE_SPLIT(x) … #define BACKEND_MAP(x) … #define GB_TILING_CONFIG … #define PIPE_TILING__SHIFT … #define PIPE_TILING__MASK … #define DMA_TILING_CONFIG … #define DMA_TILING_CONFIG2 … /* RV730 only */ #define UVD_UDEC_TILING_CONFIG … #define UVD_UDEC_DB_TILING_CONFIG … #define UVD_UDEC_DBW_TILING_CONFIG … #define UVD_NO_OP … #define GC_USER_SHADER_PIPE_CONFIG … #define INACTIVE_QD_PIPES(x) … #define INACTIVE_QD_PIPES_MASK … #define INACTIVE_QD_PIPES_SHIFT … #define INACTIVE_SIMDS(x) … #define INACTIVE_SIMDS_MASK … #define GRBM_CNTL … #define GRBM_READ_TIMEOUT(x) … #define GRBM_SOFT_RESET … #define SOFT_RESET_CP … #define GRBM_STATUS … #define CMDFIFO_AVAIL_MASK … #define GUI_ACTIVE … #define GRBM_STATUS2 … #define CG_THERMAL_CTRL … #define DPM_EVENT_SRC(x) … #define DPM_EVENT_SRC_MASK … #define DIG_THERM_DPM(x) … #define DIG_THERM_DPM_MASK … #define DIG_THERM_DPM_SHIFT … #define CG_THERMAL_INT … #define DIG_THERM_INTH(x) … #define DIG_THERM_INTH_MASK … #define DIG_THERM_INTH_SHIFT … #define DIG_THERM_INTL(x) … #define DIG_THERM_INTL_MASK … #define DIG_THERM_INTL_SHIFT … #define THERM_INT_MASK_HIGH … #define THERM_INT_MASK_LOW … #define CG_MULT_THERMAL_STATUS … #define ASIC_T(x) … #define ASIC_T_MASK … #define ASIC_T_SHIFT … #define HDP_HOST_PATH_CNTL … #define HDP_NONSURFACE_BASE … #define HDP_NONSURFACE_INFO … #define HDP_NONSURFACE_SIZE … #define HDP_REG_COHERENCY_FLUSH_CNTL … #define HDP_TILING_CONFIG … #define HDP_DEBUG1 … #define MC_SHARED_CHMAP … #define NOOFCHAN_SHIFT … #define NOOFCHAN_MASK … #define MC_SHARED_CHREMAP … #define MC_ARB_RAMCFG … #define NOOFBANK_SHIFT … #define NOOFBANK_MASK … #define NOOFRANK_SHIFT … #define NOOFRANK_MASK … #define NOOFROWS_SHIFT … #define NOOFROWS_MASK … #define NOOFCOLS_SHIFT … #define NOOFCOLS_MASK … #define CHANSIZE_SHIFT … #define CHANSIZE_MASK … #define BURSTLENGTH_SHIFT … #define BURSTLENGTH_MASK … #define CHANSIZE_OVERRIDE … #define MC_VM_AGP_TOP … #define MC_VM_AGP_BOT … #define MC_VM_AGP_BASE … #define MC_VM_FB_LOCATION … #define MC_VM_MB_L1_TLB0_CNTL … #define MC_VM_MB_L1_TLB1_CNTL … #define MC_VM_MB_L1_TLB2_CNTL … #define MC_VM_MB_L1_TLB3_CNTL … #define ENABLE_L1_TLB … #define ENABLE_L1_FRAGMENT_PROCESSING … #define SYSTEM_ACCESS_MODE_PA_ONLY … #define SYSTEM_ACCESS_MODE_USE_SYS_MAP … #define SYSTEM_ACCESS_MODE_IN_SYS … #define SYSTEM_ACCESS_MODE_NOT_IN_SYS … #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU … #define EFFECTIVE_L1_TLB_SIZE(x) … #define EFFECTIVE_L1_QUEUE_SIZE(x) … #define MC_VM_MD_L1_TLB0_CNTL … #define MC_VM_MD_L1_TLB1_CNTL … #define MC_VM_MD_L1_TLB2_CNTL … #define MC_VM_MD_L1_TLB3_CNTL … #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR … #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR … #define MC_VM_SYSTEM_APERTURE_LOW_ADDR … #define PA_CL_ENHANCE … #define CLIP_VTX_REORDER_ENA … #define NUM_CLIP_SEQ(x) … #define PA_SC_AA_CONFIG … #define PA_SC_CLIPRECT_RULE … #define PA_SC_EDGERULE … #define PA_SC_FIFO_SIZE … #define SC_PRIM_FIFO_SIZE(x) … #define SC_HIZ_TILE_FIFO_SIZE(x) … #define PA_SC_FORCE_EOV_MAX_CNTS … #define FORCE_EOV_MAX_CLK_CNT(x) … #define FORCE_EOV_MAX_REZ_CNT(x) … #define PA_SC_LINE_STIPPLE … #define PA_SC_LINE_STIPPLE_STATE … #define PA_SC_MODE_CNTL … #define PA_SC_MULTI_CHIP_CNTL … #define SC_EARLYZ_TILE_FIFO_SIZE(x) … #define SCRATCH_REG0 … #define SCRATCH_REG1 … #define SCRATCH_REG2 … #define SCRATCH_REG3 … #define SCRATCH_REG4 … #define SCRATCH_REG5 … #define SCRATCH_REG6 … #define SCRATCH_REG7 … #define SCRATCH_UMSK … #define SCRATCH_ADDR … #define SMX_SAR_CTL0 … #define SMX_DC_CTL0 … #define USE_HASH_FUNCTION … #define CACHE_DEPTH(x) … #define FLUSH_ALL_ON_EVENT … #define STALL_ON_EVENT … #define SMX_EVENT_CTL … #define ES_FLUSH_CTL(x) … #define GS_FLUSH_CTL(x) … #define ACK_FLUSH_CTL(x) … #define SYNC_FLUSH_CTL … #define SPI_CONFIG_CNTL … #define GPR_WRITE_PRIORITY(x) … #define DISABLE_INTERP_1 … #define SPI_CONFIG_CNTL_1 … #define VTX_DONE_DELAY(x) … #define INTERP_ONE_PRIM_PER_ROW … #define SPI_INPUT_Z … #define SPI_PS_IN_CONTROL_0 … #define NUM_INTERP(x) … #define POSITION_ENA … #define POSITION_CENTROID … #define POSITION_ADDR(x) … #define PARAM_GEN(x) … #define PARAM_GEN_ADDR(x) … #define BARYC_SAMPLE_CNTL(x) … #define PERSP_GRADIENT_ENA … #define LINEAR_GRADIENT_ENA … #define POSITION_SAMPLE … #define BARYC_AT_SAMPLE_ENA … #define SQ_CONFIG … #define VC_ENABLE … #define EXPORT_SRC_C … #define DX9_CONSTS … #define ALU_INST_PREFER_VECTOR … #define DX10_CLAMP … #define CLAUSE_SEQ_PRIO(x) … #define PS_PRIO(x) … #define VS_PRIO(x) … #define GS_PRIO(x) … #define SQ_DYN_GPR_SIZE_SIMD_AB_0 … #define SIMDA_RING0(x) … #define SIMDA_RING1(x) … #define SIMDB_RING0(x) … #define SIMDB_RING1(x) … #define SQ_DYN_GPR_SIZE_SIMD_AB_1 … #define SQ_DYN_GPR_SIZE_SIMD_AB_2 … #define SQ_DYN_GPR_SIZE_SIMD_AB_3 … #define SQ_DYN_GPR_SIZE_SIMD_AB_4 … #define SQ_DYN_GPR_SIZE_SIMD_AB_5 … #define SQ_DYN_GPR_SIZE_SIMD_AB_6 … #define SQ_DYN_GPR_SIZE_SIMD_AB_7 … #define ES_PRIO(x) … #define SQ_GPR_RESOURCE_MGMT_1 … #define NUM_PS_GPRS(x) … #define NUM_VS_GPRS(x) … #define DYN_GPR_ENABLE … #define NUM_CLAUSE_TEMP_GPRS(x) … #define SQ_GPR_RESOURCE_MGMT_2 … #define NUM_GS_GPRS(x) … #define NUM_ES_GPRS(x) … #define SQ_MS_FIFO_SIZES … #define CACHE_FIFO_SIZE(x) … #define FETCH_FIFO_HIWATER(x) … #define DONE_FIFO_HIWATER(x) … #define ALU_UPDATE_FIFO_HIWATER(x) … #define SQ_STACK_RESOURCE_MGMT_1 … #define NUM_PS_STACK_ENTRIES(x) … #define NUM_VS_STACK_ENTRIES(x) … #define SQ_STACK_RESOURCE_MGMT_2 … #define NUM_GS_STACK_ENTRIES(x) … #define NUM_ES_STACK_ENTRIES(x) … #define SQ_THREAD_RESOURCE_MGMT … #define NUM_PS_THREADS(x) … #define NUM_VS_THREADS(x) … #define NUM_GS_THREADS(x) … #define NUM_ES_THREADS(x) … #define SX_DEBUG_1 … #define ENABLE_NEW_SMX_ADDRESS … #define SX_EXPORT_BUFFER_SIZES … #define COLOR_BUFFER_SIZE(x) … #define POSITION_BUFFER_SIZE(x) … #define SMX_BUFFER_SIZE(x) … #define SX_MISC … #define TA_CNTL_AUX … #define DISABLE_CUBE_WRAP … #define DISABLE_CUBE_ANISO … #define SYNC_GRADIENT … #define SYNC_WALKER … #define SYNC_ALIGNER … #define BILINEAR_PRECISION_6_BIT … #define BILINEAR_PRECISION_8_BIT … #define TCP_CNTL … #define TCP_CHAN_STEER … #define VC_ENHANCE … #define VGT_CACHE_INVALIDATION … #define CACHE_INVALIDATION(x) … #define VC_ONLY … #define TC_ONLY … #define VC_AND_TC … #define AUTO_INVLD_EN(x) … #define NO_AUTO … #define ES_AUTO … #define GS_AUTO … #define ES_AND_GS_AUTO … #define VGT_ES_PER_GS … #define VGT_GS_PER_ES … #define VGT_GS_PER_VS … #define VGT_GS_VERTEX_REUSE … #define VGT_NUM_INSTANCES … #define VGT_OUT_DEALLOC_CNTL … #define DEALLOC_DIST_MASK … #define VGT_STRMOUT_EN … #define VGT_VERTEX_REUSE_BLOCK_CNTL … #define VTX_REUSE_DEPTH_MASK … #define VM_CONTEXT0_CNTL … #define ENABLE_CONTEXT … #define PAGE_TABLE_DEPTH(x) … #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT … #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT0_PAGE_TABLE_END_ADDR … #define VM_CONTEXT0_PAGE_TABLE_START_ADDR … #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR … #define VM_L2_CNTL … #define ENABLE_L2_CACHE … #define ENABLE_L2_FRAGMENT_PROCESSING … #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE … #define EFFECTIVE_L2_QUEUE_SIZE(x) … #define VM_L2_CNTL2 … #define INVALIDATE_ALL_L1_TLBS … #define INVALIDATE_L2_CACHE … #define VM_L2_CNTL3 … #define BANK_SELECT(x) … #define CACHE_UPDATE_MODE(x) … #define VM_L2_STATUS … #define L2_BUSY … #define WAIT_UNTIL … /* async DMA */ #define DMA_RB_RPTR … #define DMA_RB_WPTR … /* async DMA packets */ #define DMA_PACKET(cmd, t, s, n) … /* async DMA Packet types */ #define DMA_PACKET_WRITE … #define DMA_PACKET_COPY … #define DMA_PACKET_INDIRECT_BUFFER … #define DMA_PACKET_SEMAPHORE … #define DMA_PACKET_FENCE … #define DMA_PACKET_TRAP … #define DMA_PACKET_CONSTANT_FILL … #define DMA_PACKET_NOP … #define SRBM_STATUS … /* DCE 3.2 HDMI */ #define HDMI_CONTROL … #define HDMI_KEEPOUT_MODE … #define HDMI_PACKET_GEN_VERSION … #define HDMI_ERROR_ACK … #define HDMI_ERROR_MASK … #define HDMI_STATUS … #define HDMI_ACTIVE_AVMUTE … #define HDMI_AUDIO_PACKET_ERROR … #define HDMI_VBI_PACKET_ERROR … #define HDMI_AUDIO_PACKET_CONTROL … #define HDMI_AUDIO_DELAY_EN(x) … #define HDMI_AUDIO_PACKETS_PER_LINE(x) … #define HDMI_ACR_PACKET_CONTROL … #define HDMI_ACR_SEND … #define HDMI_ACR_CONT … #define HDMI_ACR_SELECT(x) … #define HDMI_ACR_HW … #define HDMI_ACR_32 … #define HDMI_ACR_44 … #define HDMI_ACR_48 … #define HDMI_ACR_SOURCE … #define HDMI_ACR_AUTO_SEND … #define HDMI_VBI_PACKET_CONTROL … #define HDMI_NULL_SEND … #define HDMI_GC_SEND … #define HDMI_GC_CONT … #define HDMI_INFOFRAME_CONTROL0 … #define HDMI_AVI_INFO_SEND … #define HDMI_AVI_INFO_CONT … #define HDMI_AUDIO_INFO_SEND … #define HDMI_AUDIO_INFO_CONT … #define HDMI_MPEG_INFO_SEND … #define HDMI_MPEG_INFO_CONT … #define HDMI_INFOFRAME_CONTROL1 … #define HDMI_AVI_INFO_LINE(x) … #define HDMI_AUDIO_INFO_LINE(x) … #define HDMI_MPEG_INFO_LINE(x) … #define HDMI_GENERIC_PACKET_CONTROL … #define HDMI_GENERIC0_SEND … #define HDMI_GENERIC0_CONT … #define HDMI_GENERIC1_SEND … #define HDMI_GENERIC1_CONT … #define HDMI_GENERIC0_LINE(x) … #define HDMI_GENERIC1_LINE(x) … #define HDMI_GC … #define HDMI_GC_AVMUTE … #define AFMT_AUDIO_PACKET_CONTROL2 … #define AFMT_AUDIO_LAYOUT_OVRD … #define AFMT_AUDIO_LAYOUT_SELECT … #define AFMT_60958_CS_SOURCE … #define AFMT_AUDIO_CHANNEL_ENABLE(x) … #define AFMT_DP_AUDIO_STREAM_ID(x) … #define AFMT_AVI_INFO0 … #define AFMT_AVI_INFO_CHECKSUM(x) … #define AFMT_AVI_INFO_S(x) … #define AFMT_AVI_INFO_B(x) … #define AFMT_AVI_INFO_A(x) … #define AFMT_AVI_INFO_Y(x) … #define AFMT_AVI_INFO_Y_RGB … #define AFMT_AVI_INFO_Y_YCBCR422 … #define AFMT_AVI_INFO_Y_YCBCR444 … #define AFMT_AVI_INFO_Y_A_B_S(x) … #define AFMT_AVI_INFO_R(x) … #define AFMT_AVI_INFO_M(x) … #define AFMT_AVI_INFO_C(x) … #define AFMT_AVI_INFO_C_M_R(x) … #define AFMT_AVI_INFO_SC(x) … #define AFMT_AVI_INFO_Q(x) … #define AFMT_AVI_INFO_EC(x) … #define AFMT_AVI_INFO_ITC(x) … #define AFMT_AVI_INFO_ITC_EC_Q_SC(x) … #define AFMT_AVI_INFO1 … #define AFMT_AVI_INFO_VIC(x) … #define AFMT_AVI_INFO_PR(x) … #define AFMT_AVI_INFO_TOP(x) … #define AFMT_AVI_INFO2 … #define AFMT_AVI_INFO_BOTTOM(x) … #define AFMT_AVI_INFO_LEFT(x) … #define AFMT_AVI_INFO3 … #define AFMT_AVI_INFO_RIGHT(x) … #define AFMT_AVI_INFO_VERSION(x) … #define AFMT_MPEG_INFO0 … #define AFMT_MPEG_INFO_CHECKSUM(x) … #define AFMT_MPEG_INFO_MB0(x) … #define AFMT_MPEG_INFO_MB1(x) … #define AFMT_MPEG_INFO_MB2(x) … #define AFMT_MPEG_INFO1 … #define AFMT_MPEG_INFO_MB3(x) … #define AFMT_MPEG_INFO_MF(x) … #define AFMT_MPEG_INFO_FR(x) … #define AFMT_GENERIC0_HDR … #define AFMT_GENERIC0_0 … #define AFMT_GENERIC0_1 … #define AFMT_GENERIC0_2 … #define AFMT_GENERIC0_3 … #define AFMT_GENERIC0_4 … #define AFMT_GENERIC0_5 … #define AFMT_GENERIC0_6 … #define AFMT_GENERIC1_HDR … #define AFMT_GENERIC1_0 … #define AFMT_GENERIC1_1 … #define AFMT_GENERIC1_2 … #define AFMT_GENERIC1_3 … #define AFMT_GENERIC1_4 … #define AFMT_GENERIC1_5 … #define AFMT_GENERIC1_6 … #define HDMI_ACR_32_0 … #define HDMI_ACR_CTS_32(x) … #define HDMI_ACR_32_1 … #define HDMI_ACR_N_32(x) … #define HDMI_ACR_44_0 … #define HDMI_ACR_CTS_44(x) … #define HDMI_ACR_44_1 … #define HDMI_ACR_N_44(x) … #define HDMI_ACR_48_0 … #define HDMI_ACR_CTS_48(x) … #define HDMI_ACR_48_1 … #define HDMI_ACR_N_48(x) … #define HDMI_ACR_STATUS_0 … #define HDMI_ACR_STATUS_1 … #define AFMT_AUDIO_INFO0 … #define AFMT_AUDIO_INFO_CHECKSUM(x) … #define AFMT_AUDIO_INFO_CC(x) … #define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) … #define AFMT_AUDIO_INFO1 … #define AFMT_AUDIO_INFO_CA(x) … #define AFMT_AUDIO_INFO_LSV(x) … #define AFMT_AUDIO_INFO_DM_INH(x) … #define AFMT_AUDIO_INFO_DM_INH_LSV(x) … #define AFMT_60958_0 … #define AFMT_60958_CS_A(x) … #define AFMT_60958_CS_B(x) … #define AFMT_60958_CS_C(x) … #define AFMT_60958_CS_D(x) … #define AFMT_60958_CS_MODE(x) … #define AFMT_60958_CS_CATEGORY_CODE(x) … #define AFMT_60958_CS_SOURCE_NUMBER(x) … #define AFMT_60958_CS_CHANNEL_NUMBER_L(x) … #define AFMT_60958_CS_SAMPLING_FREQUENCY(x) … #define AFMT_60958_CS_CLOCK_ACCURACY(x) … #define AFMT_60958_1 … #define AFMT_60958_CS_WORD_LENGTH(x) … #define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) … #define AFMT_60958_CS_VALID_L(x) … #define AFMT_60958_CS_VALID_R(x) … #define AFMT_60958_CS_CHANNEL_NUMBER_R(x) … #define AFMT_AUDIO_CRC_CONTROL … #define AFMT_AUDIO_CRC_EN … #define AFMT_RAMP_CONTROL0 … #define AFMT_RAMP_MAX_COUNT(x) … #define AFMT_RAMP_DATA_SIGN … #define AFMT_RAMP_CONTROL1 … #define AFMT_RAMP_MIN_COUNT(x) … #define AFMT_AUDIO_TEST_CH_DISABLE(x) … #define AFMT_RAMP_CONTROL2 … #define AFMT_RAMP_INC_COUNT(x) … #define AFMT_RAMP_CONTROL3 … #define AFMT_RAMP_DEC_COUNT(x) … #define AFMT_60958_2 … #define AFMT_60958_CS_CHANNEL_NUMBER_2(x) … #define AFMT_60958_CS_CHANNEL_NUMBER_3(x) … #define AFMT_60958_CS_CHANNEL_NUMBER_4(x) … #define AFMT_60958_CS_CHANNEL_NUMBER_5(x) … #define AFMT_60958_CS_CHANNEL_NUMBER_6(x) … #define AFMT_60958_CS_CHANNEL_NUMBER_7(x) … #define AFMT_STATUS … #define AFMT_AUDIO_ENABLE … #define AFMT_AZ_FORMAT_WTRIG … #define AFMT_AZ_FORMAT_WTRIG_INT … #define AFMT_AZ_AUDIO_ENABLE_CHG … #define AFMT_AUDIO_PACKET_CONTROL … #define AFMT_AUDIO_SAMPLE_SEND … #define AFMT_AUDIO_TEST_EN … #define AFMT_AUDIO_CHANNEL_SWAP … #define AFMT_60958_CS_UPDATE … #define AFMT_AZ_AUDIO_ENABLE_CHG_MASK … #define AFMT_AZ_FORMAT_WTRIG_MASK … #define AFMT_AZ_FORMAT_WTRIG_ACK … #define AFMT_AZ_AUDIO_ENABLE_CHG_ACK … #define AFMT_VBI_PACKET_CONTROL … #define AFMT_GENERIC0_UPDATE … #define AFMT_INFOFRAME_CONTROL0 … #define AFMT_AUDIO_INFO_SOURCE … #define AFMT_AUDIO_INFO_UPDATE … #define AFMT_MPEG_INFO_UPDATE … #define AFMT_GENERIC0_7 … /* second instance starts at 0x7800 */ #define HDMI_OFFSET0 … #define HDMI_OFFSET1 … /* DCE3.2 ELD audio interface */ #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 … #define MAX_CHANNELS(x) … /* max channels minus one. 7 = 8 channels */ #define SUPPORTED_FREQUENCIES(x) … #define DESCRIPTOR_BYTE_2(x) … #define SUPPORTED_FREQUENCIES_STEREO(x) … /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO * bit0 = 32 kHz * bit1 = 44.1 kHz * bit2 = 48 kHz * bit3 = 88.2 kHz * bit4 = 96 kHz * bit5 = 176.4 kHz * bit6 = 192 kHz */ #define AZ_HOT_PLUG_CONTROL … #define AZ_FORCE_CODEC_WAKE … #define PIN0_JACK_DETECTION_ENABLE … #define PIN1_JACK_DETECTION_ENABLE … #define PIN2_JACK_DETECTION_ENABLE … #define PIN3_JACK_DETECTION_ENABLE … #define PIN0_UNSOLICITED_RESPONSE_ENABLE … #define PIN1_UNSOLICITED_RESPONSE_ENABLE … #define PIN2_UNSOLICITED_RESPONSE_ENABLE … #define PIN3_UNSOLICITED_RESPONSE_ENABLE … #define CODEC_HOT_PLUG_ENABLE … #define PIN0_AUDIO_ENABLED … #define PIN1_AUDIO_ENABLED … #define PIN2_AUDIO_ENABLED … #define PIN3_AUDIO_ENABLED … #define AUDIO_ENABLED … #define D1GRPH_PRIMARY_SURFACE_ADDRESS … #define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH … #define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH … #define D1GRPH_SECONDARY_SURFACE_ADDRESS … #define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH … #define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH … /* PCIE indirect regs */ #define PCIE_P_CNTL … #define P_PLL_PWRDN_IN_L1L23 … #define P_PLL_BUF_PDNB … #define P_PLL_PDNB … #define P_ALLOW_PRX_FRONTEND_SHUTOFF … /* PCIE PORT regs */ #define PCIE_LC_CNTL … #define LC_L0S_INACTIVITY(x) … #define LC_L0S_INACTIVITY_MASK … #define LC_L0S_INACTIVITY_SHIFT … #define LC_L1_INACTIVITY(x) … #define LC_L1_INACTIVITY_MASK … #define LC_L1_INACTIVITY_SHIFT … #define LC_PMI_TO_L1_DIS … #define LC_ASPM_TO_L1_DIS … #define PCIE_LC_TRAINING_CNTL … #define PCIE_LC_LINK_WIDTH_CNTL … #define LC_LINK_WIDTH_SHIFT … #define LC_LINK_WIDTH_MASK … #define LC_LINK_WIDTH_X0 … #define LC_LINK_WIDTH_X1 … #define LC_LINK_WIDTH_X2 … #define LC_LINK_WIDTH_X4 … #define LC_LINK_WIDTH_X8 … #define LC_LINK_WIDTH_X16 … #define LC_LINK_WIDTH_RD_SHIFT … #define LC_LINK_WIDTH_RD_MASK … #define LC_RECONFIG_ARC_MISSING_ESCAPE … #define LC_RECONFIG_NOW … #define LC_RENEGOTIATION_SUPPORT … #define LC_RENEGOTIATE_EN … #define LC_SHORT_RECONFIG_EN … #define LC_UPCONFIGURE_SUPPORT … #define LC_UPCONFIGURE_DIS … #define PCIE_LC_SPEED_CNTL … #define LC_GEN2_EN_STRAP … #define LC_TARGET_LINK_SPEED_OVERRIDE_EN … #define LC_FORCE_EN_HW_SPEED_CHANGE … #define LC_FORCE_DIS_HW_SPEED_CHANGE … #define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK … #define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT … #define LC_CURRENT_DATA_RATE … #define LC_HW_VOLTAGE_IF_CONTROL(x) … #define LC_HW_VOLTAGE_IF_CONTROL_MASK … #define LC_HW_VOLTAGE_IF_CONTROL_SHIFT … #define LC_VOLTAGE_TIMER_SEL_MASK … #define LC_CLR_FAILED_SPD_CHANGE_CNT … #define LC_OTHER_SIDE_EVER_SENT_GEN2 … #define LC_OTHER_SIDE_SUPPORTS_GEN2 … #define MM_CFGREGS_CNTL … #define MM_WR_TO_CFG_EN … #define LINK_CNTL2 … #define TARGET_LINK_SPEED_MASK … #define SELECTABLE_DEEMPHASIS … /* * PM4 */ #define PACKET0(reg, n) … #define PACKET3(op, n) … /* UVD */ #define UVD_SEMA_ADDR_LOW … #define UVD_SEMA_ADDR_HIGH … #define UVD_SEMA_CMD … #define UVD_GPCOM_VCPU_CMD … #define UVD_GPCOM_VCPU_DATA0 … #define UVD_GPCOM_VCPU_DATA1 … #define UVD_LMI_EXT40_ADDR … #define UVD_VCPU_CHIP_ID … #define UVD_VCPU_CACHE_OFFSET0 … #define UVD_VCPU_CACHE_SIZE0 … #define UVD_VCPU_CACHE_OFFSET1 … #define UVD_VCPU_CACHE_SIZE1 … #define UVD_VCPU_CACHE_OFFSET2 … #define UVD_VCPU_CACHE_SIZE2 … #define UVD_LMI_ADDR_EXT … #define UVD_RBC_RB_RPTR … #define UVD_RBC_RB_WPTR … #define UVD_CONTEXT_ID … #endif
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