// SPDX-License-Identifier: MIT #include <drm/drm_device.h> #include "radeon.h" /* * Integrated TV out support based on the GATOS code by * Federico Ulivi <[email protected]> */ /* * Limits of h/v positions (hPos & vPos) */ #define MAX_H_POSITION … #define MAX_V_POSITION … /* * Unit for hPos (in TV clock periods) */ #define H_POS_UNIT … /* * Indexes in h. code timing table for horizontal line position adjustment */ #define H_TABLE_POS1 … #define H_TABLE_POS2 … /* * Limits of hor. size (hSize) */ #define MAX_H_SIZE … /* tv standard constants */ #define NTSC_TV_CLOCK_T … #define NTSC_TV_VFTOTAL … #define NTSC_TV_LINES_PER_FRAME … #define NTSC_TV_ZERO_H_SIZE … #define NTSC_TV_H_SIZE_UNIT … #define PAL_TV_CLOCK_T … #define PAL_TV_VFTOTAL … #define PAL_TV_LINES_PER_FRAME … #define PAL_TV_ZERO_H_SIZE … #define PAL_TV_H_SIZE_UNIT … /* tv pll setting for 27 mhz ref clk */ #define NTSC_TV_PLL_M_27 … #define NTSC_TV_PLL_N_27 … #define NTSC_TV_PLL_P_27 … #define PAL_TV_PLL_M_27 … #define PAL_TV_PLL_N_27 … #define PAL_TV_PLL_P_27 … /* tv pll setting for 14 mhz ref clk */ #define NTSC_TV_PLL_M_14 … #define NTSC_TV_PLL_N_14 … #define NTSC_TV_PLL_P_14 … #define PAL_TV_PLL_M_14 … #define PAL_TV_PLL_N_14 … #define PAL_TV_PLL_P_14 … #define VERT_LEAD_IN_LINES … #define FRAC_BITS … #define FRAC_MASK … struct radeon_tv_mode_constants { … }; static const uint16_t hor_timing_NTSC[MAX_H_CODE_TIMING_LEN] = …; static const uint16_t vert_timing_NTSC[MAX_V_CODE_TIMING_LEN] = …; static const uint16_t hor_timing_PAL[MAX_H_CODE_TIMING_LEN] = …; static const uint16_t vert_timing_PAL[MAX_V_CODE_TIMING_LEN] = …; /********************************************************************** * * availableModes * * Table of all allowed modes for tv output * **********************************************************************/ static const struct radeon_tv_mode_constants available_tv_modes[] = …; #define N_AVAILABLE_MODES … static const struct radeon_tv_mode_constants *radeon_legacy_tv_get_std_mode(struct radeon_encoder *radeon_encoder, uint16_t *pll_ref_freq) { … } static long YCOEF_value[5] = …; static long YCOEF_EN_value[5] = …; static long SLOPE_value[5] = …; static long SLOPE_limit[5] = …; static void radeon_wait_pll_lock(struct drm_encoder *encoder, unsigned n_tests, unsigned n_wait_loops, unsigned cnt_threshold) { … } static void radeon_legacy_tv_write_fifo(struct radeon_encoder *radeon_encoder, uint16_t addr, uint32_t value) { … } #if 0 /* included for completeness */ static uint32_t radeon_legacy_tv_read_fifo(struct radeon_encoder *radeon_encoder, uint16_t addr) { struct drm_device *dev = radeon_encoder->base.dev; struct radeon_device *rdev = dev->dev_private; uint32_t tmp; int i = 0; WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD); do { tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0) break; i++; } while (i < 10000); WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); return RREG32(RADEON_TV_HOST_READ_DATA); } #endif static uint16_t radeon_get_htiming_tables_addr(uint32_t tv_uv_adr) { … } static uint16_t radeon_get_vtiming_tables_addr(uint32_t tv_uv_adr) { … } static void radeon_restore_tv_timing_tables(struct radeon_encoder *radeon_encoder) { … } static void radeon_legacy_write_tv_restarts(struct radeon_encoder *radeon_encoder) { … } static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder) { … } void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { … } void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, uint32_t *v_total_disp, uint32_t *v_sync_strt_wid) { … } static int get_post_div(int value) { … } void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, uint32_t *htotal_cntl, uint32_t *ppll_ref_div, uint32_t *ppll_div_3, uint32_t *pixclks_cntl) { … } void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, uint32_t *p2pll_div_0, uint32_t *pixclks_cntl) { … }
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