/* * Copyright 2010 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Alex Deucher */ #ifndef EVERGREEND_H #define EVERGREEND_H #define EVERGREEN_MAX_SH_GPRS … #define EVERGREEN_MAX_TEMP_GPRS … #define EVERGREEN_MAX_SH_THREADS … #define EVERGREEN_MAX_SH_STACK_ENTRIES … #define EVERGREEN_MAX_FRC_EOV_CNT … #define EVERGREEN_MAX_BACKENDS … #define EVERGREEN_MAX_BACKENDS_MASK … #define EVERGREEN_MAX_SIMDS … #define EVERGREEN_MAX_SIMDS_MASK … #define EVERGREEN_MAX_PIPES … #define EVERGREEN_MAX_PIPES_MASK … #define EVERGREEN_MAX_LDS_NUM … #define CYPRESS_GB_ADDR_CONFIG_GOLDEN … #define BARTS_GB_ADDR_CONFIG_GOLDEN … #define CAYMAN_GB_ADDR_CONFIG_GOLDEN … #define JUNIPER_GB_ADDR_CONFIG_GOLDEN … #define REDWOOD_GB_ADDR_CONFIG_GOLDEN … #define TURKS_GB_ADDR_CONFIG_GOLDEN … #define CEDAR_GB_ADDR_CONFIG_GOLDEN … #define CAICOS_GB_ADDR_CONFIG_GOLDEN … #define SUMO_GB_ADDR_CONFIG_GOLDEN … #define SUMO2_GB_ADDR_CONFIG_GOLDEN … /* pm registers */ #define SMC_MSG … #define HOST_SMC_MSG(x) … #define HOST_SMC_MSG_MASK … #define HOST_SMC_MSG_SHIFT … #define HOST_SMC_RESP(x) … #define HOST_SMC_RESP_MASK … #define HOST_SMC_RESP_SHIFT … #define SMC_HOST_MSG(x) … #define SMC_HOST_MSG_MASK … #define SMC_HOST_MSG_SHIFT … #define SMC_HOST_RESP(x) … #define SMC_HOST_RESP_MASK … #define SMC_HOST_RESP_SHIFT … #define DCCG_DISP_SLOW_SELECT_REG … #define DCCG_DISP1_SLOW_SELECT(x) … #define DCCG_DISP1_SLOW_SELECT_MASK … #define DCCG_DISP1_SLOW_SELECT_SHIFT … #define DCCG_DISP2_SLOW_SELECT(x) … #define DCCG_DISP2_SLOW_SELECT_MASK … #define DCCG_DISP2_SLOW_SELECT_SHIFT … #define CG_SPLL_FUNC_CNTL … #define SPLL_RESET … #define SPLL_SLEEP … #define SPLL_BYPASS_EN … #define SPLL_REF_DIV(x) … #define SPLL_REF_DIV_MASK … #define SPLL_PDIV_A(x) … #define SPLL_PDIV_A_MASK … #define CG_SPLL_FUNC_CNTL_2 … #define SCLK_MUX_SEL(x) … #define SCLK_MUX_SEL_MASK … #define SCLK_MUX_UPDATE … #define CG_SPLL_FUNC_CNTL_3 … #define SPLL_FB_DIV(x) … #define SPLL_FB_DIV_MASK … #define SPLL_DITHEN … #define CG_SPLL_STATUS … #define SPLL_CHG_STATUS … #define MPLL_CNTL_MODE … #define MPLL_MCLK_SEL … #define SS_SSEN … #define SS_DSMODE_EN … #define MPLL_AD_FUNC_CNTL … #define CLKF(x) … #define CLKF_MASK … #define CLKR(x) … #define CLKR_MASK … #define CLKFRAC(x) … #define CLKFRAC_MASK … #define YCLK_POST_DIV(x) … #define YCLK_POST_DIV_MASK … #define IBIAS(x) … #define IBIAS_MASK … #define RESET … #define PDNB … #define MPLL_AD_FUNC_CNTL_2 … #define BYPASS … #define BIAS_GEN_PDNB … #define RESET_EN … #define VCO_MODE … #define MPLL_DQ_FUNC_CNTL … #define MPLL_DQ_FUNC_CNTL_2 … #define GENERAL_PWRMGT … #define GLOBAL_PWRMGT_EN … #define STATIC_PM_EN … #define THERMAL_PROTECTION_DIS … #define THERMAL_PROTECTION_TYPE … #define ENABLE_GEN2PCIE … #define ENABLE_GEN2XSP … #define SW_SMIO_INDEX(x) … #define SW_SMIO_INDEX_MASK … #define SW_SMIO_INDEX_SHIFT … #define LOW_VOLT_D2_ACPI … #define LOW_VOLT_D3_ACPI … #define VOLT_PWRMGT_EN … #define BACKBIAS_PAD_EN … #define BACKBIAS_VALUE … #define DYN_SPREAD_SPECTRUM_EN … #define AC_DC_SW … #define SCLK_PWRMGT_CNTL … #define SCLK_PWRMGT_OFF … #define SCLK_LOW_D1 … #define FIR_RESET … #define FIR_FORCE_TREND_SEL … #define FIR_TREND_MODE … #define DYN_GFX_CLK_OFF_EN … #define GFX_CLK_FORCE_ON … #define GFX_CLK_REQUEST_OFF … #define GFX_CLK_FORCE_OFF … #define GFX_CLK_OFF_ACPI_D1 … #define GFX_CLK_OFF_ACPI_D2 … #define GFX_CLK_OFF_ACPI_D3 … #define DYN_LIGHT_SLEEP_EN … #define MCLK_PWRMGT_CNTL … #define DLL_SPEED(x) … #define DLL_SPEED_MASK … #define MPLL_PWRMGT_OFF … #define DLL_READY … #define MC_INT_CNTL … #define MRDCKA0_PDNB … #define MRDCKA1_PDNB … #define MRDCKB0_PDNB … #define MRDCKB1_PDNB … #define MRDCKC0_PDNB … #define MRDCKC1_PDNB … #define MRDCKD0_PDNB … #define MRDCKD1_PDNB … #define MRDCKA0_RESET … #define MRDCKA1_RESET … #define MRDCKB0_RESET … #define MRDCKB1_RESET … #define MRDCKC0_RESET … #define MRDCKC1_RESET … #define MRDCKD0_RESET … #define MRDCKD1_RESET … #define DLL_READY_READ … #define USE_DISPLAY_GAP … #define USE_DISPLAY_URGENT_NORMAL … #define MPLL_TURNOFF_D2 … #define DLL_CNTL … #define MRDCKA0_BYPASS … #define MRDCKA1_BYPASS … #define MRDCKB0_BYPASS … #define MRDCKB1_BYPASS … #define MRDCKC0_BYPASS … #define MRDCKC1_BYPASS … #define MRDCKD0_BYPASS … #define MRDCKD1_BYPASS … #define CG_AT … #define CG_R(x) … #define CG_R_MASK … #define CG_L(x) … #define CG_L_MASK … #define CG_DISPLAY_GAP_CNTL … #define DISP1_GAP(x) … #define DISP1_GAP_MASK … #define DISP2_GAP(x) … #define DISP2_GAP_MASK … #define VBI_TIMER_COUNT(x) … #define VBI_TIMER_COUNT_MASK … #define VBI_TIMER_UNIT(x) … #define VBI_TIMER_UNIT_MASK … #define DISP1_GAP_MCHG(x) … #define DISP1_GAP_MCHG_MASK … #define DISP2_GAP_MCHG(x) … #define DISP2_GAP_MCHG_MASK … #define CG_BIF_REQ_AND_RSP … #define CG_CLIENT_REQ(x) … #define CG_CLIENT_REQ_MASK … #define CG_CLIENT_REQ_SHIFT … #define CG_CLIENT_RESP(x) … #define CG_CLIENT_RESP_MASK … #define CG_CLIENT_RESP_SHIFT … #define CLIENT_CG_REQ(x) … #define CLIENT_CG_REQ_MASK … #define CLIENT_CG_REQ_SHIFT … #define CLIENT_CG_RESP(x) … #define CLIENT_CG_RESP_MASK … #define CLIENT_CG_RESP_SHIFT … #define CG_SPLL_SPREAD_SPECTRUM … #define SSEN … #define CG_SPLL_SPREAD_SPECTRUM_2 … #define MPLL_SS1 … #define CLKV(x) … #define CLKV_MASK … #define MPLL_SS2 … #define CLKS(x) … #define CLKS_MASK … #define CG_IND_ADDR … #define CG_IND_DATA … /* CGIND regs */ #define CG_CGTT_LOCAL_0 … #define CG_CGTT_LOCAL_1 … #define CG_CGTT_LOCAL_2 … #define CG_CGTT_LOCAL_3 … #define CG_CGLS_TILE_0 … #define CG_CGLS_TILE_1 … #define CG_CGLS_TILE_2 … #define CG_CGLS_TILE_3 … #define CG_CGLS_TILE_4 … #define CG_CGLS_TILE_5 … #define CG_CGLS_TILE_6 … #define CG_CGLS_TILE_7 … #define CG_CGLS_TILE_8 … #define CG_CGLS_TILE_9 … #define CG_CGLS_TILE_10 … #define CG_CGLS_TILE_11 … #define VM_L2_CG … #define MC_CONFIG … #define MC_CONFIG_MCD … #define MC_CG_CONFIG_MCD … #define MC_RD_ENABLE_MCD(x) … #define MC_RD_ENABLE_MCD_MASK … #define MC_HUB_MISC_HUB_CG … #define MC_HUB_MISC_VM_CG … #define MC_HUB_MISC_SIP_CG … #define MC_XPB_CLK_GAT … #define MC_CG_CONFIG … #define MC_RD_ENABLE(x) … #define MC_RD_ENABLE_MASK … #define MC_CITF_MISC_RD_CG … #define MC_CITF_MISC_WR_CG … #define MC_CITF_MISC_VM_CG … #define MEM_LS_ENABLE … #define MC_ARB_BURST_TIME … #define STATE0(x) … #define STATE0_MASK … #define STATE1(x) … #define STATE1_MASK … #define STATE2(x) … #define STATE2_MASK … #define STATE3(x) … #define STATE3_MASK … #define MC_SEQ_RAS_TIMING … #define MC_SEQ_CAS_TIMING … #define MC_SEQ_MISC_TIMING … #define MC_SEQ_MISC_TIMING2 … #define MC_SEQ_RD_CTL_D0 … #define MC_SEQ_RD_CTL_D1 … #define MC_SEQ_WR_CTL_D0 … #define MC_SEQ_WR_CTL_D1 … #define MC_SEQ_STATUS_M … #define PMG_PWRSTATE … #define MC_SEQ_MISC1 … #define MC_SEQ_RESERVE_M … #define MC_PMG_CMD_EMRS … #define MC_SEQ_MISC3 … #define MC_SEQ_MISC5 … #define MC_SEQ_MISC6 … #define MC_SEQ_MISC7 … #define MC_SEQ_CG … #define CG_SEQ_REQ(x) … #define CG_SEQ_REQ_MASK … #define CG_SEQ_REQ_SHIFT … #define CG_SEQ_RESP(x) … #define CG_SEQ_RESP_MASK … #define CG_SEQ_RESP_SHIFT … #define SEQ_CG_REQ(x) … #define SEQ_CG_REQ_MASK … #define SEQ_CG_REQ_SHIFT … #define SEQ_CG_RESP(x) … #define SEQ_CG_RESP_MASK … #define SEQ_CG_RESP_SHIFT … #define MC_SEQ_RAS_TIMING_LP … #define MC_SEQ_CAS_TIMING_LP … #define MC_SEQ_MISC_TIMING_LP … #define MC_SEQ_MISC_TIMING2_LP … #define MC_SEQ_WR_CTL_D0_LP … #define MC_SEQ_WR_CTL_D1_LP … #define MC_SEQ_PMG_CMD_EMRS_LP … #define MC_SEQ_PMG_CMD_MRS_LP … #define MC_PMG_CMD_MRS … #define MC_SEQ_RD_CTL_D0_LP … #define MC_SEQ_RD_CTL_D1_LP … #define MC_PMG_CMD_MRS1 … #define MC_SEQ_PMG_CMD_MRS1_LP … #define CGTS_SM_CTRL_REG … /* Registers */ #define RCU_IND_INDEX … #define RCU_IND_DATA … /* discrete uvd clocks */ #define CG_UPLL_FUNC_CNTL … #define UPLL_RESET_MASK … #define UPLL_SLEEP_MASK … #define UPLL_BYPASS_EN_MASK … #define UPLL_CTLREQ_MASK … #define UPLL_REF_DIV_MASK … #define UPLL_VCO_MODE_MASK … #define UPLL_CTLACK_MASK … #define UPLL_CTLACK2_MASK … #define CG_UPLL_FUNC_CNTL_2 … #define UPLL_PDIV_A(x) … #define UPLL_PDIV_A_MASK … #define UPLL_PDIV_B(x) … #define UPLL_PDIV_B_MASK … #define VCLK_SRC_SEL(x) … #define VCLK_SRC_SEL_MASK … #define DCLK_SRC_SEL(x) … #define DCLK_SRC_SEL_MASK … #define CG_UPLL_FUNC_CNTL_3 … #define UPLL_FB_DIV(x) … #define UPLL_FB_DIV_MASK … #define CG_UPLL_FUNC_CNTL_4 … #define UPLL_SPARE_ISPARE9 … #define CG_UPLL_SPREAD_SPECTRUM … #define SSEN_MASK … /* fusion uvd clocks */ #define CG_DCLK_CNTL … #define DCLK_DIVIDER_MASK … #define DCLK_DIR_CNTL_EN … #define CG_DCLK_STATUS … #define DCLK_STATUS … #define CG_VCLK_CNTL … #define CG_VCLK_STATUS … #define CG_SCRATCH1 … #define RLC_CNTL … #define RLC_ENABLE … #define GFX_POWER_GATING_ENABLE … #define GFX_POWER_GATING_SRC … #define DYN_PER_SIMD_PG_ENABLE … #define LB_CNT_SPIM_ACTIVE … #define LOAD_BALANCE_ENABLE … #define RLC_HB_BASE … #define RLC_HB_CNTL … #define RLC_HB_RPTR … #define RLC_HB_WPTR … #define RLC_HB_WPTR_LSB_ADDR … #define RLC_HB_WPTR_MSB_ADDR … #define RLC_MC_CNTL … #define RLC_UCODE_CNTL … #define RLC_UCODE_ADDR … #define RLC_UCODE_DATA … /* new for TN */ #define TN_RLC_SAVE_AND_RESTORE_BASE … #define TN_RLC_LB_CNTR_MAX … #define TN_RLC_LB_CNTR_INIT … #define TN_RLC_CLEAR_STATE_RESTORE_BASE … #define TN_RLC_LB_INIT_SIMD_MASK … #define TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK … #define TN_RLC_LB_PARAMS … #define GRBM_GFX_INDEX … #define INSTANCE_INDEX(x) … #define SE_INDEX(x) … #define INSTANCE_BROADCAST_WRITES … #define SE_BROADCAST_WRITES … #define RLC_GFX_INDEX … #define CC_GC_SHADER_PIPE_CONFIG … #define WRITE_DIS … #define CC_RB_BACKEND_DISABLE … #define BACKEND_DISABLE(x) … #define GB_ADDR_CONFIG … #define NUM_PIPES(x) … #define NUM_PIPES_MASK … #define PIPE_INTERLEAVE_SIZE(x) … #define BANK_INTERLEAVE_SIZE(x) … #define NUM_SHADER_ENGINES(x) … #define SHADER_ENGINE_TILE_SIZE(x) … #define NUM_GPUS(x) … #define MULTI_GPU_TILE_SIZE(x) … #define ROW_SIZE(x) … #define GB_BACKEND_MAP … #define DMIF_ADDR_CONFIG … #define HDP_ADDR_CONFIG … #define HDP_MISC_CNTL … #define HDP_FLUSH_INVALIDATE_CACHE … #define CC_SYS_RB_BACKEND_DISABLE … #define GC_USER_RB_BACKEND_DISABLE … #define CGTS_SYS_TCC_DISABLE … #define CGTS_TCC_DISABLE … #define CGTS_USER_SYS_TCC_DISABLE … #define CGTS_USER_TCC_DISABLE … #define CONFIG_MEMSIZE … #define BIF_FB_EN … #define FB_READ_EN … #define FB_WRITE_EN … #define CP_STRMOUT_CNTL … #define CP_COHER_CNTL … #define CP_COHER_SIZE … #define CP_COHER_BASE … #define CP_STALLED_STAT1 … #define CP_STALLED_STAT2 … #define CP_BUSY_STAT … #define CP_STAT … #define CP_ME_CNTL … #define CP_ME_HALT … #define CP_PFP_HALT … #define CP_ME_RAM_DATA … #define CP_ME_RAM_RADDR … #define CP_ME_RAM_WADDR … #define CP_MEQ_THRESHOLDS … #define STQ_SPLIT(x) … #define CP_PERFMON_CNTL … #define CP_PFP_UCODE_ADDR … #define CP_PFP_UCODE_DATA … #define CP_QUEUE_THRESHOLDS … #define ROQ_IB1_START(x) … #define ROQ_IB2_START(x) … #define CP_RB_BASE … #define CP_RB_CNTL … #define RB_BUFSZ(x) … #define RB_BLKSZ(x) … #define RB_NO_UPDATE … #define RB_RPTR_WR_ENA … #define BUF_SWAP_32BIT … #define CP_RB_RPTR … #define CP_RB_RPTR_ADDR … #define RB_RPTR_SWAP(x) … #define CP_RB_RPTR_ADDR_HI … #define CP_RB_RPTR_WR … #define CP_RB_WPTR … #define CP_RB_WPTR_ADDR … #define CP_RB_WPTR_ADDR_HI … #define CP_RB_WPTR_DELAY … #define CP_SEM_WAIT_TIMER … #define CP_SEM_INCOMPLETE_TIMER_CNTL … #define CP_DEBUG … /* Audio clocks */ #define DCCG_AUDIO_DTO_SOURCE … #define DCCG_AUDIO_DTO0_SOURCE_SEL(x) … #define DCCG_AUDIO_DTO_SEL … #define DCCG_AUDIO_DTO0_PHASE … #define DCCG_AUDIO_DTO0_MODULE … #define DCCG_AUDIO_DTO0_LOAD … #define DCCG_AUDIO_DTO0_CNTL … #define DCCG_AUDIO_DTO_WALLCLOCK_RATIO(x) … #define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK … #define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_SHIFT … #define DCCG_AUDIO_DTO1_PHASE … #define DCCG_AUDIO_DTO1_MODULE … #define DCCG_AUDIO_DTO1_LOAD … #define DCCG_AUDIO_DTO1_CNTL … #define DCCG_AUDIO_DTO1_USE_512FBR_DTO … #define DCE41_DENTIST_DISPCLK_CNTL … #define DENTIST_DPREFCLK_WDIVIDER(x) … #define DENTIST_DPREFCLK_WDIVIDER_MASK … #define DENTIST_DPREFCLK_WDIVIDER_SHIFT … /* DCE 4.0 AFMT */ #define HDMI_CONTROL … #define HDMI_KEEPOUT_MODE … #define HDMI_PACKET_GEN_VERSION … #define HDMI_ERROR_ACK … #define HDMI_ERROR_MASK … #define HDMI_DEEP_COLOR_ENABLE … #define HDMI_DEEP_COLOR_DEPTH(x) … #define HDMI_24BIT_DEEP_COLOR … #define HDMI_30BIT_DEEP_COLOR … #define HDMI_36BIT_DEEP_COLOR … #define HDMI_DEEP_COLOR_DEPTH_MASK … #define HDMI_STATUS … #define HDMI_ACTIVE_AVMUTE … #define HDMI_AUDIO_PACKET_ERROR … #define HDMI_VBI_PACKET_ERROR … #define HDMI_AUDIO_PACKET_CONTROL … #define HDMI_AUDIO_DELAY_EN(x) … #define HDMI_AUDIO_PACKETS_PER_LINE(x) … #define HDMI_ACR_PACKET_CONTROL … #define HDMI_ACR_SEND … #define HDMI_ACR_CONT … #define HDMI_ACR_SELECT(x) … #define HDMI_ACR_HW … #define HDMI_ACR_32 … #define HDMI_ACR_44 … #define HDMI_ACR_48 … #define HDMI_ACR_SOURCE … #define HDMI_ACR_AUTO_SEND … #define HDMI_ACR_N_MULTIPLE(x) … #define HDMI_ACR_X1 … #define HDMI_ACR_X2 … #define HDMI_ACR_X4 … #define HDMI_ACR_AUDIO_PRIORITY … #define HDMI_VBI_PACKET_CONTROL … #define HDMI_NULL_SEND … #define HDMI_GC_SEND … #define HDMI_GC_CONT … #define HDMI_INFOFRAME_CONTROL0 … #define HDMI_AVI_INFO_SEND … #define HDMI_AVI_INFO_CONT … #define HDMI_AUDIO_INFO_SEND … #define HDMI_AUDIO_INFO_CONT … #define HDMI_MPEG_INFO_SEND … #define HDMI_MPEG_INFO_CONT … #define HDMI_INFOFRAME_CONTROL1 … #define HDMI_AVI_INFO_LINE(x) … #define HDMI_AVI_INFO_LINE_MASK … #define HDMI_AUDIO_INFO_LINE(x) … #define HDMI_MPEG_INFO_LINE(x) … #define HDMI_GENERIC_PACKET_CONTROL … #define HDMI_GENERIC0_SEND … #define HDMI_GENERIC0_CONT … #define HDMI_GENERIC1_SEND … #define HDMI_GENERIC1_CONT … #define HDMI_GENERIC0_LINE(x) … #define HDMI_GENERIC1_LINE(x) … #define HDMI_GC … #define HDMI_GC_AVMUTE … #define HDMI_GC_AVMUTE_CONT … #define AFMT_AUDIO_PACKET_CONTROL2 … #define AFMT_AUDIO_LAYOUT_OVRD … #define AFMT_AUDIO_LAYOUT_SELECT … #define AFMT_60958_CS_SOURCE … #define AFMT_AUDIO_CHANNEL_ENABLE(x) … #define AFMT_DP_AUDIO_STREAM_ID(x) … #define AFMT_AVI_INFO0 … #define AFMT_AVI_INFO_CHECKSUM(x) … #define AFMT_AVI_INFO_S(x) … #define AFMT_AVI_INFO_B(x) … #define AFMT_AVI_INFO_A(x) … #define AFMT_AVI_INFO_Y(x) … #define AFMT_AVI_INFO_Y_RGB … #define AFMT_AVI_INFO_Y_YCBCR422 … #define AFMT_AVI_INFO_Y_YCBCR444 … #define AFMT_AVI_INFO_Y_A_B_S(x) … #define AFMT_AVI_INFO_R(x) … #define AFMT_AVI_INFO_M(x) … #define AFMT_AVI_INFO_C(x) … #define AFMT_AVI_INFO_C_M_R(x) … #define AFMT_AVI_INFO_SC(x) … #define AFMT_AVI_INFO_Q(x) … #define AFMT_AVI_INFO_EC(x) … #define AFMT_AVI_INFO_ITC(x) … #define AFMT_AVI_INFO_ITC_EC_Q_SC(x) … #define AFMT_AVI_INFO1 … #define AFMT_AVI_INFO_VIC(x) … #define AFMT_AVI_INFO_PR(x) … #define AFMT_AVI_INFO_CN(x) … #define AFMT_AVI_INFO_YQ(x) … #define AFMT_AVI_INFO_TOP(x) … #define AFMT_AVI_INFO2 … #define AFMT_AVI_INFO_BOTTOM(x) … #define AFMT_AVI_INFO_LEFT(x) … #define AFMT_AVI_INFO3 … #define AFMT_AVI_INFO_RIGHT(x) … #define AFMT_AVI_INFO_VERSION(x) … #define AFMT_MPEG_INFO0 … #define AFMT_MPEG_INFO_CHECKSUM(x) … #define AFMT_MPEG_INFO_MB0(x) … #define AFMT_MPEG_INFO_MB1(x) … #define AFMT_MPEG_INFO_MB2(x) … #define AFMT_MPEG_INFO1 … #define AFMT_MPEG_INFO_MB3(x) … #define AFMT_MPEG_INFO_MF(x) … #define AFMT_MPEG_INFO_FR(x) … #define AFMT_GENERIC0_HDR … #define AFMT_GENERIC0_0 … #define AFMT_GENERIC0_1 … #define AFMT_GENERIC0_2 … #define AFMT_GENERIC0_3 … #define AFMT_GENERIC0_4 … #define AFMT_GENERIC0_5 … #define AFMT_GENERIC0_6 … #define AFMT_GENERIC1_HDR … #define AFMT_GENERIC1_0 … #define AFMT_GENERIC1_1 … #define AFMT_GENERIC1_2 … #define AFMT_GENERIC1_3 … #define AFMT_GENERIC1_4 … #define AFMT_GENERIC1_5 … #define AFMT_GENERIC1_6 … #define HDMI_ACR_32_0 … #define HDMI_ACR_CTS_32(x) … #define HDMI_ACR_32_1 … #define HDMI_ACR_N_32(x) … #define HDMI_ACR_44_0 … #define HDMI_ACR_CTS_44(x) … #define HDMI_ACR_44_1 … #define HDMI_ACR_N_44(x) … #define HDMI_ACR_48_0 … #define HDMI_ACR_CTS_48(x) … #define HDMI_ACR_48_1 … #define HDMI_ACR_N_48(x) … #define HDMI_ACR_STATUS_0 … #define HDMI_ACR_STATUS_1 … #define AFMT_AUDIO_INFO0 … #define AFMT_AUDIO_INFO_CHECKSUM(x) … #define AFMT_AUDIO_INFO_CC(x) … #define AFMT_AUDIO_INFO_CT(x) … #define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) … #define AFMT_AUDIO_INFO_CXT(x) … #define AFMT_AUDIO_INFO1 … #define AFMT_AUDIO_INFO_CA(x) … #define AFMT_AUDIO_INFO_LSV(x) … #define AFMT_AUDIO_INFO_DM_INH(x) … #define AFMT_AUDIO_INFO_DM_INH_LSV(x) … #define AFMT_AUDIO_INFO_LFEBPL(x) … #define AFMT_60958_0 … #define AFMT_60958_CS_A(x) … #define AFMT_60958_CS_B(x) … #define AFMT_60958_CS_C(x) … #define AFMT_60958_CS_D(x) … #define AFMT_60958_CS_MODE(x) … #define AFMT_60958_CS_CATEGORY_CODE(x) … #define AFMT_60958_CS_SOURCE_NUMBER(x) … #define AFMT_60958_CS_CHANNEL_NUMBER_L(x) … #define AFMT_60958_CS_SAMPLING_FREQUENCY(x) … #define AFMT_60958_CS_CLOCK_ACCURACY(x) … #define AFMT_60958_1 … #define AFMT_60958_CS_WORD_LENGTH(x) … #define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) … #define AFMT_60958_CS_VALID_L(x) … #define AFMT_60958_CS_VALID_R(x) … #define AFMT_60958_CS_CHANNEL_NUMBER_R(x) … #define AFMT_AUDIO_CRC_CONTROL … #define AFMT_AUDIO_CRC_EN … #define AFMT_RAMP_CONTROL0 … #define AFMT_RAMP_MAX_COUNT(x) … #define AFMT_RAMP_DATA_SIGN … #define AFMT_RAMP_CONTROL1 … #define AFMT_RAMP_MIN_COUNT(x) … #define AFMT_AUDIO_TEST_CH_DISABLE(x) … #define AFMT_RAMP_CONTROL2 … #define AFMT_RAMP_INC_COUNT(x) … #define AFMT_RAMP_CONTROL3 … #define AFMT_RAMP_DEC_COUNT(x) … #define AFMT_60958_2 … #define AFMT_60958_CS_CHANNEL_NUMBER_2(x) … #define AFMT_60958_CS_CHANNEL_NUMBER_3(x) … #define AFMT_60958_CS_CHANNEL_NUMBER_4(x) … #define AFMT_60958_CS_CHANNEL_NUMBER_5(x) … #define AFMT_60958_CS_CHANNEL_NUMBER_6(x) … #define AFMT_60958_CS_CHANNEL_NUMBER_7(x) … #define AFMT_STATUS … #define AFMT_AUDIO_ENABLE … #define AFMT_AUDIO_HBR_ENABLE … #define AFMT_AZ_FORMAT_WTRIG … #define AFMT_AZ_FORMAT_WTRIG_INT … #define AFMT_AZ_AUDIO_ENABLE_CHG … #define AFMT_AUDIO_PACKET_CONTROL … #define AFMT_AUDIO_SAMPLE_SEND … #define AFMT_RESET_FIFO_WHEN_AUDIO_DIS … #define AFMT_AUDIO_TEST_EN … #define AFMT_AUDIO_CHANNEL_SWAP … #define AFMT_60958_CS_UPDATE … #define AFMT_AZ_AUDIO_ENABLE_CHG_MASK … #define AFMT_AZ_FORMAT_WTRIG_MASK … #define AFMT_AZ_FORMAT_WTRIG_ACK … #define AFMT_AZ_AUDIO_ENABLE_CHG_ACK … #define AFMT_VBI_PACKET_CONTROL … #define AFMT_GENERIC0_UPDATE … #define AFMT_INFOFRAME_CONTROL0 … #define AFMT_AUDIO_INFO_SOURCE … #define AFMT_AUDIO_INFO_UPDATE … #define AFMT_MPEG_INFO_UPDATE … #define AFMT_GENERIC0_7 … /* DCE4/5 ELD audio interface */ #define AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER … #define SPEAKER_ALLOCATION(x) … #define SPEAKER_ALLOCATION_MASK … #define SPEAKER_ALLOCATION_SHIFT … #define HDMI_CONNECTION … #define DP_CONNECTION … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 … #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 … #define MAX_CHANNELS(x) … /* max channels minus one. 7 = 8 channels */ #define SUPPORTED_FREQUENCIES(x) … #define DESCRIPTOR_BYTE_2(x) … #define SUPPORTED_FREQUENCIES_STEREO(x) … /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO * bit0 = 32 kHz * bit1 = 44.1 kHz * bit2 = 48 kHz * bit3 = 88.2 kHz * bit4 = 96 kHz * bit5 = 176.4 kHz * bit6 = 192 kHz */ #define AZ_CHANNEL_COUNT_CONTROL … #define HBR_CHANNEL_COUNT(x) … #define COMPRESSED_CHANNEL_COUNT(x) … /* HBR_CHANNEL_COUNT, COMPRESSED_CHANNEL_COUNT * 0 = use stream header * 1-7 = channel count - 1 */ #define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC … #define VIDEO_LIPSYNC(x) … #define AUDIO_LIPSYNC(x) … /* VIDEO_LIPSYNC, AUDIO_LIPSYNC * 0 = invalid * x = legal delay value * 255 = sync not supported */ #define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR … #define HBR_CAPABLE … #define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0 … #define DISPLAY0_TYPE(x) … #define DISPLAY_TYPE_NONE … #define DISPLAY_TYPE_HDMI … #define DISPLAY_TYPE_DP … #define DISPLAY0_ID(x) … #define DISPLAY1_TYPE(x) … #define DISPLAY1_ID(x) … #define DISPLAY2_TYPE(x) … #define DISPLAY2_ID(x) … #define DISPLAY3_TYPE(x) … #define DISPLAY3_ID(x) … #define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1 … #define DISPLAY4_TYPE(x) … #define DISPLAY4_ID(x) … #define DISPLAY5_TYPE(x) … #define DISPLAY5_ID(x) … #define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_NUMBER … #define NUMBER_OF_DISPLAY_ID(x) … #define AZ_HOT_PLUG_CONTROL … #define AZ_FORCE_CODEC_WAKE … #define PIN0_JACK_DETECTION_ENABLE … #define PIN1_JACK_DETECTION_ENABLE … #define PIN2_JACK_DETECTION_ENABLE … #define PIN3_JACK_DETECTION_ENABLE … #define PIN0_UNSOLICITED_RESPONSE_ENABLE … #define PIN1_UNSOLICITED_RESPONSE_ENABLE … #define PIN2_UNSOLICITED_RESPONSE_ENABLE … #define PIN3_UNSOLICITED_RESPONSE_ENABLE … #define CODEC_HOT_PLUG_ENABLE … #define PIN0_AUDIO_ENABLED … #define PIN1_AUDIO_ENABLED … #define PIN2_AUDIO_ENABLED … #define PIN3_AUDIO_ENABLED … #define AUDIO_ENABLED … #define GC_USER_SHADER_PIPE_CONFIG … #define INACTIVE_QD_PIPES(x) … #define INACTIVE_QD_PIPES_MASK … #define INACTIVE_SIMDS(x) … #define INACTIVE_SIMDS_MASK … #define GRBM_CNTL … #define GRBM_READ_TIMEOUT(x) … #define GRBM_SOFT_RESET … #define SOFT_RESET_CP … #define SOFT_RESET_CB … #define SOFT_RESET_DB … #define SOFT_RESET_PA … #define SOFT_RESET_SC … #define SOFT_RESET_SPI … #define SOFT_RESET_SH … #define SOFT_RESET_SX … #define SOFT_RESET_TC … #define SOFT_RESET_TA … #define SOFT_RESET_VC … #define SOFT_RESET_VGT … #define GRBM_STATUS … #define CMDFIFO_AVAIL_MASK … #define SRBM_RQ_PENDING … #define CF_RQ_PENDING … #define PF_RQ_PENDING … #define GRBM_EE_BUSY … #define SX_CLEAN … #define DB_CLEAN … #define CB_CLEAN … #define TA_BUSY … #define VGT_BUSY_NO_DMA … #define VGT_BUSY … #define SX_BUSY … #define SH_BUSY … #define SPI_BUSY … #define SC_BUSY … #define PA_BUSY … #define DB_BUSY … #define CP_COHERENCY_BUSY … #define CP_BUSY … #define CB_BUSY … #define GUI_ACTIVE … #define GRBM_STATUS_SE0 … #define GRBM_STATUS_SE1 … #define SE_SX_CLEAN … #define SE_DB_CLEAN … #define SE_CB_CLEAN … #define SE_TA_BUSY … #define SE_SX_BUSY … #define SE_SPI_BUSY … #define SE_SH_BUSY … #define SE_SC_BUSY … #define SE_DB_BUSY … #define SE_CB_BUSY … /* evergreen */ #define CG_THERMAL_CTRL … #define TOFFSET_MASK … #define TOFFSET_SHIFT … #define DIG_THERM_DPM(x) … #define DIG_THERM_DPM_MASK … #define DIG_THERM_DPM_SHIFT … #define CG_THERMAL_INT … #define DIG_THERM_INTH(x) … #define DIG_THERM_INTH_MASK … #define DIG_THERM_INTH_SHIFT … #define DIG_THERM_INTL(x) … #define DIG_THERM_INTL_MASK … #define DIG_THERM_INTL_SHIFT … #define THERM_INT_MASK_HIGH … #define THERM_INT_MASK_LOW … #define TN_CG_THERMAL_INT_CTRL … #define TN_DIG_THERM_INTH(x) … #define TN_DIG_THERM_INTH_MASK … #define TN_DIG_THERM_INTH_SHIFT … #define TN_DIG_THERM_INTL(x) … #define TN_DIG_THERM_INTL_MASK … #define TN_DIG_THERM_INTL_SHIFT … #define TN_THERM_INT_MASK_HIGH … #define TN_THERM_INT_MASK_LOW … #define CG_MULT_THERMAL_STATUS … #define ASIC_T(x) … #define ASIC_T_MASK … #define ASIC_T_SHIFT … #define CG_TS0_STATUS … #define TS0_ADC_DOUT_MASK … #define TS0_ADC_DOUT_SHIFT … /* APU */ #define CG_THERMAL_STATUS … #define HDP_HOST_PATH_CNTL … #define HDP_NONSURFACE_BASE … #define HDP_NONSURFACE_INFO … #define HDP_NONSURFACE_SIZE … #define HDP_MEM_COHERENCY_FLUSH_CNTL … #define HDP_REG_COHERENCY_FLUSH_CNTL … #define HDP_TILING_CONFIG … #define MC_SHARED_CHMAP … #define NOOFCHAN_SHIFT … #define NOOFCHAN_MASK … #define MC_SHARED_CHREMAP … #define MC_SHARED_BLACKOUT_CNTL … #define BLACKOUT_MODE_MASK … #define MC_ARB_RAMCFG … #define NOOFBANK_SHIFT … #define NOOFBANK_MASK … #define NOOFRANK_SHIFT … #define NOOFRANK_MASK … #define NOOFROWS_SHIFT … #define NOOFROWS_MASK … #define NOOFCOLS_SHIFT … #define NOOFCOLS_MASK … #define CHANSIZE_SHIFT … #define CHANSIZE_MASK … #define BURSTLENGTH_SHIFT … #define BURSTLENGTH_MASK … #define CHANSIZE_OVERRIDE … #define FUS_MC_ARB_RAMCFG … #define MC_VM_AGP_TOP … #define MC_VM_AGP_BOT … #define MC_VM_AGP_BASE … #define MC_VM_FB_LOCATION … #define MC_FUS_VM_FB_OFFSET … #define MC_VM_MB_L1_TLB0_CNTL … #define MC_VM_MB_L1_TLB1_CNTL … #define MC_VM_MB_L1_TLB2_CNTL … #define MC_VM_MB_L1_TLB3_CNTL … #define ENABLE_L1_TLB … #define ENABLE_L1_FRAGMENT_PROCESSING … #define SYSTEM_ACCESS_MODE_PA_ONLY … #define SYSTEM_ACCESS_MODE_USE_SYS_MAP … #define SYSTEM_ACCESS_MODE_IN_SYS … #define SYSTEM_ACCESS_MODE_NOT_IN_SYS … #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU … #define EFFECTIVE_L1_TLB_SIZE(x) … #define EFFECTIVE_L1_QUEUE_SIZE(x) … #define MC_VM_MD_L1_TLB0_CNTL … #define MC_VM_MD_L1_TLB1_CNTL … #define MC_VM_MD_L1_TLB2_CNTL … #define MC_VM_MD_L1_TLB3_CNTL … #define FUS_MC_VM_MD_L1_TLB0_CNTL … #define FUS_MC_VM_MD_L1_TLB1_CNTL … #define FUS_MC_VM_MD_L1_TLB2_CNTL … #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR … #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR … #define MC_VM_SYSTEM_APERTURE_LOW_ADDR … #define PA_CL_ENHANCE … #define CLIP_VTX_REORDER_ENA … #define NUM_CLIP_SEQ(x) … #define PA_SC_ENHANCE … #define PA_SC_AA_CONFIG … #define MSAA_NUM_SAMPLES_SHIFT … #define MSAA_NUM_SAMPLES_MASK … #define PA_SC_CLIPRECT_RULE … #define PA_SC_EDGERULE … #define PA_SC_FIFO_SIZE … #define SC_PRIM_FIFO_SIZE(x) … #define SC_HIZ_TILE_FIFO_SIZE(x) … #define SC_EARLYZ_TILE_FIFO_SIZE(x) … #define PA_SC_FORCE_EOV_MAX_CNTS … #define FORCE_EOV_MAX_CLK_CNT(x) … #define FORCE_EOV_MAX_REZ_CNT(x) … #define PA_SC_LINE_STIPPLE … #define PA_SU_LINE_STIPPLE_VALUE … #define PA_SC_LINE_STIPPLE_STATE … #define SCRATCH_REG0 … #define SCRATCH_REG1 … #define SCRATCH_REG2 … #define SCRATCH_REG3 … #define SCRATCH_REG4 … #define SCRATCH_REG5 … #define SCRATCH_REG6 … #define SCRATCH_REG7 … #define SCRATCH_UMSK … #define SCRATCH_ADDR … #define SMX_SAR_CTL0 … #define SMX_DC_CTL0 … #define USE_HASH_FUNCTION … #define NUMBER_OF_SETS(x) … #define FLUSH_ALL_ON_EVENT … #define STALL_ON_EVENT … #define SMX_EVENT_CTL … #define ES_FLUSH_CTL(x) … #define GS_FLUSH_CTL(x) … #define ACK_FLUSH_CTL(x) … #define SYNC_FLUSH_CTL … #define SPI_CONFIG_CNTL … #define GPR_WRITE_PRIORITY(x) … #define SPI_CONFIG_CNTL_1 … #define VTX_DONE_DELAY(x) … #define INTERP_ONE_PRIM_PER_ROW … #define SPI_INPUT_Z … #define SPI_PS_IN_CONTROL_0 … #define NUM_INTERP(x) … #define POSITION_ENA … #define POSITION_CENTROID … #define POSITION_ADDR(x) … #define PARAM_GEN(x) … #define PARAM_GEN_ADDR(x) … #define BARYC_SAMPLE_CNTL(x) … #define PERSP_GRADIENT_ENA … #define LINEAR_GRADIENT_ENA … #define POSITION_SAMPLE … #define BARYC_AT_SAMPLE_ENA … #define SQ_CONFIG … #define VC_ENABLE … #define EXPORT_SRC_C … #define CS_PRIO(x) … #define LS_PRIO(x) … #define HS_PRIO(x) … #define PS_PRIO(x) … #define VS_PRIO(x) … #define GS_PRIO(x) … #define ES_PRIO(x) … #define SQ_GPR_RESOURCE_MGMT_1 … #define NUM_PS_GPRS(x) … #define NUM_VS_GPRS(x) … #define NUM_CLAUSE_TEMP_GPRS(x) … #define SQ_GPR_RESOURCE_MGMT_2 … #define NUM_GS_GPRS(x) … #define NUM_ES_GPRS(x) … #define SQ_GPR_RESOURCE_MGMT_3 … #define NUM_HS_GPRS(x) … #define NUM_LS_GPRS(x) … #define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 … #define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 … #define SQ_THREAD_RESOURCE_MGMT … #define NUM_PS_THREADS(x) … #define NUM_VS_THREADS(x) … #define NUM_GS_THREADS(x) … #define NUM_ES_THREADS(x) … #define SQ_THREAD_RESOURCE_MGMT_2 … #define NUM_HS_THREADS(x) … #define NUM_LS_THREADS(x) … #define SQ_STACK_RESOURCE_MGMT_1 … #define NUM_PS_STACK_ENTRIES(x) … #define NUM_VS_STACK_ENTRIES(x) … #define SQ_STACK_RESOURCE_MGMT_2 … #define NUM_GS_STACK_ENTRIES(x) … #define NUM_ES_STACK_ENTRIES(x) … #define SQ_STACK_RESOURCE_MGMT_3 … #define NUM_HS_STACK_ENTRIES(x) … #define NUM_LS_STACK_ENTRIES(x) … #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ … #define SQ_DYN_GPR_SIMD_LOCK_EN … #define SQ_STATIC_THREAD_MGMT_1 … #define SQ_STATIC_THREAD_MGMT_2 … #define SQ_STATIC_THREAD_MGMT_3 … #define SQ_LDS_RESOURCE_MGMT … #define SQ_MS_FIFO_SIZES … #define CACHE_FIFO_SIZE(x) … #define FETCH_FIFO_HIWATER(x) … #define DONE_FIFO_HIWATER(x) … #define ALU_UPDATE_FIFO_HIWATER(x) … #define SX_DEBUG_1 … #define ENABLE_NEW_SMX_ADDRESS … #define SX_EXPORT_BUFFER_SIZES … #define COLOR_BUFFER_SIZE(x) … #define POSITION_BUFFER_SIZE(x) … #define SMX_BUFFER_SIZE(x) … #define SX_MEMORY_EXPORT_BASE … #define SX_MISC … #define CB_PERF_CTR0_SEL_0 … #define CB_PERF_CTR0_SEL_1 … #define CB_PERF_CTR1_SEL_0 … #define CB_PERF_CTR1_SEL_1 … #define CB_PERF_CTR2_SEL_0 … #define CB_PERF_CTR2_SEL_1 … #define CB_PERF_CTR3_SEL_0 … #define CB_PERF_CTR3_SEL_1 … #define TA_CNTL_AUX … #define DISABLE_CUBE_WRAP … #define DISABLE_CUBE_ANISO … #define SYNC_GRADIENT … #define SYNC_WALKER … #define SYNC_ALIGNER … #define TCP_CHAN_STEER_LO … #define TCP_CHAN_STEER_HI … #define VGT_CACHE_INVALIDATION … #define CACHE_INVALIDATION(x) … #define VC_ONLY … #define TC_ONLY … #define VC_AND_TC … #define AUTO_INVLD_EN(x) … #define NO_AUTO … #define ES_AUTO … #define GS_AUTO … #define ES_AND_GS_AUTO … #define VGT_GS_VERTEX_REUSE … #define VGT_NUM_INSTANCES … #define VGT_OUT_DEALLOC_CNTL … #define DEALLOC_DIST_MASK … #define VGT_VERTEX_REUSE_BLOCK_CNTL … #define VTX_REUSE_DEPTH_MASK … #define VM_CONTEXT0_CNTL … #define ENABLE_CONTEXT … #define PAGE_TABLE_DEPTH(x) … #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT … #define VM_CONTEXT1_CNTL … #define VM_CONTEXT1_CNTL2 … #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT0_PAGE_TABLE_END_ADDR … #define VM_CONTEXT0_PAGE_TABLE_START_ADDR … #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR … #define VM_CONTEXT0_REQUEST_RESPONSE … #define REQUEST_TYPE(x) … #define RESPONSE_TYPE_MASK … #define RESPONSE_TYPE_SHIFT … #define VM_L2_CNTL … #define ENABLE_L2_CACHE … #define ENABLE_L2_FRAGMENT_PROCESSING … #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE … #define EFFECTIVE_L2_QUEUE_SIZE(x) … #define VM_L2_CNTL2 … #define INVALIDATE_ALL_L1_TLBS … #define INVALIDATE_L2_CACHE … #define VM_L2_CNTL3 … #define BANK_SELECT(x) … #define CACHE_UPDATE_MODE(x) … #define VM_L2_STATUS … #define L2_BUSY … #define VM_CONTEXT1_PROTECTION_FAULT_ADDR … #define VM_CONTEXT1_PROTECTION_FAULT_STATUS … #define WAIT_UNTIL … #define SRBM_STATUS … #define RLC_RQ_PENDING … #define GRBM_RQ_PENDING … #define VMC_BUSY … #define MCB_BUSY … #define MCB_NON_DISPLAY_BUSY … #define MCC_BUSY … #define MCD_BUSY … #define SEM_BUSY … #define RLC_BUSY … #define IH_BUSY … #define SRBM_STATUS2 … #define DMA_BUSY … #define SRBM_SOFT_RESET … #define SRBM_SOFT_RESET_ALL_MASK … #define SOFT_RESET_BIF … #define SOFT_RESET_CG … #define SOFT_RESET_DC … #define SOFT_RESET_GRBM … #define SOFT_RESET_HDP … #define SOFT_RESET_IH … #define SOFT_RESET_MC … #define SOFT_RESET_RLC … #define SOFT_RESET_ROM … #define SOFT_RESET_SEM … #define SOFT_RESET_VMC … #define SOFT_RESET_DMA … #define SOFT_RESET_TST … #define SOFT_RESET_REGBB … #define SOFT_RESET_ORB … #define SRBM_READ_ERROR … #define SRBM_INT_CNTL … #define SRBM_INT_ACK … /* display watermarks */ #define DC_LB_MEMORY_SPLIT … #define PRIORITY_A_CNT … #define PRIORITY_MARK_MASK … #define PRIORITY_OFF … #define PRIORITY_ALWAYS_ON … #define PRIORITY_B_CNT … #define PIPE0_ARBITRATION_CONTROL3 … #define LATENCY_WATERMARK_MASK(x) … #define PIPE0_LATENCY_CONTROL … #define LATENCY_LOW_WATERMARK(x) … #define LATENCY_HIGH_WATERMARK(x) … #define PIPE0_DMIF_BUFFER_CONTROL … #define DMIF_BUFFERS_ALLOCATED(x) … #define DMIF_BUFFERS_ALLOCATED_COMPLETED … #define IH_RB_CNTL … #define IH_RB_ENABLE … #define IH_IB_SIZE(x) … #define IH_RB_FULL_DRAIN_ENABLE … #define IH_WPTR_WRITEBACK_ENABLE … #define IH_WPTR_WRITEBACK_TIMER(x) … #define IH_WPTR_OVERFLOW_ENABLE … #define IH_WPTR_OVERFLOW_CLEAR … #define IH_RB_BASE … #define IH_RB_RPTR … #define IH_RB_WPTR … #define RB_OVERFLOW … #define WPTR_OFFSET_MASK … #define IH_RB_WPTR_ADDR_HI … #define IH_RB_WPTR_ADDR_LO … #define IH_CNTL … #define ENABLE_INTR … #define IH_MC_SWAP(x) … #define IH_MC_SWAP_NONE … #define IH_MC_SWAP_16BIT … #define IH_MC_SWAP_32BIT … #define IH_MC_SWAP_64BIT … #define RPTR_REARM … #define MC_WRREQ_CREDIT(x) … #define MC_WR_CLEAN_CNT(x) … #define CP_INT_CNTL … #define CNTX_BUSY_INT_ENABLE … #define CNTX_EMPTY_INT_ENABLE … #define SCRATCH_INT_ENABLE … #define TIME_STAMP_INT_ENABLE … #define IB2_INT_ENABLE … #define IB1_INT_ENABLE … #define RB_INT_ENABLE … #define CP_INT_STATUS … #define SCRATCH_INT_STAT … #define TIME_STAMP_INT_STAT … #define IB2_INT_STAT … #define IB1_INT_STAT … #define RB_INT_STAT … #define GRBM_INT_CNTL … #define RDERR_INT_ENABLE … #define GUI_IDLE_INT_ENABLE … /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ #define CRTC_STATUS_FRAME_COUNT … /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ #define VLINE_STATUS … #define VLINE_OCCURRED … #define VLINE_ACK … #define VLINE_STAT … #define VLINE_INTERRUPT … #define VLINE_INTERRUPT_TYPE … /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ #define VBLANK_STATUS … #define VBLANK_OCCURRED … #define VBLANK_ACK … #define VBLANK_STAT … #define VBLANK_INTERRUPT … #define VBLANK_INTERRUPT_TYPE … /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ #define INT_MASK … #define VBLANK_INT_MASK … #define VLINE_INT_MASK … #define DISP_INTERRUPT_STATUS … #define LB_D1_VLINE_INTERRUPT … #define LB_D1_VBLANK_INTERRUPT … #define DC_HPD1_INTERRUPT … #define DC_HPD1_RX_INTERRUPT … #define DACA_AUTODETECT_INTERRUPT … #define DACB_AUTODETECT_INTERRUPT … #define DC_I2C_SW_DONE_INTERRUPT … #define DC_I2C_HW_DONE_INTERRUPT … #define DISP_INTERRUPT_STATUS_CONTINUE … #define LB_D2_VLINE_INTERRUPT … #define LB_D2_VBLANK_INTERRUPT … #define DC_HPD2_INTERRUPT … #define DC_HPD2_RX_INTERRUPT … #define DISP_TIMER_INTERRUPT … #define DISP_INTERRUPT_STATUS_CONTINUE2 … #define LB_D3_VLINE_INTERRUPT … #define LB_D3_VBLANK_INTERRUPT … #define DC_HPD3_INTERRUPT … #define DC_HPD3_RX_INTERRUPT … #define DISP_INTERRUPT_STATUS_CONTINUE3 … #define LB_D4_VLINE_INTERRUPT … #define LB_D4_VBLANK_INTERRUPT … #define DC_HPD4_INTERRUPT … #define DC_HPD4_RX_INTERRUPT … #define DISP_INTERRUPT_STATUS_CONTINUE4 … #define LB_D5_VLINE_INTERRUPT … #define LB_D5_VBLANK_INTERRUPT … #define DC_HPD5_INTERRUPT … #define DC_HPD5_RX_INTERRUPT … #define DISP_INTERRUPT_STATUS_CONTINUE5 … #define LB_D6_VLINE_INTERRUPT … #define LB_D6_VBLANK_INTERRUPT … #define DC_HPD6_INTERRUPT … #define DC_HPD6_RX_INTERRUPT … /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ #define GRPH_INT_STATUS … #define GRPH_PFLIP_INT_OCCURRED … #define GRPH_PFLIP_INT_CLEAR … /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ #define GRPH_INT_CONTROL … #define GRPH_PFLIP_INT_MASK … #define GRPH_PFLIP_INT_TYPE … #define DACA_AUTODETECT_INT_CONTROL … #define DACB_AUTODETECT_INT_CONTROL … #define DC_HPD1_INT_STATUS … #define DC_HPD2_INT_STATUS … #define DC_HPD3_INT_STATUS … #define DC_HPD4_INT_STATUS … #define DC_HPD5_INT_STATUS … #define DC_HPD6_INT_STATUS … #define DC_HPDx_INT_STATUS … #define DC_HPDx_SENSE … #define DC_HPDx_RX_INT_STATUS … #define DC_HPD1_INT_CONTROL … #define DC_HPD2_INT_CONTROL … #define DC_HPD3_INT_CONTROL … #define DC_HPD4_INT_CONTROL … #define DC_HPD5_INT_CONTROL … #define DC_HPD6_INT_CONTROL … #define DC_HPDx_INT_ACK … #define DC_HPDx_INT_POLARITY … #define DC_HPDx_INT_EN … #define DC_HPDx_RX_INT_ACK … #define DC_HPDx_RX_INT_EN … #define DC_HPD1_CONTROL … #define DC_HPD2_CONTROL … #define DC_HPD3_CONTROL … #define DC_HPD4_CONTROL … #define DC_HPD5_CONTROL … #define DC_HPD6_CONTROL … #define DC_HPDx_CONNECTION_TIMER(x) … #define DC_HPDx_RX_INT_TIMER(x) … #define DC_HPDx_EN … /* DCE4/5/6 FMT blocks */ #define FMT_DYNAMIC_EXP_CNTL … #define FMT_DYNAMIC_EXP_EN … #define FMT_DYNAMIC_EXP_MODE … /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */ #define FMT_CONTROL … #define FMT_PIXEL_ENCODING … /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */ #define FMT_BIT_DEPTH_CONTROL … #define FMT_TRUNCATE_EN … #define FMT_TRUNCATE_DEPTH … #define FMT_SPATIAL_DITHER_EN … #define FMT_SPATIAL_DITHER_MODE(x) … #define FMT_SPATIAL_DITHER_DEPTH … #define FMT_FRAME_RANDOM_ENABLE … #define FMT_RGB_RANDOM_ENABLE … #define FMT_HIGHPASS_RANDOM_ENABLE … #define FMT_TEMPORAL_DITHER_EN … #define FMT_TEMPORAL_DITHER_DEPTH … #define FMT_TEMPORAL_DITHER_OFFSET(x) … #define FMT_TEMPORAL_LEVEL … #define FMT_TEMPORAL_DITHER_RESET … #define FMT_25FRC_SEL(x) … #define FMT_50FRC_SEL(x) … #define FMT_75FRC_SEL(x) … #define FMT_CLAMP_CONTROL … #define FMT_CLAMP_DATA_EN … #define FMT_CLAMP_COLOR_FORMAT(x) … #define FMT_CLAMP_6BPC … #define FMT_CLAMP_8BPC … #define FMT_CLAMP_10BPC … /* ASYNC DMA */ #define DMA_RB_RPTR … #define DMA_RB_WPTR … #define DMA_CNTL … #define TRAP_ENABLE … #define SEM_INCOMPLETE_INT_ENABLE … #define SEM_WAIT_INT_ENABLE … #define DATA_SWAP_ENABLE … #define FENCE_SWAP_ENABLE … #define CTXEMPTY_INT_ENABLE … #define DMA_TILING_CONFIG … #define CAYMAN_DMA1_CNTL … /* async DMA packets */ #define DMA_PACKET(cmd, sub_cmd, n) … #define GET_DMA_CMD(h) … #define GET_DMA_COUNT(h) … #define GET_DMA_SUB_CMD(h) … /* async DMA Packet types */ #define DMA_PACKET_WRITE … #define DMA_PACKET_COPY … #define DMA_PACKET_INDIRECT_BUFFER … #define DMA_PACKET_SEMAPHORE … #define DMA_PACKET_FENCE … #define DMA_PACKET_TRAP … #define DMA_PACKET_SRBM_WRITE … #define DMA_PACKET_CONSTANT_FILL … #define DMA_PACKET_NOP … /* PIF PHY0 indirect regs */ #define PB0_PIF_CNTL … #define LS2_EXIT_TIME(x) … #define LS2_EXIT_TIME_MASK … #define LS2_EXIT_TIME_SHIFT … #define PB0_PIF_PAIRING … #define MULTI_PIF … #define PB0_PIF_PWRDOWN_0 … #define PLL_POWER_STATE_IN_TXS2_0(x) … #define PLL_POWER_STATE_IN_TXS2_0_MASK … #define PLL_POWER_STATE_IN_TXS2_0_SHIFT … #define PLL_POWER_STATE_IN_OFF_0(x) … #define PLL_POWER_STATE_IN_OFF_0_MASK … #define PLL_POWER_STATE_IN_OFF_0_SHIFT … #define PLL_RAMP_UP_TIME_0(x) … #define PLL_RAMP_UP_TIME_0_MASK … #define PLL_RAMP_UP_TIME_0_SHIFT … #define PB0_PIF_PWRDOWN_1 … #define PLL_POWER_STATE_IN_TXS2_1(x) … #define PLL_POWER_STATE_IN_TXS2_1_MASK … #define PLL_POWER_STATE_IN_TXS2_1_SHIFT … #define PLL_POWER_STATE_IN_OFF_1(x) … #define PLL_POWER_STATE_IN_OFF_1_MASK … #define PLL_POWER_STATE_IN_OFF_1_SHIFT … #define PLL_RAMP_UP_TIME_1(x) … #define PLL_RAMP_UP_TIME_1_MASK … #define PLL_RAMP_UP_TIME_1_SHIFT … /* PIF PHY1 indirect regs */ #define PB1_PIF_CNTL … #define PB1_PIF_PAIRING … #define PB1_PIF_PWRDOWN_0 … #define PB1_PIF_PWRDOWN_1 … /* PCIE PORT indirect regs */ #define PCIE_LC_CNTL … #define LC_L0S_INACTIVITY(x) … #define LC_L0S_INACTIVITY_MASK … #define LC_L0S_INACTIVITY_SHIFT … #define LC_L1_INACTIVITY(x) … #define LC_L1_INACTIVITY_MASK … #define LC_L1_INACTIVITY_SHIFT … #define LC_PMI_TO_L1_DIS … #define LC_ASPM_TO_L1_DIS … #define PCIE_LC_TRAINING_CNTL … #define PCIE_LC_LINK_WIDTH_CNTL … #define LC_LINK_WIDTH_SHIFT … #define LC_LINK_WIDTH_MASK … #define LC_LINK_WIDTH_X0 … #define LC_LINK_WIDTH_X1 … #define LC_LINK_WIDTH_X2 … #define LC_LINK_WIDTH_X4 … #define LC_LINK_WIDTH_X8 … #define LC_LINK_WIDTH_X16 … #define LC_LINK_WIDTH_RD_SHIFT … #define LC_LINK_WIDTH_RD_MASK … #define LC_RECONFIG_ARC_MISSING_ESCAPE … #define LC_RECONFIG_NOW … #define LC_RENEGOTIATION_SUPPORT … #define LC_RENEGOTIATE_EN … #define LC_SHORT_RECONFIG_EN … #define LC_UPCONFIGURE_SUPPORT … #define LC_UPCONFIGURE_DIS … #define LC_DYN_LANES_PWR_STATE(x) … #define LC_DYN_LANES_PWR_STATE_MASK … #define LC_DYN_LANES_PWR_STATE_SHIFT … #define PCIE_LC_SPEED_CNTL … #define LC_GEN2_EN_STRAP … #define LC_TARGET_LINK_SPEED_OVERRIDE_EN … #define LC_FORCE_EN_HW_SPEED_CHANGE … #define LC_FORCE_DIS_HW_SPEED_CHANGE … #define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK … #define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT … #define LC_CURRENT_DATA_RATE … #define LC_HW_VOLTAGE_IF_CONTROL(x) … #define LC_HW_VOLTAGE_IF_CONTROL_MASK … #define LC_HW_VOLTAGE_IF_CONTROL_SHIFT … #define LC_VOLTAGE_TIMER_SEL_MASK … #define LC_CLR_FAILED_SPD_CHANGE_CNT … #define LC_OTHER_SIDE_EVER_SENT_GEN2 … #define LC_OTHER_SIDE_SUPPORTS_GEN2 … #define MM_CFGREGS_CNTL … #define MM_WR_TO_CFG_EN … #define LINK_CNTL2 … #define TARGET_LINK_SPEED_MASK … #define SELECTABLE_DEEMPHASIS … /* * UVD */ #define UVD_UDEC_ADDR_CONFIG … #define UVD_UDEC_DB_ADDR_CONFIG … #define UVD_UDEC_DBW_ADDR_CONFIG … #define UVD_NO_OP … #define UVD_RBC_RB_RPTR … #define UVD_RBC_RB_WPTR … #define UVD_STATUS … /* * PM4 */ #define PACKET0(reg, n) … #define CP_PACKET2 … #define PACKET2_PAD_SHIFT … #define PACKET2_PAD_MASK … #define PACKET2(v) … #define PACKET3(op, n) … /* Packet 3 types */ #define PACKET3_NOP … #define PACKET3_SET_BASE … #define PACKET3_CLEAR_STATE … #define PACKET3_INDEX_BUFFER_SIZE … #define PACKET3_DISPATCH_DIRECT … #define PACKET3_DISPATCH_INDIRECT … #define PACKET3_INDIRECT_BUFFER_END … #define PACKET3_MODE_CONTROL … #define PACKET3_SET_PREDICATION … #define PACKET3_REG_RMW … #define PACKET3_COND_EXEC … #define PACKET3_PRED_EXEC … #define PACKET3_DRAW_INDIRECT … #define PACKET3_DRAW_INDEX_INDIRECT … #define PACKET3_INDEX_BASE … #define PACKET3_DRAW_INDEX_2 … #define PACKET3_CONTEXT_CONTROL … #define PACKET3_DRAW_INDEX_OFFSET … #define PACKET3_INDEX_TYPE … #define PACKET3_DRAW_INDEX … #define PACKET3_DRAW_INDEX_AUTO … #define PACKET3_DRAW_INDEX_IMMD … #define PACKET3_NUM_INSTANCES … #define PACKET3_DRAW_INDEX_MULTI_AUTO … #define PACKET3_STRMOUT_BUFFER_UPDATE … #define PACKET3_DRAW_INDEX_OFFSET_2 … #define PACKET3_DRAW_INDEX_MULTI_ELEMENT … #define PACKET3_MEM_SEMAPHORE … #define PACKET3_MPEG_INDEX … #define PACKET3_COPY_DW … #define PACKET3_WAIT_REG_MEM … #define PACKET3_MEM_WRITE … #define PACKET3_INDIRECT_BUFFER … #define PACKET3_CP_DMA … /* 1. header * 2. SRC_ADDR_LO or DATA [31:0] * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | * SRC_ADDR_HI [7:0] * 4. DST_ADDR_LO [31:0] * 5. DST_ADDR_HI [7:0] * 6. COMMAND [29:22] | BYTE_COUNT [20:0] */ #define PACKET3_CP_DMA_DST_SEL(x) … /* 0 - DST_ADDR * 1 - GDS */ #define PACKET3_CP_DMA_ENGINE(x) … /* 0 - ME * 1 - PFP */ #define PACKET3_CP_DMA_SRC_SEL(x) … /* 0 - SRC_ADDR * 1 - GDS * 2 - DATA */ #define PACKET3_CP_DMA_CP_SYNC … /* COMMAND */ #define PACKET3_CP_DMA_DIS_WC … #define PACKET3_CP_DMA_CMD_SRC_SWAP(x) … /* 0 - none * 1 - 8 in 16 * 2 - 8 in 32 * 3 - 8 in 64 */ #define PACKET3_CP_DMA_CMD_DST_SWAP(x) … /* 0 - none * 1 - 8 in 16 * 2 - 8 in 32 * 3 - 8 in 64 */ #define PACKET3_CP_DMA_CMD_SAS … /* 0 - memory * 1 - register */ #define PACKET3_CP_DMA_CMD_DAS … /* 0 - memory * 1 - register */ #define PACKET3_CP_DMA_CMD_SAIC … #define PACKET3_CP_DMA_CMD_DAIC … #define PACKET3_PFP_SYNC_ME … #define PACKET3_SURFACE_SYNC … #define PACKET3_CB0_DEST_BASE_ENA … #define PACKET3_CB1_DEST_BASE_ENA … #define PACKET3_CB2_DEST_BASE_ENA … #define PACKET3_CB3_DEST_BASE_ENA … #define PACKET3_CB4_DEST_BASE_ENA … #define PACKET3_CB5_DEST_BASE_ENA … #define PACKET3_CB6_DEST_BASE_ENA … #define PACKET3_CB7_DEST_BASE_ENA … #define PACKET3_DB_DEST_BASE_ENA … #define PACKET3_CB8_DEST_BASE_ENA … #define PACKET3_CB9_DEST_BASE_ENA … #define PACKET3_CB10_DEST_BASE_ENA … #define PACKET3_CB11_DEST_BASE_ENA … #define PACKET3_FULL_CACHE_ENA … #define PACKET3_TC_ACTION_ENA … #define PACKET3_VC_ACTION_ENA … #define PACKET3_CB_ACTION_ENA … #define PACKET3_DB_ACTION_ENA … #define PACKET3_SH_ACTION_ENA … #define PACKET3_SX_ACTION_ENA … #define PACKET3_ME_INITIALIZE … #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) … #define PACKET3_COND_WRITE … #define PACKET3_EVENT_WRITE … #define PACKET3_EVENT_WRITE_EOP … #define PACKET3_EVENT_WRITE_EOS … #define PACKET3_PREAMBLE_CNTL … #define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE … #define PACKET3_PREAMBLE_END_CLEAR_STATE … #define PACKET3_RB_OFFSET … #define PACKET3_ALU_PS_CONST_BUFFER_COPY … #define PACKET3_ALU_VS_CONST_BUFFER_COPY … #define PACKET3_ALU_PS_CONST_UPDATE … #define PACKET3_ALU_VS_CONST_UPDATE … #define PACKET3_ONE_REG_WRITE … #define PACKET3_SET_CONFIG_REG … #define PACKET3_SET_CONFIG_REG_START … #define PACKET3_SET_CONFIG_REG_END … #define PACKET3_SET_CONTEXT_REG … #define PACKET3_SET_CONTEXT_REG_START … #define PACKET3_SET_CONTEXT_REG_END … #define PACKET3_SET_ALU_CONST … /* alu const buffers only; no reg file */ #define PACKET3_SET_BOOL_CONST … #define PACKET3_SET_BOOL_CONST_START … #define PACKET3_SET_BOOL_CONST_END … #define PACKET3_SET_LOOP_CONST … #define PACKET3_SET_LOOP_CONST_START … #define PACKET3_SET_LOOP_CONST_END … #define PACKET3_SET_RESOURCE … #define PACKET3_SET_RESOURCE_START … #define PACKET3_SET_RESOURCE_END … #define PACKET3_SET_SAMPLER … #define PACKET3_SET_SAMPLER_START … #define PACKET3_SET_SAMPLER_END … #define PACKET3_SET_CTL_CONST … #define PACKET3_SET_CTL_CONST_START … #define PACKET3_SET_CTL_CONST_END … #define PACKET3_SET_RESOURCE_OFFSET … #define PACKET3_SET_ALU_CONST_VS … #define PACKET3_SET_ALU_CONST_DI … #define PACKET3_SET_CONTEXT_REG_INDIRECT … #define PACKET3_SET_RESOURCE_INDIRECT … #define PACKET3_SET_APPEND_CNT … /* SET_APPEND_CNT - documentation * 1. header * 2. COMMAND * 1:0 - SOURCE SEL * 15:2 - Reserved * 31:16 - WR_REG_OFFSET - context register to write source data to. * (one of R_02872C_GDS_APPEND_COUNT_0-11) * 3. CONTROL * (for source == mem) * 31:2 SRC_ADDRESS_LO * 0:1 SWAP * (for source == GDS) * 31:0 GDS offset * (for source == DATA) * 31:0 DATA * (for source == REG) * 31:0 REG * 4. SRC_ADDRESS_HI[7:0] * kernel driver 2.44 only supports SRC == MEM. */ #define PACKET3_SET_APPEND_CNT_SRC_SELECT(x) … #define G_PACKET3_SET_APPEND_CNT_SRC_SELECT(x) … /* source is from the data in CONTROL */ #define PACKET3_SAC_SRC_SEL_DATA … /* source is from register */ #define PACKET3_SAC_SRC_SEL_REG … /* source is from GDS offset in CONTROL */ #define PACKET3_SAC_SRC_SEL_GDS … /* source is from memory address */ #define PACKET3_SAC_SRC_SEL_MEM … #define SQ_RESOURCE_CONSTANT_WORD7_0 … #define S__SQ_CONSTANT_TYPE(x) … #define G__SQ_CONSTANT_TYPE(x) … #define SQ_TEX_VTX_INVALID_TEXTURE … #define SQ_TEX_VTX_INVALID_BUFFER … #define SQ_TEX_VTX_VALID_TEXTURE … #define SQ_TEX_VTX_VALID_BUFFER … #define VGT_VTX_VECT_EJECT_REG … #define SQ_CONST_MEM_BASE … #define SQ_ESGS_RING_BASE … #define SQ_ESGS_RING_SIZE … #define SQ_GSVS_RING_BASE … #define SQ_GSVS_RING_SIZE … #define SQ_ESTMP_RING_BASE … #define SQ_ESTMP_RING_SIZE … #define SQ_GSTMP_RING_BASE … #define SQ_GSTMP_RING_SIZE … #define SQ_VSTMP_RING_BASE … #define SQ_VSTMP_RING_SIZE … #define SQ_PSTMP_RING_BASE … #define SQ_PSTMP_RING_SIZE … #define SQ_LSTMP_RING_BASE … #define SQ_LSTMP_RING_SIZE … #define SQ_HSTMP_RING_BASE … #define SQ_HSTMP_RING_SIZE … #define VGT_TF_RING_SIZE … #define SQ_ESGS_RING_ITEMSIZE … #define SQ_GSVS_RING_ITEMSIZE … #define SQ_ESTMP_RING_ITEMSIZE … #define SQ_GSTMP_RING_ITEMSIZE … #define SQ_VSTMP_RING_ITEMSIZE … #define SQ_PSTMP_RING_ITEMSIZE … #define SQ_LSTMP_RING_ITEMSIZE … #define SQ_HSTMP_RING_ITEMSIZE … #define SQ_GS_VERT_ITEMSIZE … #define SQ_GS_VERT_ITEMSIZE_1 … #define SQ_GS_VERT_ITEMSIZE_2 … #define SQ_GS_VERT_ITEMSIZE_3 … #define SQ_GSVS_RING_OFFSET_1 … #define SQ_GSVS_RING_OFFSET_2 … #define SQ_GSVS_RING_OFFSET_3 … #define SQ_ALU_CONST_BUFFER_SIZE_PS_0 … #define SQ_ALU_CONST_BUFFER_SIZE_HS_0 … #define SQ_ALU_CONST_CACHE_PS_0 … #define SQ_ALU_CONST_CACHE_PS_1 … #define SQ_ALU_CONST_CACHE_PS_2 … #define SQ_ALU_CONST_CACHE_PS_3 … #define SQ_ALU_CONST_CACHE_PS_4 … #define SQ_ALU_CONST_CACHE_PS_5 … #define SQ_ALU_CONST_CACHE_PS_6 … #define SQ_ALU_CONST_CACHE_PS_7 … #define SQ_ALU_CONST_CACHE_PS_8 … #define SQ_ALU_CONST_CACHE_PS_9 … #define SQ_ALU_CONST_CACHE_PS_10 … #define SQ_ALU_CONST_CACHE_PS_11 … #define SQ_ALU_CONST_CACHE_PS_12 … #define SQ_ALU_CONST_CACHE_PS_13 … #define SQ_ALU_CONST_CACHE_PS_14 … #define SQ_ALU_CONST_CACHE_PS_15 … #define SQ_ALU_CONST_CACHE_VS_0 … #define SQ_ALU_CONST_CACHE_VS_1 … #define SQ_ALU_CONST_CACHE_VS_2 … #define SQ_ALU_CONST_CACHE_VS_3 … #define SQ_ALU_CONST_CACHE_VS_4 … #define SQ_ALU_CONST_CACHE_VS_5 … #define SQ_ALU_CONST_CACHE_VS_6 … #define SQ_ALU_CONST_CACHE_VS_7 … #define SQ_ALU_CONST_CACHE_VS_8 … #define SQ_ALU_CONST_CACHE_VS_9 … #define SQ_ALU_CONST_CACHE_VS_10 … #define SQ_ALU_CONST_CACHE_VS_11 … #define SQ_ALU_CONST_CACHE_VS_12 … #define SQ_ALU_CONST_CACHE_VS_13 … #define SQ_ALU_CONST_CACHE_VS_14 … #define SQ_ALU_CONST_CACHE_VS_15 … #define SQ_ALU_CONST_CACHE_GS_0 … #define SQ_ALU_CONST_CACHE_GS_1 … #define SQ_ALU_CONST_CACHE_GS_2 … #define SQ_ALU_CONST_CACHE_GS_3 … #define SQ_ALU_CONST_CACHE_GS_4 … #define SQ_ALU_CONST_CACHE_GS_5 … #define SQ_ALU_CONST_CACHE_GS_6 … #define SQ_ALU_CONST_CACHE_GS_7 … #define SQ_ALU_CONST_CACHE_GS_8 … #define SQ_ALU_CONST_CACHE_GS_9 … #define SQ_ALU_CONST_CACHE_GS_10 … #define SQ_ALU_CONST_CACHE_GS_11 … #define SQ_ALU_CONST_CACHE_GS_12 … #define SQ_ALU_CONST_CACHE_GS_13 … #define SQ_ALU_CONST_CACHE_GS_14 … #define SQ_ALU_CONST_CACHE_GS_15 … #define SQ_ALU_CONST_CACHE_HS_0 … #define SQ_ALU_CONST_CACHE_HS_1 … #define SQ_ALU_CONST_CACHE_HS_2 … #define SQ_ALU_CONST_CACHE_HS_3 … #define SQ_ALU_CONST_CACHE_HS_4 … #define SQ_ALU_CONST_CACHE_HS_5 … #define SQ_ALU_CONST_CACHE_HS_6 … #define SQ_ALU_CONST_CACHE_HS_7 … #define SQ_ALU_CONST_CACHE_HS_8 … #define SQ_ALU_CONST_CACHE_HS_9 … #define SQ_ALU_CONST_CACHE_HS_10 … #define SQ_ALU_CONST_CACHE_HS_11 … #define SQ_ALU_CONST_CACHE_HS_12 … #define SQ_ALU_CONST_CACHE_HS_13 … #define SQ_ALU_CONST_CACHE_HS_14 … #define SQ_ALU_CONST_CACHE_HS_15 … #define SQ_ALU_CONST_CACHE_LS_0 … #define SQ_ALU_CONST_CACHE_LS_1 … #define SQ_ALU_CONST_CACHE_LS_2 … #define SQ_ALU_CONST_CACHE_LS_3 … #define SQ_ALU_CONST_CACHE_LS_4 … #define SQ_ALU_CONST_CACHE_LS_5 … #define SQ_ALU_CONST_CACHE_LS_6 … #define SQ_ALU_CONST_CACHE_LS_7 … #define SQ_ALU_CONST_CACHE_LS_8 … #define SQ_ALU_CONST_CACHE_LS_9 … #define SQ_ALU_CONST_CACHE_LS_10 … #define SQ_ALU_CONST_CACHE_LS_11 … #define SQ_ALU_CONST_CACHE_LS_12 … #define SQ_ALU_CONST_CACHE_LS_13 … #define SQ_ALU_CONST_CACHE_LS_14 … #define SQ_ALU_CONST_CACHE_LS_15 … #define PA_SC_SCREEN_SCISSOR_TL … #define PA_SC_GENERIC_SCISSOR_TL … #define PA_SC_WINDOW_SCISSOR_TL … #define VGT_PRIMITIVE_TYPE … #define VGT_INDEX_TYPE … #define VGT_NUM_INDICES … #define VGT_COMPUTE_DIM_X … #define VGT_COMPUTE_DIM_Y … #define VGT_COMPUTE_DIM_Z … #define VGT_COMPUTE_START_X … #define VGT_COMPUTE_START_Y … #define VGT_COMPUTE_START_Z … #define VGT_COMPUTE_INDEX … #define VGT_COMPUTE_THREAD_GROUP_SIZE … #define VGT_HS_OFFCHIP_PARAM … #define DB_DEBUG … #define DB_DEBUG2 … #define DB_DEBUG3 … #define DB_DEBUG4 … #define DB_WATERMARKS … #define DB_DEPTH_CONTROL … #define R_028800_DB_DEPTH_CONTROL … #define S_028800_STENCIL_ENABLE(x) … #define G_028800_STENCIL_ENABLE(x) … #define C_028800_STENCIL_ENABLE … #define S_028800_Z_ENABLE(x) … #define G_028800_Z_ENABLE(x) … #define C_028800_Z_ENABLE … #define S_028800_Z_WRITE_ENABLE(x) … #define G_028800_Z_WRITE_ENABLE(x) … #define C_028800_Z_WRITE_ENABLE … #define S_028800_ZFUNC(x) … #define G_028800_ZFUNC(x) … #define C_028800_ZFUNC … #define S_028800_BACKFACE_ENABLE(x) … #define G_028800_BACKFACE_ENABLE(x) … #define C_028800_BACKFACE_ENABLE … #define S_028800_STENCILFUNC(x) … #define G_028800_STENCILFUNC(x) … #define C_028800_STENCILFUNC … #define V_028800_STENCILFUNC_NEVER … #define V_028800_STENCILFUNC_LESS … #define V_028800_STENCILFUNC_EQUAL … #define V_028800_STENCILFUNC_LEQUAL … #define V_028800_STENCILFUNC_GREATER … #define V_028800_STENCILFUNC_NOTEQUAL … #define V_028800_STENCILFUNC_GEQUAL … #define V_028800_STENCILFUNC_ALWAYS … #define S_028800_STENCILFAIL(x) … #define G_028800_STENCILFAIL(x) … #define C_028800_STENCILFAIL … #define V_028800_STENCIL_KEEP … #define V_028800_STENCIL_ZERO … #define V_028800_STENCIL_REPLACE … #define V_028800_STENCIL_INCR … #define V_028800_STENCIL_DECR … #define V_028800_STENCIL_INVERT … #define V_028800_STENCIL_INCR_WRAP … #define V_028800_STENCIL_DECR_WRAP … #define S_028800_STENCILZPASS(x) … #define G_028800_STENCILZPASS(x) … #define C_028800_STENCILZPASS … #define S_028800_STENCILZFAIL(x) … #define G_028800_STENCILZFAIL(x) … #define C_028800_STENCILZFAIL … #define S_028800_STENCILFUNC_BF(x) … #define G_028800_STENCILFUNC_BF(x) … #define C_028800_STENCILFUNC_BF … #define S_028800_STENCILFAIL_BF(x) … #define G_028800_STENCILFAIL_BF(x) … #define C_028800_STENCILFAIL_BF … #define S_028800_STENCILZPASS_BF(x) … #define G_028800_STENCILZPASS_BF(x) … #define C_028800_STENCILZPASS_BF … #define S_028800_STENCILZFAIL_BF(x) … #define G_028800_STENCILZFAIL_BF(x) … #define C_028800_STENCILZFAIL_BF … #define DB_DEPTH_VIEW … #define R_028008_DB_DEPTH_VIEW … #define S_028008_SLICE_START(x) … #define G_028008_SLICE_START(x) … #define C_028008_SLICE_START … #define S_028008_SLICE_MAX(x) … #define G_028008_SLICE_MAX(x) … #define C_028008_SLICE_MAX … #define DB_HTILE_DATA_BASE … #define DB_HTILE_SURFACE … #define S_028ABC_HTILE_WIDTH(x) … #define G_028ABC_HTILE_WIDTH(x) … #define C_028ABC_HTILE_WIDTH … #define S_028ABC_HTILE_HEIGHT(x) … #define G_028ABC_HTILE_HEIGHT(x) … #define C_028ABC_HTILE_HEIGHT … #define G_028ABC_LINEAR(x) … #define DB_Z_INFO … #define Z_ARRAY_MODE(x) … #define DB_TILE_SPLIT(x) … #define DB_NUM_BANKS(x) … #define DB_BANK_WIDTH(x) … #define DB_BANK_HEIGHT(x) … #define DB_MACRO_TILE_ASPECT(x) … #define R_028040_DB_Z_INFO … #define S_028040_FORMAT(x) … #define G_028040_FORMAT(x) … #define C_028040_FORMAT … #define V_028040_Z_INVALID … #define V_028040_Z_16 … #define V_028040_Z_24 … #define V_028040_Z_32_FLOAT … #define S_028040_ARRAY_MODE(x) … #define G_028040_ARRAY_MODE(x) … #define C_028040_ARRAY_MODE … #define S_028040_READ_SIZE(x) … #define G_028040_READ_SIZE(x) … #define C_028040_READ_SIZE … #define S_028040_TILE_SURFACE_ENABLE(x) … #define G_028040_TILE_SURFACE_ENABLE(x) … #define C_028040_TILE_SURFACE_ENABLE … #define S_028040_ZRANGE_PRECISION(x) … #define G_028040_ZRANGE_PRECISION(x) … #define C_028040_ZRANGE_PRECISION … #define S_028040_TILE_SPLIT(x) … #define G_028040_TILE_SPLIT(x) … #define S_028040_NUM_BANKS(x) … #define G_028040_NUM_BANKS(x) … #define S_028040_BANK_WIDTH(x) … #define G_028040_BANK_WIDTH(x) … #define S_028040_BANK_HEIGHT(x) … #define G_028040_BANK_HEIGHT(x) … #define S_028040_MACRO_TILE_ASPECT(x) … #define G_028040_MACRO_TILE_ASPECT(x) … #define DB_STENCIL_INFO … #define R_028044_DB_STENCIL_INFO … #define S_028044_FORMAT(x) … #define G_028044_FORMAT(x) … #define C_028044_FORMAT … #define V_028044_STENCIL_INVALID … #define V_028044_STENCIL_8 … #define G_028044_TILE_SPLIT(x) … #define DB_Z_READ_BASE … #define DB_STENCIL_READ_BASE … #define DB_Z_WRITE_BASE … #define DB_STENCIL_WRITE_BASE … #define DB_DEPTH_SIZE … #define R_028058_DB_DEPTH_SIZE … #define S_028058_PITCH_TILE_MAX(x) … #define G_028058_PITCH_TILE_MAX(x) … #define C_028058_PITCH_TILE_MAX … #define S_028058_HEIGHT_TILE_MAX(x) … #define G_028058_HEIGHT_TILE_MAX(x) … #define C_028058_HEIGHT_TILE_MAX … #define R_02805C_DB_DEPTH_SLICE … #define S_02805C_SLICE_TILE_MAX(x) … #define G_02805C_SLICE_TILE_MAX(x) … #define C_02805C_SLICE_TILE_MAX … #define SQ_PGM_START_PS … #define SQ_PGM_START_VS … #define SQ_PGM_START_GS … #define SQ_PGM_START_ES … #define SQ_PGM_START_FS … #define SQ_PGM_START_HS … #define SQ_PGM_START_LS … #define VGT_STRMOUT_BUFFER_BASE_0 … #define VGT_STRMOUT_BUFFER_BASE_1 … #define VGT_STRMOUT_BUFFER_BASE_2 … #define VGT_STRMOUT_BUFFER_BASE_3 … #define VGT_STRMOUT_BUFFER_SIZE_0 … #define VGT_STRMOUT_BUFFER_SIZE_1 … #define VGT_STRMOUT_BUFFER_SIZE_2 … #define VGT_STRMOUT_BUFFER_SIZE_3 … #define VGT_STRMOUT_CONFIG … #define VGT_STRMOUT_BUFFER_CONFIG … #define CB_TARGET_MASK … #define CB_SHADER_MASK … #define GDS_ADDR_BASE … #define GDS_APPEND_COUNT_0 … #define GDS_APPEND_COUNT_1 … #define GDS_APPEND_COUNT_2 … #define GDS_APPEND_COUNT_3 … #define GDS_APPEND_COUNT_4 … #define GDS_APPEND_COUNT_5 … #define GDS_APPEND_COUNT_6 … #define GDS_APPEND_COUNT_7 … #define GDS_APPEND_COUNT_8 … #define GDS_APPEND_COUNT_9 … #define GDS_APPEND_COUNT_10 … #define GDS_APPEND_COUNT_11 … #define CB_IMMED0_BASE … #define CB_IMMED1_BASE … #define CB_IMMED2_BASE … #define CB_IMMED3_BASE … #define CB_IMMED4_BASE … #define CB_IMMED5_BASE … #define CB_IMMED6_BASE … #define CB_IMMED7_BASE … #define CB_IMMED8_BASE … #define CB_IMMED9_BASE … #define CB_IMMED10_BASE … #define CB_IMMED11_BASE … /* all 12 CB blocks have these regs */ #define CB_COLOR0_BASE … #define CB_COLOR0_PITCH … #define CB_COLOR0_SLICE … #define CB_COLOR0_VIEW … #define R_028C6C_CB_COLOR0_VIEW … #define S_028C6C_SLICE_START(x) … #define G_028C6C_SLICE_START(x) … #define C_028C6C_SLICE_START … #define S_028C6C_SLICE_MAX(x) … #define G_028C6C_SLICE_MAX(x) … #define C_028C6C_SLICE_MAX … #define R_028C70_CB_COLOR0_INFO … #define S_028C70_ENDIAN(x) … #define G_028C70_ENDIAN(x) … #define C_028C70_ENDIAN … #define S_028C70_FORMAT(x) … #define G_028C70_FORMAT(x) … #define C_028C70_FORMAT … #define V_028C70_COLOR_INVALID … #define V_028C70_COLOR_8 … #define V_028C70_COLOR_4_4 … #define V_028C70_COLOR_3_3_2 … #define V_028C70_COLOR_16 … #define V_028C70_COLOR_16_FLOAT … #define V_028C70_COLOR_8_8 … #define V_028C70_COLOR_5_6_5 … #define V_028C70_COLOR_6_5_5 … #define V_028C70_COLOR_1_5_5_5 … #define V_028C70_COLOR_4_4_4_4 … #define V_028C70_COLOR_5_5_5_1 … #define V_028C70_COLOR_32 … #define V_028C70_COLOR_32_FLOAT … #define V_028C70_COLOR_16_16 … #define V_028C70_COLOR_16_16_FLOAT … #define V_028C70_COLOR_8_24 … #define V_028C70_COLOR_8_24_FLOAT … #define V_028C70_COLOR_24_8 … #define V_028C70_COLOR_24_8_FLOAT … #define V_028C70_COLOR_10_11_11 … #define V_028C70_COLOR_10_11_11_FLOAT … #define V_028C70_COLOR_11_11_10 … #define V_028C70_COLOR_11_11_10_FLOAT … #define V_028C70_COLOR_2_10_10_10 … #define V_028C70_COLOR_8_8_8_8 … #define V_028C70_COLOR_10_10_10_2 … #define V_028C70_COLOR_X24_8_32_FLOAT … #define V_028C70_COLOR_32_32 … #define V_028C70_COLOR_32_32_FLOAT … #define V_028C70_COLOR_16_16_16_16 … #define V_028C70_COLOR_16_16_16_16_FLOAT … #define V_028C70_COLOR_32_32_32_32 … #define V_028C70_COLOR_32_32_32_32_FLOAT … #define V_028C70_COLOR_32_32_32_FLOAT … #define S_028C70_ARRAY_MODE(x) … #define G_028C70_ARRAY_MODE(x) … #define C_028C70_ARRAY_MODE … #define V_028C70_ARRAY_LINEAR_GENERAL … #define V_028C70_ARRAY_LINEAR_ALIGNED … #define V_028C70_ARRAY_1D_TILED_THIN1 … #define V_028C70_ARRAY_2D_TILED_THIN1 … #define S_028C70_NUMBER_TYPE(x) … #define G_028C70_NUMBER_TYPE(x) … #define C_028C70_NUMBER_TYPE … #define V_028C70_NUMBER_UNORM … #define V_028C70_NUMBER_SNORM … #define V_028C70_NUMBER_USCALED … #define V_028C70_NUMBER_SSCALED … #define V_028C70_NUMBER_UINT … #define V_028C70_NUMBER_SINT … #define V_028C70_NUMBER_SRGB … #define V_028C70_NUMBER_FLOAT … #define S_028C70_COMP_SWAP(x) … #define G_028C70_COMP_SWAP(x) … #define C_028C70_COMP_SWAP … #define V_028C70_SWAP_STD … #define V_028C70_SWAP_ALT … #define V_028C70_SWAP_STD_REV … #define V_028C70_SWAP_ALT_REV … #define S_028C70_FAST_CLEAR(x) … #define G_028C70_FAST_CLEAR(x) … #define C_028C70_FAST_CLEAR … #define S_028C70_COMPRESSION(x) … #define G_028C70_COMPRESSION(x) … #define C_028C70_COMPRESSION … #define S_028C70_BLEND_CLAMP(x) … #define G_028C70_BLEND_CLAMP(x) … #define C_028C70_BLEND_CLAMP … #define S_028C70_BLEND_BYPASS(x) … #define G_028C70_BLEND_BYPASS(x) … #define C_028C70_BLEND_BYPASS … #define S_028C70_SIMPLE_FLOAT(x) … #define G_028C70_SIMPLE_FLOAT(x) … #define C_028C70_SIMPLE_FLOAT … #define S_028C70_ROUND_MODE(x) … #define G_028C70_ROUND_MODE(x) … #define C_028C70_ROUND_MODE … #define S_028C70_TILE_COMPACT(x) … #define G_028C70_TILE_COMPACT(x) … #define C_028C70_TILE_COMPACT … #define S_028C70_SOURCE_FORMAT(x) … #define G_028C70_SOURCE_FORMAT(x) … #define C_028C70_SOURCE_FORMAT … #define V_028C70_EXPORT_4C_32BPC … #define V_028C70_EXPORT_4C_16BPC … #define V_028C70_EXPORT_2C_32BPC … #define S_028C70_RAT(x) … #define G_028C70_RAT(x) … #define C_028C70_RAT … #define S_028C70_RESOURCE_TYPE(x) … #define G_028C70_RESOURCE_TYPE(x) … #define C_028C70_RESOURCE_TYPE … #define CB_COLOR0_INFO … #define CB_FORMAT(x) … #define CB_ARRAY_MODE(x) … #define ARRAY_LINEAR_GENERAL … #define ARRAY_LINEAR_ALIGNED … #define ARRAY_1D_TILED_THIN1 … #define ARRAY_2D_TILED_THIN1 … #define CB_SOURCE_FORMAT(x) … #define CB_SF_EXPORT_FULL … #define CB_SF_EXPORT_NORM … #define R_028C74_CB_COLOR0_ATTRIB … #define S_028C74_NON_DISP_TILING_ORDER(x) … #define G_028C74_NON_DISP_TILING_ORDER(x) … #define C_028C74_NON_DISP_TILING_ORDER … #define S_028C74_TILE_SPLIT(x) … #define G_028C74_TILE_SPLIT(x) … #define S_028C74_NUM_BANKS(x) … #define G_028C74_NUM_BANKS(x) … #define S_028C74_BANK_WIDTH(x) … #define G_028C74_BANK_WIDTH(x) … #define S_028C74_BANK_HEIGHT(x) … #define G_028C74_BANK_HEIGHT(x) … #define S_028C74_MACRO_TILE_ASPECT(x) … #define G_028C74_MACRO_TILE_ASPECT(x) … #define CB_COLOR0_ATTRIB … #define CB_TILE_SPLIT(x) … #define ADDR_SURF_TILE_SPLIT_64B … #define ADDR_SURF_TILE_SPLIT_128B … #define ADDR_SURF_TILE_SPLIT_256B … #define ADDR_SURF_TILE_SPLIT_512B … #define ADDR_SURF_TILE_SPLIT_1KB … #define ADDR_SURF_TILE_SPLIT_2KB … #define ADDR_SURF_TILE_SPLIT_4KB … #define CB_NUM_BANKS(x) … #define ADDR_SURF_2_BANK … #define ADDR_SURF_4_BANK … #define ADDR_SURF_8_BANK … #define ADDR_SURF_16_BANK … #define CB_BANK_WIDTH(x) … #define ADDR_SURF_BANK_WIDTH_1 … #define ADDR_SURF_BANK_WIDTH_2 … #define ADDR_SURF_BANK_WIDTH_4 … #define ADDR_SURF_BANK_WIDTH_8 … #define CB_BANK_HEIGHT(x) … #define ADDR_SURF_BANK_HEIGHT_1 … #define ADDR_SURF_BANK_HEIGHT_2 … #define ADDR_SURF_BANK_HEIGHT_4 … #define ADDR_SURF_BANK_HEIGHT_8 … #define CB_MACRO_TILE_ASPECT(x) … #define CB_COLOR0_DIM … /* only CB0-7 blocks have these regs */ #define CB_COLOR0_CMASK … #define CB_COLOR0_CMASK_SLICE … #define CB_COLOR0_FMASK … #define CB_COLOR0_FMASK_SLICE … #define CB_COLOR0_CLEAR_WORD0 … #define CB_COLOR0_CLEAR_WORD1 … #define CB_COLOR0_CLEAR_WORD2 … #define CB_COLOR0_CLEAR_WORD3 … #define CB_COLOR1_BASE … #define CB_COLOR2_BASE … #define CB_COLOR3_BASE … #define CB_COLOR4_BASE … #define CB_COLOR5_BASE … #define CB_COLOR6_BASE … #define CB_COLOR7_BASE … #define CB_COLOR8_BASE … #define CB_COLOR9_BASE … #define CB_COLOR10_BASE … #define CB_COLOR11_BASE … #define CB_COLOR1_PITCH … #define CB_COLOR2_PITCH … #define CB_COLOR3_PITCH … #define CB_COLOR4_PITCH … #define CB_COLOR5_PITCH … #define CB_COLOR6_PITCH … #define CB_COLOR7_PITCH … #define CB_COLOR8_PITCH … #define CB_COLOR9_PITCH … #define CB_COLOR10_PITCH … #define CB_COLOR11_PITCH … #define CB_COLOR1_SLICE … #define CB_COLOR2_SLICE … #define CB_COLOR3_SLICE … #define CB_COLOR4_SLICE … #define CB_COLOR5_SLICE … #define CB_COLOR6_SLICE … #define CB_COLOR7_SLICE … #define CB_COLOR8_SLICE … #define CB_COLOR9_SLICE … #define CB_COLOR10_SLICE … #define CB_COLOR11_SLICE … #define CB_COLOR1_VIEW … #define CB_COLOR2_VIEW … #define CB_COLOR3_VIEW … #define CB_COLOR4_VIEW … #define CB_COLOR5_VIEW … #define CB_COLOR6_VIEW … #define CB_COLOR7_VIEW … #define CB_COLOR8_VIEW … #define CB_COLOR9_VIEW … #define CB_COLOR10_VIEW … #define CB_COLOR11_VIEW … #define CB_COLOR1_INFO … #define CB_COLOR2_INFO … #define CB_COLOR3_INFO … #define CB_COLOR4_INFO … #define CB_COLOR5_INFO … #define CB_COLOR6_INFO … #define CB_COLOR7_INFO … #define CB_COLOR8_INFO … #define CB_COLOR9_INFO … #define CB_COLOR10_INFO … #define CB_COLOR11_INFO … #define CB_COLOR1_ATTRIB … #define CB_COLOR2_ATTRIB … #define CB_COLOR3_ATTRIB … #define CB_COLOR4_ATTRIB … #define CB_COLOR5_ATTRIB … #define CB_COLOR6_ATTRIB … #define CB_COLOR7_ATTRIB … #define CB_COLOR8_ATTRIB … #define CB_COLOR9_ATTRIB … #define CB_COLOR10_ATTRIB … #define CB_COLOR11_ATTRIB … #define CB_COLOR1_DIM … #define CB_COLOR2_DIM … #define CB_COLOR3_DIM … #define CB_COLOR4_DIM … #define CB_COLOR5_DIM … #define CB_COLOR6_DIM … #define CB_COLOR7_DIM … #define CB_COLOR8_DIM … #define CB_COLOR9_DIM … #define CB_COLOR10_DIM … #define CB_COLOR11_DIM … #define CB_COLOR1_CMASK … #define CB_COLOR2_CMASK … #define CB_COLOR3_CMASK … #define CB_COLOR4_CMASK … #define CB_COLOR5_CMASK … #define CB_COLOR6_CMASK … #define CB_COLOR7_CMASK … #define CB_COLOR1_CMASK_SLICE … #define CB_COLOR2_CMASK_SLICE … #define CB_COLOR3_CMASK_SLICE … #define CB_COLOR4_CMASK_SLICE … #define CB_COLOR5_CMASK_SLICE … #define CB_COLOR6_CMASK_SLICE … #define CB_COLOR7_CMASK_SLICE … #define CB_COLOR1_FMASK … #define CB_COLOR2_FMASK … #define CB_COLOR3_FMASK … #define CB_COLOR4_FMASK … #define CB_COLOR5_FMASK … #define CB_COLOR6_FMASK … #define CB_COLOR7_FMASK … #define CB_COLOR1_FMASK_SLICE … #define CB_COLOR2_FMASK_SLICE … #define CB_COLOR3_FMASK_SLICE … #define CB_COLOR4_FMASK_SLICE … #define CB_COLOR5_FMASK_SLICE … #define CB_COLOR6_FMASK_SLICE … #define CB_COLOR7_FMASK_SLICE … #define CB_COLOR1_CLEAR_WORD0 … #define CB_COLOR2_CLEAR_WORD0 … #define CB_COLOR3_CLEAR_WORD0 … #define CB_COLOR4_CLEAR_WORD0 … #define CB_COLOR5_CLEAR_WORD0 … #define CB_COLOR6_CLEAR_WORD0 … #define CB_COLOR7_CLEAR_WORD0 … #define CB_COLOR1_CLEAR_WORD1 … #define CB_COLOR2_CLEAR_WORD1 … #define CB_COLOR3_CLEAR_WORD1 … #define CB_COLOR4_CLEAR_WORD1 … #define CB_COLOR5_CLEAR_WORD1 … #define CB_COLOR6_CLEAR_WORD1 … #define CB_COLOR7_CLEAR_WORD1 … #define CB_COLOR1_CLEAR_WORD2 … #define CB_COLOR2_CLEAR_WORD2 … #define CB_COLOR3_CLEAR_WORD2 … #define CB_COLOR4_CLEAR_WORD2 … #define CB_COLOR5_CLEAR_WORD2 … #define CB_COLOR6_CLEAR_WORD2 … #define CB_COLOR7_CLEAR_WORD2 … #define CB_COLOR1_CLEAR_WORD3 … #define CB_COLOR2_CLEAR_WORD3 … #define CB_COLOR3_CLEAR_WORD3 … #define CB_COLOR4_CLEAR_WORD3 … #define CB_COLOR5_CLEAR_WORD3 … #define CB_COLOR6_CLEAR_WORD3 … #define CB_COLOR7_CLEAR_WORD3 … #define SQ_TEX_RESOURCE_WORD0_0 … #define TEX_DIM(x) … #define SQ_TEX_DIM_1D … #define SQ_TEX_DIM_2D … #define SQ_TEX_DIM_3D … #define SQ_TEX_DIM_CUBEMAP … #define SQ_TEX_DIM_1D_ARRAY … #define SQ_TEX_DIM_2D_ARRAY … #define SQ_TEX_DIM_2D_MSAA … #define SQ_TEX_DIM_2D_ARRAY_MSAA … #define SQ_TEX_RESOURCE_WORD1_0 … #define TEX_ARRAY_MODE(x) … #define SQ_TEX_RESOURCE_WORD2_0 … #define SQ_TEX_RESOURCE_WORD3_0 … #define SQ_TEX_RESOURCE_WORD4_0 … #define TEX_DST_SEL_X(x) … #define TEX_DST_SEL_Y(x) … #define TEX_DST_SEL_Z(x) … #define TEX_DST_SEL_W(x) … #define SQ_SEL_X … #define SQ_SEL_Y … #define SQ_SEL_Z … #define SQ_SEL_W … #define SQ_SEL_0 … #define SQ_SEL_1 … #define SQ_TEX_RESOURCE_WORD5_0 … #define SQ_TEX_RESOURCE_WORD6_0 … #define TEX_TILE_SPLIT(x) … #define SQ_TEX_RESOURCE_WORD7_0 … #define MACRO_TILE_ASPECT(x) … #define TEX_BANK_WIDTH(x) … #define TEX_BANK_HEIGHT(x) … #define TEX_NUM_BANKS(x) … #define R_030000_SQ_TEX_RESOURCE_WORD0_0 … #define S_030000_DIM(x) … #define G_030000_DIM(x) … #define C_030000_DIM … #define V_030000_SQ_TEX_DIM_1D … #define V_030000_SQ_TEX_DIM_2D … #define V_030000_SQ_TEX_DIM_3D … #define V_030000_SQ_TEX_DIM_CUBEMAP … #define V_030000_SQ_TEX_DIM_1D_ARRAY … #define V_030000_SQ_TEX_DIM_2D_ARRAY … #define V_030000_SQ_TEX_DIM_2D_MSAA … #define V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA … #define S_030000_NON_DISP_TILING_ORDER(x) … #define G_030000_NON_DISP_TILING_ORDER(x) … #define C_030000_NON_DISP_TILING_ORDER … #define S_030000_PITCH(x) … #define G_030000_PITCH(x) … #define C_030000_PITCH … #define S_030000_TEX_WIDTH(x) … #define G_030000_TEX_WIDTH(x) … #define C_030000_TEX_WIDTH … #define R_030004_SQ_TEX_RESOURCE_WORD1_0 … #define S_030004_TEX_HEIGHT(x) … #define G_030004_TEX_HEIGHT(x) … #define C_030004_TEX_HEIGHT … #define S_030004_TEX_DEPTH(x) … #define G_030004_TEX_DEPTH(x) … #define C_030004_TEX_DEPTH … #define S_030004_ARRAY_MODE(x) … #define G_030004_ARRAY_MODE(x) … #define C_030004_ARRAY_MODE … #define R_030008_SQ_TEX_RESOURCE_WORD2_0 … #define S_030008_BASE_ADDRESS(x) … #define G_030008_BASE_ADDRESS(x) … #define C_030008_BASE_ADDRESS … #define R_03000C_SQ_TEX_RESOURCE_WORD3_0 … #define S_03000C_MIP_ADDRESS(x) … #define G_03000C_MIP_ADDRESS(x) … #define C_03000C_MIP_ADDRESS … #define R_030010_SQ_TEX_RESOURCE_WORD4_0 … #define S_030010_FORMAT_COMP_X(x) … #define G_030010_FORMAT_COMP_X(x) … #define C_030010_FORMAT_COMP_X … #define V_030010_SQ_FORMAT_COMP_UNSIGNED … #define V_030010_SQ_FORMAT_COMP_SIGNED … #define V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED … #define S_030010_FORMAT_COMP_Y(x) … #define G_030010_FORMAT_COMP_Y(x) … #define C_030010_FORMAT_COMP_Y … #define S_030010_FORMAT_COMP_Z(x) … #define G_030010_FORMAT_COMP_Z(x) … #define C_030010_FORMAT_COMP_Z … #define S_030010_FORMAT_COMP_W(x) … #define G_030010_FORMAT_COMP_W(x) … #define C_030010_FORMAT_COMP_W … #define S_030010_NUM_FORMAT_ALL(x) … #define G_030010_NUM_FORMAT_ALL(x) … #define C_030010_NUM_FORMAT_ALL … #define V_030010_SQ_NUM_FORMAT_NORM … #define V_030010_SQ_NUM_FORMAT_INT … #define V_030010_SQ_NUM_FORMAT_SCALED … #define S_030010_SRF_MODE_ALL(x) … #define G_030010_SRF_MODE_ALL(x) … #define C_030010_SRF_MODE_ALL … #define V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE … #define V_030010_SRF_MODE_NO_ZERO … #define S_030010_FORCE_DEGAMMA(x) … #define G_030010_FORCE_DEGAMMA(x) … #define C_030010_FORCE_DEGAMMA … #define S_030010_ENDIAN_SWAP(x) … #define G_030010_ENDIAN_SWAP(x) … #define C_030010_ENDIAN_SWAP … #define S_030010_DST_SEL_X(x) … #define G_030010_DST_SEL_X(x) … #define C_030010_DST_SEL_X … #define V_030010_SQ_SEL_X … #define V_030010_SQ_SEL_Y … #define V_030010_SQ_SEL_Z … #define V_030010_SQ_SEL_W … #define V_030010_SQ_SEL_0 … #define V_030010_SQ_SEL_1 … #define S_030010_DST_SEL_Y(x) … #define G_030010_DST_SEL_Y(x) … #define C_030010_DST_SEL_Y … #define S_030010_DST_SEL_Z(x) … #define G_030010_DST_SEL_Z(x) … #define C_030010_DST_SEL_Z … #define S_030010_DST_SEL_W(x) … #define G_030010_DST_SEL_W(x) … #define C_030010_DST_SEL_W … #define S_030010_BASE_LEVEL(x) … #define G_030010_BASE_LEVEL(x) … #define C_030010_BASE_LEVEL … #define R_030014_SQ_TEX_RESOURCE_WORD5_0 … #define S_030014_LAST_LEVEL(x) … #define G_030014_LAST_LEVEL(x) … #define C_030014_LAST_LEVEL … #define S_030014_BASE_ARRAY(x) … #define G_030014_BASE_ARRAY(x) … #define C_030014_BASE_ARRAY … #define S_030014_LAST_ARRAY(x) … #define G_030014_LAST_ARRAY(x) … #define C_030014_LAST_ARRAY … #define R_030018_SQ_TEX_RESOURCE_WORD6_0 … #define S_030018_MAX_ANISO(x) … #define G_030018_MAX_ANISO(x) … #define C_030018_MAX_ANISO … #define S_030018_PERF_MODULATION(x) … #define G_030018_PERF_MODULATION(x) … #define C_030018_PERF_MODULATION … #define S_030018_INTERLACED(x) … #define G_030018_INTERLACED(x) … #define C_030018_INTERLACED … #define S_030018_TILE_SPLIT(x) … #define G_030018_TILE_SPLIT(x) … #define R_03001C_SQ_TEX_RESOURCE_WORD7_0 … #define S_03001C_MACRO_TILE_ASPECT(x) … #define G_03001C_MACRO_TILE_ASPECT(x) … #define S_03001C_BANK_WIDTH(x) … #define G_03001C_BANK_WIDTH(x) … #define S_03001C_BANK_HEIGHT(x) … #define G_03001C_BANK_HEIGHT(x) … #define S_03001C_NUM_BANKS(x) … #define G_03001C_NUM_BANKS(x) … #define S_03001C_TYPE(x) … #define G_03001C_TYPE(x) … #define C_03001C_TYPE … #define V_03001C_SQ_TEX_VTX_INVALID_TEXTURE … #define V_03001C_SQ_TEX_VTX_INVALID_BUFFER … #define V_03001C_SQ_TEX_VTX_VALID_TEXTURE … #define V_03001C_SQ_TEX_VTX_VALID_BUFFER … #define S_03001C_DATA_FORMAT(x) … #define G_03001C_DATA_FORMAT(x) … #define C_03001C_DATA_FORMAT … #define SQ_VTX_CONSTANT_WORD0_0 … #define SQ_VTX_CONSTANT_WORD1_0 … #define SQ_VTX_CONSTANT_WORD2_0 … #define SQ_VTXC_BASE_ADDR_HI(x) … #define SQ_VTXC_STRIDE(x) … #define SQ_VTXC_ENDIAN_SWAP(x) … #define SQ_ENDIAN_NONE … #define SQ_ENDIAN_8IN16 … #define SQ_ENDIAN_8IN32 … #define SQ_VTX_CONSTANT_WORD3_0 … #define SQ_VTCX_SEL_X(x) … #define SQ_VTCX_SEL_Y(x) … #define SQ_VTCX_SEL_Z(x) … #define SQ_VTCX_SEL_W(x) … #define SQ_VTX_CONSTANT_WORD4_0 … #define SQ_VTX_CONSTANT_WORD5_0 … #define SQ_VTX_CONSTANT_WORD6_0 … #define SQ_VTX_CONSTANT_WORD7_0 … #define TD_PS_BORDER_COLOR_INDEX … #define TD_PS_BORDER_COLOR_RED … #define TD_PS_BORDER_COLOR_GREEN … #define TD_PS_BORDER_COLOR_BLUE … #define TD_PS_BORDER_COLOR_ALPHA … #define TD_VS_BORDER_COLOR_INDEX … #define TD_VS_BORDER_COLOR_RED … #define TD_VS_BORDER_COLOR_GREEN … #define TD_VS_BORDER_COLOR_BLUE … #define TD_VS_BORDER_COLOR_ALPHA … #define TD_GS_BORDER_COLOR_INDEX … #define TD_GS_BORDER_COLOR_RED … #define TD_GS_BORDER_COLOR_GREEN … #define TD_GS_BORDER_COLOR_BLUE … #define TD_GS_BORDER_COLOR_ALPHA … #define TD_HS_BORDER_COLOR_INDEX … #define TD_HS_BORDER_COLOR_RED … #define TD_HS_BORDER_COLOR_GREEN … #define TD_HS_BORDER_COLOR_BLUE … #define TD_HS_BORDER_COLOR_ALPHA … #define TD_LS_BORDER_COLOR_INDEX … #define TD_LS_BORDER_COLOR_RED … #define TD_LS_BORDER_COLOR_GREEN … #define TD_LS_BORDER_COLOR_BLUE … #define TD_LS_BORDER_COLOR_ALPHA … #define TD_CS_BORDER_COLOR_INDEX … #define TD_CS_BORDER_COLOR_RED … #define TD_CS_BORDER_COLOR_GREEN … #define TD_CS_BORDER_COLOR_BLUE … #define TD_CS_BORDER_COLOR_ALPHA … /* cayman 3D regs */ #define CAYMAN_VGT_OFFCHIP_LDS_BASE … #define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS … #define CAYMAN_DB_EQAA … #define CAYMAN_DB_DEPTH_INFO … #define CAYMAN_PA_SC_AA_CONFIG … #define CAYMAN_MSAA_NUM_SAMPLES_SHIFT … #define CAYMAN_MSAA_NUM_SAMPLES_MASK … #define CAYMAN_SX_SCATTER_EXPORT_BASE … /* cayman packet3 addition */ #define CAYMAN_PACKET3_DEALLOC_STATE … /* DMA regs common on r6xx/r7xx/evergreen/ni */ #define DMA_RB_CNTL … #define DMA_RB_ENABLE … #define DMA_RB_SIZE(x) … #define DMA_RB_SWAP_ENABLE … #define DMA_RPTR_WRITEBACK_ENABLE … #define DMA_RPTR_WRITEBACK_SWAP_ENABLE … #define DMA_RPTR_WRITEBACK_TIMER(x) … #define DMA_STATUS_REG … #define DMA_IDLE … #endif
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