/* * Copyright 2010 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Alex Deucher */ #ifndef NI_H #define NI_H #define CAYMAN_MAX_SH_GPRS … #define CAYMAN_MAX_TEMP_GPRS … #define CAYMAN_MAX_SH_THREADS … #define CAYMAN_MAX_SH_STACK_ENTRIES … #define CAYMAN_MAX_FRC_EOV_CNT … #define CAYMAN_MAX_BACKENDS … #define CAYMAN_MAX_BACKENDS_MASK … #define CAYMAN_MAX_BACKENDS_PER_SE_MASK … #define CAYMAN_MAX_SIMDS … #define CAYMAN_MAX_SIMDS_MASK … #define CAYMAN_MAX_SIMDS_PER_SE_MASK … #define CAYMAN_MAX_PIPES … #define CAYMAN_MAX_PIPES_MASK … #define CAYMAN_MAX_LDS_NUM … #define CAYMAN_MAX_TCC … #define CAYMAN_MAX_TCC_MASK … #define CAYMAN_GB_ADDR_CONFIG_GOLDEN … #define ARUBA_GB_ADDR_CONFIG_GOLDEN … #define DMIF_ADDR_CONFIG … /* fusion vce clocks */ #define CG_ECLK_CNTL … #define ECLK_DIVIDER_MASK … #define ECLK_DIR_CNTL_EN … #define CG_ECLK_STATUS … #define ECLK_STATUS … /* DCE6 only */ #define DMIF_ADDR_CALC … #define SRBM_GFX_CNTL … #define RINGID(x) … #define VMID(x) … #define SRBM_STATUS … #define RLC_RQ_PENDING … #define GRBM_RQ_PENDING … #define VMC_BUSY … #define MCB_BUSY … #define MCB_NON_DISPLAY_BUSY … #define MCC_BUSY … #define MCD_BUSY … #define SEM_BUSY … #define RLC_BUSY … #define IH_BUSY … #define SRBM_SOFT_RESET … #define SOFT_RESET_BIF … #define SOFT_RESET_CG … #define SOFT_RESET_DC … #define SOFT_RESET_DMA1 … #define SOFT_RESET_GRBM … #define SOFT_RESET_HDP … #define SOFT_RESET_IH … #define SOFT_RESET_MC … #define SOFT_RESET_RLC … #define SOFT_RESET_ROM … #define SOFT_RESET_SEM … #define SOFT_RESET_VMC … #define SOFT_RESET_DMA … #define SOFT_RESET_TST … #define SOFT_RESET_REGBB … #define SOFT_RESET_ORB … #define SRBM_READ_ERROR … #define SRBM_INT_CNTL … #define SRBM_INT_ACK … #define SRBM_STATUS2 … #define DMA_BUSY … #define DMA1_BUSY … #define VM_CONTEXT0_REQUEST_RESPONSE … #define REQUEST_TYPE(x) … #define RESPONSE_TYPE_MASK … #define RESPONSE_TYPE_SHIFT … #define VM_L2_CNTL … #define ENABLE_L2_CACHE … #define ENABLE_L2_FRAGMENT_PROCESSING … #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE … #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE … #define EFFECTIVE_L2_QUEUE_SIZE(x) … #define CONTEXT1_IDENTITY_ACCESS_MODE(x) … /* CONTEXT1_IDENTITY_ACCESS_MODE * 0 physical = logical * 1 logical via context1 page table * 2 inside identity aperture use translation, outside physical = logical * 3 inside identity aperture physical = logical, outside use translation */ #define VM_L2_CNTL2 … #define INVALIDATE_ALL_L1_TLBS … #define INVALIDATE_L2_CACHE … #define VM_L2_CNTL3 … #define BANK_SELECT(x) … #define CACHE_UPDATE_MODE(x) … #define L2_CACHE_BIGK_ASSOCIATIVITY … #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) … #define VM_L2_STATUS … #define L2_BUSY … #define VM_CONTEXT0_CNTL … #define ENABLE_CONTEXT … #define PAGE_TABLE_DEPTH(x) … #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT … #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT … #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT … #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT … #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT … #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT … #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT … #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT … #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT … #define READ_PROTECTION_FAULT_ENABLE_DEFAULT … #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT … #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT … #define PAGE_TABLE_BLOCK_SIZE(x) … #define VM_CONTEXT1_CNTL … #define VM_CONTEXT0_CNTL2 … #define VM_CONTEXT1_CNTL2 … #define VM_INVALIDATE_REQUEST … #define VM_INVALIDATE_RESPONSE … #define VM_CONTEXT1_PROTECTION_FAULT_ADDR … #define VM_CONTEXT1_PROTECTION_FAULT_STATUS … #define PROTECTIONS_MASK … #define PROTECTIONS_SHIFT … /* bit 0: range * bit 2: pde0 * bit 3: valid * bit 4: read * bit 5: write */ #define MEMORY_CLIENT_ID_MASK … #define MEMORY_CLIENT_ID_SHIFT … #define MEMORY_CLIENT_RW_MASK … #define MEMORY_CLIENT_RW_SHIFT … #define FAULT_VMID_MASK … #define FAULT_VMID_SHIFT … #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR … #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR … #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT0_PAGE_TABLE_START_ADDR … #define VM_CONTEXT0_PAGE_TABLE_END_ADDR … #define MC_SHARED_CHMAP … #define NOOFCHAN_SHIFT … #define NOOFCHAN_MASK … #define MC_SHARED_CHREMAP … #define MC_VM_SYSTEM_APERTURE_LOW_ADDR … #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR … #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR … #define MC_VM_MX_L1_TLB_CNTL … #define ENABLE_L1_TLB … #define ENABLE_L1_FRAGMENT_PROCESSING … #define SYSTEM_ACCESS_MODE_PA_ONLY … #define SYSTEM_ACCESS_MODE_USE_SYS_MAP … #define SYSTEM_ACCESS_MODE_IN_SYS … #define SYSTEM_ACCESS_MODE_NOT_IN_SYS … #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU … #define ENABLE_ADVANCED_DRIVER_MODEL … #define FUS_MC_VM_FB_OFFSET … #define MC_SHARED_BLACKOUT_CNTL … #define MC_ARB_RAMCFG … #define NOOFBANK_SHIFT … #define NOOFBANK_MASK … #define NOOFRANK_SHIFT … #define NOOFRANK_MASK … #define NOOFROWS_SHIFT … #define NOOFROWS_MASK … #define NOOFCOLS_SHIFT … #define NOOFCOLS_MASK … #define CHANSIZE_SHIFT … #define CHANSIZE_MASK … #define BURSTLENGTH_SHIFT … #define BURSTLENGTH_MASK … #define CHANSIZE_OVERRIDE … #define MC_SEQ_SUP_CNTL … #define RUN_MASK … #define MC_SEQ_SUP_PGM … #define MC_IO_PAD_CNTL_D0 … #define MEM_FALL_OUT_CMD … #define MC_SEQ_MISC0 … #define MC_SEQ_MISC0_GDDR5_SHIFT … #define MC_SEQ_MISC0_GDDR5_MASK … #define MC_SEQ_MISC0_GDDR5_VALUE … #define MC_SEQ_IO_DEBUG_INDEX … #define MC_SEQ_IO_DEBUG_DATA … #define HDP_HOST_PATH_CNTL … #define HDP_NONSURFACE_BASE … #define HDP_NONSURFACE_INFO … #define HDP_NONSURFACE_SIZE … #define HDP_ADDR_CONFIG … #define HDP_MISC_CNTL … #define HDP_FLUSH_INVALIDATE_CACHE … #define CC_SYS_RB_BACKEND_DISABLE … #define GC_USER_SYS_RB_BACKEND_DISABLE … #define CGTS_SYS_TCC_DISABLE … #define CGTS_USER_SYS_TCC_DISABLE … #define RLC_GFX_INDEX … #define CONFIG_MEMSIZE … #define HDP_MEM_COHERENCY_FLUSH_CNTL … #define HDP_REG_COHERENCY_FLUSH_CNTL … #define GRBM_CNTL … #define GRBM_READ_TIMEOUT(x) … #define GRBM_STATUS … #define CMDFIFO_AVAIL_MASK … #define RING2_RQ_PENDING … #define SRBM_RQ_PENDING … #define RING1_RQ_PENDING … #define CF_RQ_PENDING … #define PF_RQ_PENDING … #define GDS_DMA_RQ_PENDING … #define GRBM_EE_BUSY … #define SX_CLEAN … #define DB_CLEAN … #define CB_CLEAN … #define TA_BUSY … #define GDS_BUSY … #define VGT_BUSY_NO_DMA … #define VGT_BUSY … #define IA_BUSY_NO_DMA … #define IA_BUSY … #define SX_BUSY … #define SH_BUSY … #define SPI_BUSY … #define SC_BUSY … #define PA_BUSY … #define DB_BUSY … #define CP_COHERENCY_BUSY … #define CP_BUSY … #define CB_BUSY … #define GUI_ACTIVE … #define GRBM_STATUS_SE0 … #define GRBM_STATUS_SE1 … #define SE_SX_CLEAN … #define SE_DB_CLEAN … #define SE_CB_CLEAN … #define SE_VGT_BUSY … #define SE_PA_BUSY … #define SE_TA_BUSY … #define SE_SX_BUSY … #define SE_SPI_BUSY … #define SE_SH_BUSY … #define SE_SC_BUSY … #define SE_DB_BUSY … #define SE_CB_BUSY … #define GRBM_SOFT_RESET … #define SOFT_RESET_CP … #define SOFT_RESET_CB … #define SOFT_RESET_DB … #define SOFT_RESET_GDS … #define SOFT_RESET_PA … #define SOFT_RESET_SC … #define SOFT_RESET_SPI … #define SOFT_RESET_SH … #define SOFT_RESET_SX … #define SOFT_RESET_TC … #define SOFT_RESET_TA … #define SOFT_RESET_VGT … #define SOFT_RESET_IA … #define GRBM_GFX_INDEX … #define INSTANCE_INDEX(x) … #define SE_INDEX(x) … #define INSTANCE_BROADCAST_WRITES … #define SE_BROADCAST_WRITES … #define SCRATCH_REG0 … #define SCRATCH_REG1 … #define SCRATCH_REG2 … #define SCRATCH_REG3 … #define SCRATCH_REG4 … #define SCRATCH_REG5 … #define SCRATCH_REG6 … #define SCRATCH_REG7 … #define SCRATCH_UMSK … #define SCRATCH_ADDR … #define CP_SEM_WAIT_TIMER … #define CP_SEM_INCOMPLETE_TIMER_CNTL … #define CP_COHER_CNTL2 … #define CP_STALLED_STAT1 … #define CP_STALLED_STAT2 … #define CP_BUSY_STAT … #define CP_STAT … #define CP_ME_CNTL … #define CP_ME_HALT … #define CP_PFP_HALT … #define CP_RB2_RPTR … #define CP_RB1_RPTR … #define CP_RB0_RPTR … #define CP_RB_WPTR_DELAY … #define CP_MEQ_THRESHOLDS … #define MEQ1_START(x) … #define MEQ2_START(x) … #define CP_PERFMON_CNTL … #define VGT_CACHE_INVALIDATION … #define CACHE_INVALIDATION(x) … #define VC_ONLY … #define TC_ONLY … #define VC_AND_TC … #define AUTO_INVLD_EN(x) … #define NO_AUTO … #define ES_AUTO … #define GS_AUTO … #define ES_AND_GS_AUTO … #define VGT_GS_VERTEX_REUSE … #define CC_GC_SHADER_PIPE_CONFIG … #define GC_USER_SHADER_PIPE_CONFIG … #define INACTIVE_QD_PIPES(x) … #define INACTIVE_QD_PIPES_MASK … #define INACTIVE_QD_PIPES_SHIFT … #define INACTIVE_SIMDS(x) … #define INACTIVE_SIMDS_MASK … #define INACTIVE_SIMDS_SHIFT … #define VGT_PRIMITIVE_TYPE … #define VGT_NUM_INSTANCES … #define VGT_TF_RING_SIZE … #define VGT_OFFCHIP_LDS_BASE … #define PA_SC_LINE_STIPPLE_STATE … #define PA_CL_ENHANCE … #define CLIP_VTX_REORDER_ENA … #define NUM_CLIP_SEQ(x) … #define PA_SC_FIFO_SIZE … #define SC_PRIM_FIFO_SIZE(x) … #define SC_HIZ_TILE_FIFO_SIZE(x) … #define SC_EARLYZ_TILE_FIFO_SIZE(x) … #define PA_SC_FORCE_EOV_MAX_CNTS … #define FORCE_EOV_MAX_CLK_CNT(x) … #define FORCE_EOV_MAX_REZ_CNT(x) … #define SQ_CONFIG … #define VC_ENABLE … #define EXPORT_SRC_C … #define GFX_PRIO(x) … #define CS1_PRIO(x) … #define CS2_PRIO(x) … #define SQ_GPR_RESOURCE_MGMT_1 … #define NUM_PS_GPRS(x) … #define NUM_VS_GPRS(x) … #define NUM_CLAUSE_TEMP_GPRS(x) … #define SQ_ESGS_RING_SIZE … #define SQ_GSVS_RING_SIZE … #define SQ_ESTMP_RING_BASE … #define SQ_ESTMP_RING_SIZE … #define SQ_GSTMP_RING_BASE … #define SQ_GSTMP_RING_SIZE … #define SQ_VSTMP_RING_BASE … #define SQ_VSTMP_RING_SIZE … #define SQ_PSTMP_RING_BASE … #define SQ_PSTMP_RING_SIZE … #define SQ_MS_FIFO_SIZES … #define CACHE_FIFO_SIZE(x) … #define FETCH_FIFO_HIWATER(x) … #define DONE_FIFO_HIWATER(x) … #define ALU_UPDATE_FIFO_HIWATER(x) … #define SQ_LSTMP_RING_BASE … #define SQ_LSTMP_RING_SIZE … #define SQ_HSTMP_RING_BASE … #define SQ_HSTMP_RING_SIZE … #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ … #define DYN_GPR_ENABLE … #define SQ_CONST_MEM_BASE … #define SX_EXPORT_BUFFER_SIZES … #define COLOR_BUFFER_SIZE(x) … #define POSITION_BUFFER_SIZE(x) … #define SMX_BUFFER_SIZE(x) … #define SX_DEBUG_1 … #define ENABLE_NEW_SMX_ADDRESS … #define SPI_CONFIG_CNTL … #define GPR_WRITE_PRIORITY(x) … #define SPI_CONFIG_CNTL_1 … #define VTX_DONE_DELAY(x) … #define INTERP_ONE_PRIM_PER_ROW … #define CRC_SIMD_ID_WADDR_DISABLE … #define CGTS_TCC_DISABLE … #define CGTS_USER_TCC_DISABLE … #define TCC_DISABLE_MASK … #define TCC_DISABLE_SHIFT … #define CGTS_SM_CTRL_REG … #define OVERRIDE … #define TA_CNTL_AUX … #define DISABLE_CUBE_WRAP … #define DISABLE_CUBE_ANISO … #define TCP_CHAN_STEER_LO … #define TCP_CHAN_STEER_HI … #define CC_RB_BACKEND_DISABLE … #define BACKEND_DISABLE(x) … #define GB_ADDR_CONFIG … #define NUM_PIPES(x) … #define NUM_PIPES_MASK … #define NUM_PIPES_SHIFT … #define PIPE_INTERLEAVE_SIZE(x) … #define PIPE_INTERLEAVE_SIZE_MASK … #define PIPE_INTERLEAVE_SIZE_SHIFT … #define BANK_INTERLEAVE_SIZE(x) … #define NUM_SHADER_ENGINES(x) … #define NUM_SHADER_ENGINES_MASK … #define NUM_SHADER_ENGINES_SHIFT … #define SHADER_ENGINE_TILE_SIZE(x) … #define SHADER_ENGINE_TILE_SIZE_MASK … #define SHADER_ENGINE_TILE_SIZE_SHIFT … #define NUM_GPUS(x) … #define NUM_GPUS_MASK … #define NUM_GPUS_SHIFT … #define MULTI_GPU_TILE_SIZE(x) … #define MULTI_GPU_TILE_SIZE_MASK … #define MULTI_GPU_TILE_SIZE_SHIFT … #define ROW_SIZE(x) … #define ROW_SIZE_MASK … #define ROW_SIZE_SHIFT … #define NUM_LOWER_PIPES(x) … #define NUM_LOWER_PIPES_MASK … #define NUM_LOWER_PIPES_SHIFT … #define GB_BACKEND_MAP … #define CB_PERF_CTR0_SEL_0 … #define CB_PERF_CTR0_SEL_1 … #define CB_PERF_CTR1_SEL_0 … #define CB_PERF_CTR1_SEL_1 … #define CB_PERF_CTR2_SEL_0 … #define CB_PERF_CTR2_SEL_1 … #define CB_PERF_CTR3_SEL_0 … #define CB_PERF_CTR3_SEL_1 … #define GC_USER_RB_BACKEND_DISABLE … #define BACKEND_DISABLE_MASK … #define BACKEND_DISABLE_SHIFT … #define SMX_DC_CTL0 … #define USE_HASH_FUNCTION … #define NUMBER_OF_SETS(x) … #define FLUSH_ALL_ON_EVENT … #define STALL_ON_EVENT … #define SMX_EVENT_CTL … #define ES_FLUSH_CTL(x) … #define GS_FLUSH_CTL(x) … #define ACK_FLUSH_CTL(x) … #define SYNC_FLUSH_CTL … #define CP_RB0_BASE … #define CP_RB0_CNTL … #define RB_BUFSZ(x) … #define RB_BLKSZ(x) … #define RB_NO_UPDATE … #define RB_RPTR_WR_ENA … #define BUF_SWAP_32BIT … #define CP_RB0_RPTR_ADDR … #define CP_RB0_RPTR_ADDR_HI … #define CP_RB0_WPTR … #define CP_INT_CNTL … #define CNTX_BUSY_INT_ENABLE … #define CNTX_EMPTY_INT_ENABLE … #define TIME_STAMP_INT_ENABLE … #define CP_RB1_BASE … #define CP_RB1_CNTL … #define CP_RB1_RPTR_ADDR … #define CP_RB1_RPTR_ADDR_HI … #define CP_RB1_WPTR … #define CP_RB2_BASE … #define CP_RB2_CNTL … #define CP_RB2_RPTR_ADDR … #define CP_RB2_RPTR_ADDR_HI … #define CP_RB2_WPTR … #define CP_PFP_UCODE_ADDR … #define CP_PFP_UCODE_DATA … #define CP_ME_RAM_RADDR … #define CP_ME_RAM_WADDR … #define CP_ME_RAM_DATA … #define CP_DEBUG … #define VGT_EVENT_INITIATOR … #define CACHE_FLUSH_AND_INV_EVENT_TS … #define CACHE_FLUSH_AND_INV_EVENT … /* TN SMU registers */ #define TN_CURRENT_GNB_TEMP … /* pm registers */ #define SMC_MSG … #define HOST_SMC_MSG(x) … #define HOST_SMC_MSG_MASK … #define HOST_SMC_MSG_SHIFT … #define HOST_SMC_RESP(x) … #define HOST_SMC_RESP_MASK … #define HOST_SMC_RESP_SHIFT … #define SMC_HOST_MSG(x) … #define SMC_HOST_MSG_MASK … #define SMC_HOST_MSG_SHIFT … #define SMC_HOST_RESP(x) … #define SMC_HOST_RESP_MASK … #define SMC_HOST_RESP_SHIFT … #define CG_SPLL_FUNC_CNTL … #define SPLL_RESET … #define SPLL_SLEEP … #define SPLL_BYPASS_EN … #define SPLL_REF_DIV(x) … #define SPLL_REF_DIV_MASK … #define SPLL_PDIV_A(x) … #define SPLL_PDIV_A_MASK … #define SPLL_PDIV_A_SHIFT … #define CG_SPLL_FUNC_CNTL_2 … #define SCLK_MUX_SEL(x) … #define SCLK_MUX_SEL_MASK … #define CG_SPLL_FUNC_CNTL_3 … #define SPLL_FB_DIV(x) … #define SPLL_FB_DIV_MASK … #define SPLL_FB_DIV_SHIFT … #define SPLL_DITHEN … #define MPLL_CNTL_MODE … #define SS_SSEN … #define SS_DSMODE_EN … #define MPLL_AD_FUNC_CNTL … #define CLKF(x) … #define CLKF_MASK … #define CLKR(x) … #define CLKR_MASK … #define CLKFRAC(x) … #define CLKFRAC_MASK … #define YCLK_POST_DIV(x) … #define YCLK_POST_DIV_MASK … #define IBIAS(x) … #define IBIAS_MASK … #define RESET … #define PDNB … #define MPLL_AD_FUNC_CNTL_2 … #define BYPASS … #define BIAS_GEN_PDNB … #define RESET_EN … #define VCO_MODE … #define MPLL_DQ_FUNC_CNTL … #define MPLL_DQ_FUNC_CNTL_2 … #define GENERAL_PWRMGT … #define GLOBAL_PWRMGT_EN … #define STATIC_PM_EN … #define THERMAL_PROTECTION_DIS … #define THERMAL_PROTECTION_TYPE … #define ENABLE_GEN2PCIE … #define ENABLE_GEN2XSP … #define SW_SMIO_INDEX(x) … #define SW_SMIO_INDEX_MASK … #define SW_SMIO_INDEX_SHIFT … #define LOW_VOLT_D2_ACPI … #define LOW_VOLT_D3_ACPI … #define VOLT_PWRMGT_EN … #define BACKBIAS_PAD_EN … #define BACKBIAS_VALUE … #define DYN_SPREAD_SPECTRUM_EN … #define AC_DC_SW … #define SCLK_PWRMGT_CNTL … #define SCLK_PWRMGT_OFF … #define SCLK_LOW_D1 … #define FIR_RESET … #define FIR_FORCE_TREND_SEL … #define FIR_TREND_MODE … #define DYN_GFX_CLK_OFF_EN … #define GFX_CLK_FORCE_ON … #define GFX_CLK_REQUEST_OFF … #define GFX_CLK_FORCE_OFF … #define GFX_CLK_OFF_ACPI_D1 … #define GFX_CLK_OFF_ACPI_D2 … #define GFX_CLK_OFF_ACPI_D3 … #define DYN_LIGHT_SLEEP_EN … #define MCLK_PWRMGT_CNTL … #define DLL_SPEED(x) … #define DLL_SPEED_MASK … #define MPLL_PWRMGT_OFF … #define DLL_READY … #define MC_INT_CNTL … #define MRDCKA0_PDNB … #define MRDCKA1_PDNB … #define MRDCKB0_PDNB … #define MRDCKB1_PDNB … #define MRDCKC0_PDNB … #define MRDCKC1_PDNB … #define MRDCKD0_PDNB … #define MRDCKD1_PDNB … #define MRDCKA0_RESET … #define MRDCKA1_RESET … #define MRDCKB0_RESET … #define MRDCKB1_RESET … #define MRDCKC0_RESET … #define MRDCKC1_RESET … #define MRDCKD0_RESET … #define MRDCKD1_RESET … #define DLL_READY_READ … #define USE_DISPLAY_GAP … #define USE_DISPLAY_URGENT_NORMAL … #define MPLL_TURNOFF_D2 … #define DLL_CNTL … #define MRDCKA0_BYPASS … #define MRDCKA1_BYPASS … #define MRDCKB0_BYPASS … #define MRDCKB1_BYPASS … #define MRDCKC0_BYPASS … #define MRDCKC1_BYPASS … #define MRDCKD0_BYPASS … #define MRDCKD1_BYPASS … #define TARGET_AND_CURRENT_PROFILE_INDEX … #define CURRENT_STATE_INDEX_MASK … #define CURRENT_STATE_INDEX_SHIFT … #define CG_AT … #define CG_R(x) … #define CG_R_MASK … #define CG_L(x) … #define CG_L_MASK … #define CG_BIF_REQ_AND_RSP … #define CG_CLIENT_REQ(x) … #define CG_CLIENT_REQ_MASK … #define CG_CLIENT_REQ_SHIFT … #define CG_CLIENT_RESP(x) … #define CG_CLIENT_RESP_MASK … #define CG_CLIENT_RESP_SHIFT … #define CLIENT_CG_REQ(x) … #define CLIENT_CG_REQ_MASK … #define CLIENT_CG_REQ_SHIFT … #define CLIENT_CG_RESP(x) … #define CLIENT_CG_RESP_MASK … #define CLIENT_CG_RESP_SHIFT … #define CG_SPLL_SPREAD_SPECTRUM … #define SSEN … #define CLK_S(x) … #define CLK_S_MASK … #define CLK_S_SHIFT … #define CG_SPLL_SPREAD_SPECTRUM_2 … #define CLK_V(x) … #define CLK_V_MASK … #define CLK_V_SHIFT … #define SMC_SCRATCH0 … #define CG_SPLL_FUNC_CNTL_4 … #define MPLL_SS1 … #define CLKV(x) … #define CLKV_MASK … #define MPLL_SS2 … #define CLKS(x) … #define CLKS_MASK … #define CG_CAC_CTRL … #define TID_CNT(x) … #define TID_CNT_MASK … #define TID_UNIT(x) … #define TID_UNIT_MASK … #define CG_IND_ADDR … #define CG_IND_DATA … /* CGIND regs */ #define CG_CGTT_LOCAL_0 … #define CG_CGTT_LOCAL_1 … #define MC_CG_CONFIG … #define MCDW_WR_ENABLE … #define MCDX_WR_ENABLE … #define MCDY_WR_ENABLE … #define MCDZ_WR_ENABLE … #define MC_RD_ENABLE(x) … #define MC_RD_ENABLE_MASK … #define INDEX(x) … #define INDEX_MASK … #define INDEX_SHIFT … #define MC_ARB_CAC_CNTL … #define ENABLE … #define READ_WEIGHT(x) … #define READ_WEIGHT_MASK … #define READ_WEIGHT_SHIFT … #define WRITE_WEIGHT(x) … #define WRITE_WEIGHT_MASK … #define WRITE_WEIGHT_SHIFT … #define ALLOW_OVERFLOW … #define MC_ARB_DRAM_TIMING … #define MC_ARB_DRAM_TIMING2 … #define MC_ARB_RFSH_RATE … #define POWERMODE0(x) … #define POWERMODE0_MASK … #define POWERMODE0_SHIFT … #define POWERMODE1(x) … #define POWERMODE1_MASK … #define POWERMODE1_SHIFT … #define POWERMODE2(x) … #define POWERMODE2_MASK … #define POWERMODE2_SHIFT … #define POWERMODE3(x) … #define POWERMODE3_MASK … #define POWERMODE3_SHIFT … #define MC_ARB_CG … #define CG_ARB_REQ(x) … #define CG_ARB_REQ_MASK … #define CG_ARB_REQ_SHIFT … #define CG_ARB_RESP(x) … #define CG_ARB_RESP_MASK … #define CG_ARB_RESP_SHIFT … #define ARB_CG_REQ(x) … #define ARB_CG_REQ_MASK … #define ARB_CG_REQ_SHIFT … #define ARB_CG_RESP(x) … #define ARB_CG_RESP_MASK … #define ARB_CG_RESP_SHIFT … #define MC_ARB_DRAM_TIMING_1 … #define MC_ARB_DRAM_TIMING_2 … #define MC_ARB_DRAM_TIMING_3 … #define MC_ARB_DRAM_TIMING2_1 … #define MC_ARB_DRAM_TIMING2_2 … #define MC_ARB_DRAM_TIMING2_3 … #define MC_ARB_BURST_TIME … #define STATE0(x) … #define STATE0_MASK … #define STATE0_SHIFT … #define STATE1(x) … #define STATE1_MASK … #define STATE1_SHIFT … #define STATE2(x) … #define STATE2_MASK … #define STATE2_SHIFT … #define STATE3(x) … #define STATE3_MASK … #define STATE3_SHIFT … #define MC_CG_DATAPORT … #define MC_SEQ_RAS_TIMING … #define MC_SEQ_CAS_TIMING … #define MC_SEQ_MISC_TIMING … #define MC_SEQ_MISC_TIMING2 … #define MC_SEQ_PMG_TIMING … #define MC_SEQ_RD_CTL_D0 … #define MC_SEQ_RD_CTL_D1 … #define MC_SEQ_WR_CTL_D0 … #define MC_SEQ_WR_CTL_D1 … #define MC_SEQ_MISC0 … #define MC_SEQ_MISC0_GDDR5_SHIFT … #define MC_SEQ_MISC0_GDDR5_MASK … #define MC_SEQ_MISC0_GDDR5_VALUE … #define MC_SEQ_MISC1 … #define MC_SEQ_RESERVE_M … #define MC_PMG_CMD_EMRS … #define MC_SEQ_MISC3 … #define MC_SEQ_MISC5 … #define MC_SEQ_MISC6 … #define MC_SEQ_MISC7 … #define MC_SEQ_RAS_TIMING_LP … #define MC_SEQ_CAS_TIMING_LP … #define MC_SEQ_MISC_TIMING_LP … #define MC_SEQ_MISC_TIMING2_LP … #define MC_SEQ_WR_CTL_D0_LP … #define MC_SEQ_WR_CTL_D1_LP … #define MC_SEQ_PMG_CMD_EMRS_LP … #define MC_SEQ_PMG_CMD_MRS_LP … #define MC_PMG_CMD_MRS … #define MC_SEQ_RD_CTL_D0_LP … #define MC_SEQ_RD_CTL_D1_LP … #define MC_PMG_CMD_MRS1 … #define MC_SEQ_PMG_CMD_MRS1_LP … #define MC_SEQ_PMG_TIMING_LP … #define MC_PMG_CMD_MRS2 … #define MC_SEQ_PMG_CMD_MRS2_LP … #define AUX_CONTROL … #define AUX_EN … #define AUX_LS_READ_EN … #define AUX_LS_UPDATE_DISABLE(x) … #define AUX_HPD_DISCON(x) … #define AUX_DET_EN … #define AUX_HPD_SEL(x) … #define AUX_IMPCAL_REQ_EN … #define AUX_TEST_MODE … #define AUX_DEGLITCH_EN … #define AUX_SW_CONTROL … #define AUX_SW_GO … #define AUX_LS_READ_TRIG … #define AUX_SW_START_DELAY(x) … #define AUX_SW_WR_BYTES(x) … #define AUX_SW_INTERRUPT_CONTROL … #define AUX_SW_DONE_INT … #define AUX_SW_DONE_ACK … #define AUX_SW_DONE_MASK … #define AUX_SW_LS_DONE_INT … #define AUX_SW_LS_DONE_MASK … #define AUX_SW_STATUS … #define AUX_SW_DONE … #define AUX_SW_REQ … #define AUX_SW_RX_TIMEOUT_STATE(x) … #define AUX_SW_RX_TIMEOUT … #define AUX_SW_RX_OVERFLOW … #define AUX_SW_RX_HPD_DISCON … #define AUX_SW_RX_PARTIAL_BYTE … #define AUX_SW_NON_AUX_MODE … #define AUX_SW_RX_MIN_COUNT_VIOL … #define AUX_SW_RX_INVALID_STOP … #define AUX_SW_RX_SYNC_INVALID_L … #define AUX_SW_RX_SYNC_INVALID_H … #define AUX_SW_RX_INVALID_START … #define AUX_SW_RX_RECV_NO_DET … #define AUX_SW_RX_RECV_INVALID_H … #define AUX_SW_RX_RECV_INVALID_V … #define AUX_SW_DATA … #define AUX_SW_DATA_RW … #define AUX_SW_DATA_MASK(x) … #define AUX_SW_DATA_INDEX(x) … #define AUX_SW_AUTOINCREMENT_DISABLE … #define LB_SYNC_RESET_SEL … #define LB_SYNC_RESET_SEL_MASK … #define LB_SYNC_RESET_SEL_SHIFT … #define DC_STUTTER_CNTL … #define DC_STUTTER_ENABLE_A … #define DC_STUTTER_ENABLE_B … #define SQ_CAC_THRESHOLD … #define VSP(x) … #define VSP_MASK … #define VSP_SHIFT … #define VSP0(x) … #define VSP0_MASK … #define VSP0_SHIFT … #define GPR(x) … #define GPR_MASK … #define GPR_SHIFT … #define SQ_POWER_THROTTLE … #define MIN_POWER(x) … #define MIN_POWER_MASK … #define MIN_POWER_SHIFT … #define MAX_POWER(x) … #define MAX_POWER_MASK … #define MAX_POWER_SHIFT … #define SQ_POWER_THROTTLE2 … #define MAX_POWER_DELTA(x) … #define MAX_POWER_DELTA_MASK … #define MAX_POWER_DELTA_SHIFT … #define STI_SIZE(x) … #define STI_SIZE_MASK … #define STI_SIZE_SHIFT … #define LTI_RATIO(x) … #define LTI_RATIO_MASK … #define LTI_RATIO_SHIFT … /* CG indirect registers */ #define CG_CAC_REGION_1_WEIGHT_0 … #define WEIGHT_TCP_SIG0(x) … #define WEIGHT_TCP_SIG0_MASK … #define WEIGHT_TCP_SIG0_SHIFT … #define WEIGHT_TCP_SIG1(x) … #define WEIGHT_TCP_SIG1_MASK … #define WEIGHT_TCP_SIG1_SHIFT … #define WEIGHT_TA_SIG(x) … #define WEIGHT_TA_SIG_MASK … #define WEIGHT_TA_SIG_SHIFT … #define CG_CAC_REGION_1_WEIGHT_1 … #define WEIGHT_TCC_EN0(x) … #define WEIGHT_TCC_EN0_MASK … #define WEIGHT_TCC_EN0_SHIFT … #define WEIGHT_TCC_EN1(x) … #define WEIGHT_TCC_EN1_MASK … #define WEIGHT_TCC_EN1_SHIFT … #define WEIGHT_TCC_EN2(x) … #define WEIGHT_TCC_EN2_MASK … #define WEIGHT_TCC_EN2_SHIFT … #define WEIGHT_TCC_EN3(x) … #define WEIGHT_TCC_EN3_MASK … #define WEIGHT_TCC_EN3_SHIFT … #define CG_CAC_REGION_2_WEIGHT_0 … #define WEIGHT_CB_EN0(x) … #define WEIGHT_CB_EN0_MASK … #define WEIGHT_CB_EN0_SHIFT … #define WEIGHT_CB_EN1(x) … #define WEIGHT_CB_EN1_MASK … #define WEIGHT_CB_EN1_SHIFT … #define WEIGHT_CB_EN2(x) … #define WEIGHT_CB_EN2_MASK … #define WEIGHT_CB_EN2_SHIFT … #define WEIGHT_CB_EN3(x) … #define WEIGHT_CB_EN3_MASK … #define WEIGHT_CB_EN3_SHIFT … #define CG_CAC_REGION_2_WEIGHT_1 … #define WEIGHT_DB_SIG0(x) … #define WEIGHT_DB_SIG0_MASK … #define WEIGHT_DB_SIG0_SHIFT … #define WEIGHT_DB_SIG1(x) … #define WEIGHT_DB_SIG1_MASK … #define WEIGHT_DB_SIG1_SHIFT … #define WEIGHT_DB_SIG2(x) … #define WEIGHT_DB_SIG2_MASK … #define WEIGHT_DB_SIG2_SHIFT … #define WEIGHT_DB_SIG3(x) … #define WEIGHT_DB_SIG3_MASK … #define WEIGHT_DB_SIG3_SHIFT … #define CG_CAC_REGION_2_WEIGHT_2 … #define WEIGHT_SXM_SIG0(x) … #define WEIGHT_SXM_SIG0_MASK … #define WEIGHT_SXM_SIG0_SHIFT … #define WEIGHT_SXM_SIG1(x) … #define WEIGHT_SXM_SIG1_MASK … #define WEIGHT_SXM_SIG1_SHIFT … #define WEIGHT_SXM_SIG2(x) … #define WEIGHT_SXM_SIG2_MASK … #define WEIGHT_SXM_SIG2_SHIFT … #define WEIGHT_SXS_SIG0(x) … #define WEIGHT_SXS_SIG0_MASK … #define WEIGHT_SXS_SIG0_SHIFT … #define WEIGHT_SXS_SIG1(x) … #define WEIGHT_SXS_SIG1_MASK … #define WEIGHT_SXS_SIG1_SHIFT … #define CG_CAC_REGION_3_WEIGHT_0 … #define WEIGHT_XBR_0(x) … #define WEIGHT_XBR_0_MASK … #define WEIGHT_XBR_0_SHIFT … #define WEIGHT_XBR_1(x) … #define WEIGHT_XBR_1_MASK … #define WEIGHT_XBR_1_SHIFT … #define WEIGHT_XBR_2(x) … #define WEIGHT_XBR_2_MASK … #define WEIGHT_XBR_2_SHIFT … #define WEIGHT_SPI_SIG0(x) … #define WEIGHT_SPI_SIG0_MASK … #define WEIGHT_SPI_SIG0_SHIFT … #define CG_CAC_REGION_3_WEIGHT_1 … #define WEIGHT_SPI_SIG1(x) … #define WEIGHT_SPI_SIG1_MASK … #define WEIGHT_SPI_SIG1_SHIFT … #define WEIGHT_SPI_SIG2(x) … #define WEIGHT_SPI_SIG2_MASK … #define WEIGHT_SPI_SIG2_SHIFT … #define WEIGHT_SPI_SIG3(x) … #define WEIGHT_SPI_SIG3_MASK … #define WEIGHT_SPI_SIG3_SHIFT … #define WEIGHT_SPI_SIG4(x) … #define WEIGHT_SPI_SIG4_MASK … #define WEIGHT_SPI_SIG4_SHIFT … #define WEIGHT_SPI_SIG5(x) … #define WEIGHT_SPI_SIG5_MASK … #define WEIGHT_SPI_SIG5_SHIFT … #define CG_CAC_REGION_4_WEIGHT_0 … #define WEIGHT_LDS_SIG0(x) … #define WEIGHT_LDS_SIG0_MASK … #define WEIGHT_LDS_SIG0_SHIFT … #define WEIGHT_LDS_SIG1(x) … #define WEIGHT_LDS_SIG1_MASK … #define WEIGHT_LDS_SIG1_SHIFT … #define WEIGHT_SC(x) … #define WEIGHT_SC_MASK … #define WEIGHT_SC_SHIFT … #define CG_CAC_REGION_4_WEIGHT_1 … #define WEIGHT_BIF(x) … #define WEIGHT_BIF_MASK … #define WEIGHT_BIF_SHIFT … #define WEIGHT_CP(x) … #define WEIGHT_CP_MASK … #define WEIGHT_CP_SHIFT … #define WEIGHT_PA_SIG0(x) … #define WEIGHT_PA_SIG0_MASK … #define WEIGHT_PA_SIG0_SHIFT … #define WEIGHT_PA_SIG1(x) … #define WEIGHT_PA_SIG1_MASK … #define WEIGHT_PA_SIG1_SHIFT … #define WEIGHT_VGT_SIG0(x) … #define WEIGHT_VGT_SIG0_MASK … #define WEIGHT_VGT_SIG0_SHIFT … #define CG_CAC_REGION_4_WEIGHT_2 … #define WEIGHT_VGT_SIG1(x) … #define WEIGHT_VGT_SIG1_MASK … #define WEIGHT_VGT_SIG1_SHIFT … #define WEIGHT_VGT_SIG2(x) … #define WEIGHT_VGT_SIG2_MASK … #define WEIGHT_VGT_SIG2_SHIFT … #define WEIGHT_DC_SIG0(x) … #define WEIGHT_DC_SIG0_MASK … #define WEIGHT_DC_SIG0_SHIFT … #define WEIGHT_DC_SIG1(x) … #define WEIGHT_DC_SIG1_MASK … #define WEIGHT_DC_SIG1_SHIFT … #define WEIGHT_DC_SIG2(x) … #define WEIGHT_DC_SIG2_MASK … #define WEIGHT_DC_SIG2_SHIFT … #define CG_CAC_REGION_4_WEIGHT_3 … #define WEIGHT_DC_SIG3(x) … #define WEIGHT_DC_SIG3_MASK … #define WEIGHT_DC_SIG3_SHIFT … #define WEIGHT_UVD_SIG0(x) … #define WEIGHT_UVD_SIG0_MASK … #define WEIGHT_UVD_SIG0_SHIFT … #define WEIGHT_UVD_SIG1(x) … #define WEIGHT_UVD_SIG1_MASK … #define WEIGHT_UVD_SIG1_SHIFT … #define WEIGHT_SPARE0(x) … #define WEIGHT_SPARE0_MASK … #define WEIGHT_SPARE0_SHIFT … #define WEIGHT_SPARE1(x) … #define WEIGHT_SPARE1_MASK … #define WEIGHT_SPARE1_SHIFT … #define CG_CAC_REGION_5_WEIGHT_0 … #define WEIGHT_SQ_VSP(x) … #define WEIGHT_SQ_VSP_MASK … #define WEIGHT_SQ_VSP_SHIFT … #define WEIGHT_SQ_VSP0(x) … #define WEIGHT_SQ_VSP0_MASK … #define WEIGHT_SQ_VSP0_SHIFT … #define CG_CAC_REGION_4_OVERRIDE_4 … #define OVR_MODE_SPARE_0(x) … #define OVR_MODE_SPARE_0_MASK … #define OVR_MODE_SPARE_0_SHIFT … #define OVR_VAL_SPARE_0(x) … #define OVR_VAL_SPARE_0_MASK … #define OVR_VAL_SPARE_0_SHIFT … #define OVR_MODE_SPARE_1(x) … #define OVR_MODE_SPARE_1_MASK … #define OVR_MODE_SPARE_1_SHIFT … #define OVR_VAL_SPARE_1(x) … #define OVR_VAL_SPARE_1_MASK … #define OVR_VAL_SPARE_1_SHIFT … #define CG_CAC_REGION_5_WEIGHT_1 … #define WEIGHT_SQ_GPR(x) … #define WEIGHT_SQ_GPR_MASK … #define WEIGHT_SQ_GPR_SHIFT … #define WEIGHT_SQ_LDS(x) … #define WEIGHT_SQ_LDS_MASK … #define WEIGHT_SQ_LDS_SHIFT … /* PCIE link stuff */ #define PCIE_LC_TRAINING_CNTL … #define PCIE_LC_LINK_WIDTH_CNTL … #define LC_LINK_WIDTH_SHIFT … #define LC_LINK_WIDTH_MASK … #define LC_LINK_WIDTH_X0 … #define LC_LINK_WIDTH_X1 … #define LC_LINK_WIDTH_X2 … #define LC_LINK_WIDTH_X4 … #define LC_LINK_WIDTH_X8 … #define LC_LINK_WIDTH_X16 … #define LC_LINK_WIDTH_RD_SHIFT … #define LC_LINK_WIDTH_RD_MASK … #define LC_RECONFIG_ARC_MISSING_ESCAPE … #define LC_RECONFIG_NOW … #define LC_RENEGOTIATION_SUPPORT … #define LC_RENEGOTIATE_EN … #define LC_SHORT_RECONFIG_EN … #define LC_UPCONFIGURE_SUPPORT … #define LC_UPCONFIGURE_DIS … #define PCIE_LC_SPEED_CNTL … #define LC_GEN2_EN_STRAP … #define LC_TARGET_LINK_SPEED_OVERRIDE_EN … #define LC_FORCE_EN_HW_SPEED_CHANGE … #define LC_FORCE_DIS_HW_SPEED_CHANGE … #define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK … #define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT … #define LC_CURRENT_DATA_RATE … #define LC_HW_VOLTAGE_IF_CONTROL(x) … #define LC_HW_VOLTAGE_IF_CONTROL_MASK … #define LC_HW_VOLTAGE_IF_CONTROL_SHIFT … #define LC_VOLTAGE_TIMER_SEL_MASK … #define LC_CLR_FAILED_SPD_CHANGE_CNT … #define LC_OTHER_SIDE_EVER_SENT_GEN2 … #define LC_OTHER_SIDE_SUPPORTS_GEN2 … #define MM_CFGREGS_CNTL … #define MM_WR_TO_CFG_EN … #define LINK_CNTL2 … #define TARGET_LINK_SPEED_MASK … #define SELECTABLE_DEEMPHASIS … /* * UVD */ #define UVD_SEMA_ADDR_LOW … #define UVD_SEMA_ADDR_HIGH … #define UVD_SEMA_CMD … #define UVD_UDEC_ADDR_CONFIG … #define UVD_UDEC_DB_ADDR_CONFIG … #define UVD_UDEC_DBW_ADDR_CONFIG … #define UVD_NO_OP … #define UVD_RBC_RB_RPTR … #define UVD_RBC_RB_WPTR … #define UVD_STATUS … /* * PM4 */ #define PACKET0(reg, n) … #define CP_PACKET2 … #define PACKET2_PAD_SHIFT … #define PACKET2_PAD_MASK … #define PACKET2(v) … #define PACKET3(op, n) … /* Packet 3 types */ #define PACKET3_NOP … #define PACKET3_SET_BASE … #define PACKET3_CLEAR_STATE … #define PACKET3_INDEX_BUFFER_SIZE … #define PACKET3_DEALLOC_STATE … #define PACKET3_DISPATCH_DIRECT … #define PACKET3_DISPATCH_INDIRECT … #define PACKET3_INDIRECT_BUFFER_END … #define PACKET3_MODE_CONTROL … #define PACKET3_SET_PREDICATION … #define PACKET3_REG_RMW … #define PACKET3_COND_EXEC … #define PACKET3_PRED_EXEC … #define PACKET3_DRAW_INDIRECT … #define PACKET3_DRAW_INDEX_INDIRECT … #define PACKET3_INDEX_BASE … #define PACKET3_DRAW_INDEX_2 … #define PACKET3_CONTEXT_CONTROL … #define PACKET3_DRAW_INDEX_OFFSET … #define PACKET3_INDEX_TYPE … #define PACKET3_DRAW_INDEX … #define PACKET3_DRAW_INDEX_AUTO … #define PACKET3_DRAW_INDEX_IMMD … #define PACKET3_NUM_INSTANCES … #define PACKET3_DRAW_INDEX_MULTI_AUTO … #define PACKET3_INDIRECT_BUFFER … #define PACKET3_STRMOUT_BUFFER_UPDATE … #define PACKET3_DRAW_INDEX_OFFSET_2 … #define PACKET3_DRAW_INDEX_MULTI_ELEMENT … #define PACKET3_WRITE_DATA … #define PACKET3_MEM_SEMAPHORE … #define PACKET3_MPEG_INDEX … #define PACKET3_WAIT_REG_MEM … #define WAIT_REG_MEM_FUNCTION(x) … /* 0 - always * 1 - < * 2 - <= * 3 - == * 4 - != * 5 - >= * 6 - > */ #define WAIT_REG_MEM_MEM_SPACE(x) … /* 0 - reg * 1 - mem */ #define WAIT_REG_MEM_ENGINE(x) … /* 0 - me * 1 - pfp */ #define PACKET3_MEM_WRITE … #define PACKET3_PFP_SYNC_ME … #define PACKET3_SURFACE_SYNC … #define PACKET3_CB0_DEST_BASE_ENA … #define PACKET3_CB1_DEST_BASE_ENA … #define PACKET3_CB2_DEST_BASE_ENA … #define PACKET3_CB3_DEST_BASE_ENA … #define PACKET3_CB4_DEST_BASE_ENA … #define PACKET3_CB5_DEST_BASE_ENA … #define PACKET3_CB6_DEST_BASE_ENA … #define PACKET3_CB7_DEST_BASE_ENA … #define PACKET3_DB_DEST_BASE_ENA … #define PACKET3_CB8_DEST_BASE_ENA … #define PACKET3_CB9_DEST_BASE_ENA … #define PACKET3_CB10_DEST_BASE_ENA … #define PACKET3_CB11_DEST_BASE_ENA … #define PACKET3_FULL_CACHE_ENA … #define PACKET3_TC_ACTION_ENA … #define PACKET3_CB_ACTION_ENA … #define PACKET3_DB_ACTION_ENA … #define PACKET3_SH_ACTION_ENA … #define PACKET3_SX_ACTION_ENA … #define PACKET3_ENGINE_ME … #define PACKET3_ME_INITIALIZE … #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) … #define PACKET3_COND_WRITE … #define PACKET3_EVENT_WRITE … #define EVENT_TYPE(x) … #define EVENT_INDEX(x) … /* 0 - any non-TS event * 1 - ZPASS_DONE * 2 - SAMPLE_PIPELINESTAT * 3 - SAMPLE_STREAMOUTSTAT* * 4 - *S_PARTIAL_FLUSH * 5 - TS events */ #define PACKET3_EVENT_WRITE_EOP … #define DATA_SEL(x) … /* 0 - discard * 1 - send low 32bit data * 2 - send 64bit data * 3 - send 64bit counter value */ #define INT_SEL(x) … /* 0 - none * 1 - interrupt only (DATA_SEL = 0) * 2 - interrupt when data write is confirmed */ #define PACKET3_EVENT_WRITE_EOS … #define PACKET3_PREAMBLE_CNTL … #define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE … #define PACKET3_PREAMBLE_END_CLEAR_STATE … #define PACKET3_ALU_PS_CONST_BUFFER_COPY … #define PACKET3_ALU_VS_CONST_BUFFER_COPY … #define PACKET3_ALU_PS_CONST_UPDATE … #define PACKET3_ALU_VS_CONST_UPDATE … #define PACKET3_ONE_REG_WRITE … #define PACKET3_SET_CONFIG_REG … #define PACKET3_SET_CONFIG_REG_START … #define PACKET3_SET_CONFIG_REG_END … #define PACKET3_SET_CONTEXT_REG … #define PACKET3_SET_CONTEXT_REG_START … #define PACKET3_SET_CONTEXT_REG_END … #define PACKET3_SET_ALU_CONST … /* alu const buffers only; no reg file */ #define PACKET3_SET_BOOL_CONST … #define PACKET3_SET_BOOL_CONST_START … #define PACKET3_SET_BOOL_CONST_END … #define PACKET3_SET_LOOP_CONST … #define PACKET3_SET_LOOP_CONST_START … #define PACKET3_SET_LOOP_CONST_END … #define PACKET3_SET_RESOURCE … #define PACKET3_SET_RESOURCE_START … #define PACKET3_SET_RESOURCE_END … #define PACKET3_SET_SAMPLER … #define PACKET3_SET_SAMPLER_START … #define PACKET3_SET_SAMPLER_END … #define PACKET3_SET_CTL_CONST … #define PACKET3_SET_CTL_CONST_START … #define PACKET3_SET_CTL_CONST_END … #define PACKET3_SET_RESOURCE_OFFSET … #define PACKET3_SET_ALU_CONST_VS … #define PACKET3_SET_ALU_CONST_DI … #define PACKET3_SET_CONTEXT_REG_INDIRECT … #define PACKET3_SET_RESOURCE_INDIRECT … #define PACKET3_SET_APPEND_CNT … #define PACKET3_ME_WRITE … /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ #define DMA0_REGISTER_OFFSET … #define DMA1_REGISTER_OFFSET … #define DMA_RB_CNTL … #define DMA_RB_ENABLE … #define DMA_RB_SIZE(x) … #define DMA_RB_SWAP_ENABLE … #define DMA_RPTR_WRITEBACK_ENABLE … #define DMA_RPTR_WRITEBACK_SWAP_ENABLE … #define DMA_RPTR_WRITEBACK_TIMER(x) … #define DMA_RB_BASE … #define DMA_RB_RPTR … #define DMA_RB_WPTR … #define DMA_RB_RPTR_ADDR_HI … #define DMA_RB_RPTR_ADDR_LO … #define DMA_IB_CNTL … #define DMA_IB_ENABLE … #define DMA_IB_SWAP_ENABLE … #define CMD_VMID_FORCE … #define DMA_IB_RPTR … #define DMA_CNTL … #define TRAP_ENABLE … #define SEM_INCOMPLETE_INT_ENABLE … #define SEM_WAIT_INT_ENABLE … #define DATA_SWAP_ENABLE … #define FENCE_SWAP_ENABLE … #define CTXEMPTY_INT_ENABLE … #define DMA_STATUS_REG … #define DMA_IDLE … #define DMA_SEM_INCOMPLETE_TIMER_CNTL … #define DMA_SEM_WAIT_FAIL_TIMER_CNTL … #define DMA_TILING_CONFIG … #define DMA_MODE … #define DMA_PACKET(cmd, t, s, n) … #define DMA_IB_PACKET(cmd, vmid, n) … #define DMA_PTE_PDE_PACKET(n) … #define DMA_SRBM_POLL_PACKET … #define DMA_SRBM_READ_PACKET … /* async DMA Packet types */ #define DMA_PACKET_WRITE … #define DMA_PACKET_COPY … #define DMA_PACKET_INDIRECT_BUFFER … #define DMA_PACKET_SEMAPHORE … #define DMA_PACKET_FENCE … #define DMA_PACKET_TRAP … #define DMA_PACKET_SRBM_WRITE … #define DMA_PACKET_CONSTANT_FILL … #define DMA_PACKET_NOP … #endif
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