/* * Copyright 2012 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Alex Deucher */ #ifndef CIK_H #define CIK_H #define BONAIRE_GB_ADDR_CONFIG_GOLDEN … #define HAWAII_GB_ADDR_CONFIG_GOLDEN … #define CIK_RB_BITMAP_WIDTH_PER_SH … #define HAWAII_RB_BITMAP_WIDTH_PER_SH … /* DIDT IND registers */ #define DIDT_SQ_CTRL0 … #define DIDT_CTRL_EN … #define DIDT_DB_CTRL0 … #define DIDT_TD_CTRL0 … #define DIDT_TCP_CTRL0 … /* SMC IND registers */ #define DPM_TABLE_475 … #define SamuBootLevel(x) … #define SamuBootLevel_MASK … #define SamuBootLevel_SHIFT … #define AcpBootLevel(x) … #define AcpBootLevel_MASK … #define AcpBootLevel_SHIFT … #define VceBootLevel(x) … #define VceBootLevel_MASK … #define VceBootLevel_SHIFT … #define UvdBootLevel(x) … #define UvdBootLevel_MASK … #define UvdBootLevel_SHIFT … #define FIRMWARE_FLAGS … #define INTERRUPTS_ENABLED … #define NB_DPM_CONFIG_1 … #define Dpm0PgNbPsLo(x) … #define Dpm0PgNbPsLo_MASK … #define Dpm0PgNbPsLo_SHIFT … #define Dpm0PgNbPsHi(x) … #define Dpm0PgNbPsHi_MASK … #define Dpm0PgNbPsHi_SHIFT … #define DpmXNbPsLo(x) … #define DpmXNbPsLo_MASK … #define DpmXNbPsLo_SHIFT … #define DpmXNbPsHi(x) … #define DpmXNbPsHi_MASK … #define DpmXNbPsHi_SHIFT … #define SMC_SYSCON_RESET_CNTL … #define RST_REG … #define SMC_SYSCON_CLOCK_CNTL_0 … #define CK_DISABLE … #define CKEN … #define SMC_SYSCON_MISC_CNTL … #define SMC_SYSCON_MSG_ARG_0 … #define SMC_PC_C … #define SMC_SCRATCH9 … #define RCU_UC_EVENTS … #define BOOT_SEQ_DONE … #define GENERAL_PWRMGT … #define GLOBAL_PWRMGT_EN … #define STATIC_PM_EN … #define THERMAL_PROTECTION_DIS … #define THERMAL_PROTECTION_TYPE … #define SW_SMIO_INDEX(x) … #define SW_SMIO_INDEX_MASK … #define SW_SMIO_INDEX_SHIFT … #define VOLT_PWRMGT_EN … #define GPU_COUNTER_CLK … #define DYN_SPREAD_SPECTRUM_EN … #define CNB_PWRMGT_CNTL … #define GNB_SLOW_MODE(x) … #define GNB_SLOW_MODE_MASK … #define GNB_SLOW_MODE_SHIFT … #define GNB_SLOW … #define FORCE_NB_PS1 … #define DPM_ENABLED … #define SCLK_PWRMGT_CNTL … #define SCLK_PWRMGT_OFF … #define RESET_BUSY_CNT … #define RESET_SCLK_CNT … #define DYNAMIC_PM_EN … #define TARGET_AND_CURRENT_PROFILE_INDEX … #define CURRENT_STATE_MASK … #define CURRENT_STATE_SHIFT … #define CURR_MCLK_INDEX_MASK … #define CURR_MCLK_INDEX_SHIFT … #define CURR_SCLK_INDEX_MASK … #define CURR_SCLK_INDEX_SHIFT … #define CG_SSP … #define SST(x) … #define SST_MASK … #define SSTU(x) … #define SSTU_MASK … #define CG_DISPLAY_GAP_CNTL … #define DISP_GAP(x) … #define DISP_GAP_MASK … #define VBI_TIMER_COUNT(x) … #define VBI_TIMER_COUNT_MASK … #define VBI_TIMER_UNIT(x) … #define VBI_TIMER_UNIT_MASK … #define DISP_GAP_MCHG(x) … #define DISP_GAP_MCHG_MASK … #define SMU_VOLTAGE_STATUS … #define SMU_VOLTAGE_CURRENT_LEVEL_MASK … #define SMU_VOLTAGE_CURRENT_LEVEL_SHIFT … #define TARGET_AND_CURRENT_PROFILE_INDEX_1 … #define CURR_PCIE_INDEX_MASK … #define CURR_PCIE_INDEX_SHIFT … #define CG_ULV_PARAMETER … #define CG_FTV_0 … #define CG_FTV_1 … #define CG_FTV_2 … #define CG_FTV_3 … #define CG_FTV_4 … #define CG_FTV_5 … #define CG_FTV_6 … #define CG_FTV_7 … #define CG_DISPLAY_GAP_CNTL2 … #define LCAC_SX0_OVR_SEL … #define LCAC_SX0_OVR_VAL … #define LCAC_MC0_CNTL … #define LCAC_MC0_OVR_SEL … #define LCAC_MC0_OVR_VAL … #define LCAC_MC1_CNTL … #define LCAC_MC1_OVR_SEL … #define LCAC_MC1_OVR_VAL … #define LCAC_MC2_OVR_SEL … #define LCAC_MC2_OVR_VAL … #define LCAC_MC3_OVR_SEL … #define LCAC_MC3_OVR_VAL … #define LCAC_CPL_CNTL … #define LCAC_CPL_OVR_SEL … #define LCAC_CPL_OVR_VAL … /* dGPU */ #define CG_THERMAL_CTRL … #define DPM_EVENT_SRC(x) … #define DPM_EVENT_SRC_MASK … #define DIG_THERM_DPM(x) … #define DIG_THERM_DPM_MASK … #define DIG_THERM_DPM_SHIFT … #define CG_THERMAL_STATUS … #define FDO_PWM_DUTY(x) … #define FDO_PWM_DUTY_MASK … #define FDO_PWM_DUTY_SHIFT … #define CG_THERMAL_INT … #define CI_DIG_THERM_INTH(x) … #define CI_DIG_THERM_INTH_MASK … #define CI_DIG_THERM_INTH_SHIFT … #define CI_DIG_THERM_INTL(x) … #define CI_DIG_THERM_INTL_MASK … #define CI_DIG_THERM_INTL_SHIFT … #define THERM_INT_MASK_HIGH … #define THERM_INT_MASK_LOW … #define CG_MULT_THERMAL_CTRL … #define TEMP_SEL(x) … #define TEMP_SEL_MASK … #define TEMP_SEL_SHIFT … #define CG_MULT_THERMAL_STATUS … #define ASIC_MAX_TEMP(x) … #define ASIC_MAX_TEMP_MASK … #define ASIC_MAX_TEMP_SHIFT … #define CTF_TEMP(x) … #define CTF_TEMP_MASK … #define CTF_TEMP_SHIFT … #define CG_FDO_CTRL0 … #define FDO_STATIC_DUTY(x) … #define FDO_STATIC_DUTY_MASK … #define FDO_STATIC_DUTY_SHIFT … #define CG_FDO_CTRL1 … #define FMAX_DUTY100(x) … #define FMAX_DUTY100_MASK … #define FMAX_DUTY100_SHIFT … #define CG_FDO_CTRL2 … #define TMIN(x) … #define TMIN_MASK … #define TMIN_SHIFT … #define FDO_PWM_MODE(x) … #define FDO_PWM_MODE_MASK … #define FDO_PWM_MODE_SHIFT … #define TACH_PWM_RESP_RATE(x) … #define TACH_PWM_RESP_RATE_MASK … #define TACH_PWM_RESP_RATE_SHIFT … #define CG_TACH_CTRL … #define EDGE_PER_REV(x) … #define EDGE_PER_REV_MASK … #define EDGE_PER_REV_SHIFT … #define TARGET_PERIOD(x) … #define TARGET_PERIOD_MASK … #define TARGET_PERIOD_SHIFT … #define CG_TACH_STATUS … #define TACH_PERIOD(x) … #define TACH_PERIOD_MASK … #define TACH_PERIOD_SHIFT … #define CG_ECLK_CNTL … #define ECLK_DIVIDER_MASK … #define ECLK_DIR_CNTL_EN … #define CG_ECLK_STATUS … #define ECLK_STATUS … #define CG_SPLL_FUNC_CNTL … #define SPLL_RESET … #define SPLL_PWRON … #define SPLL_BYPASS_EN … #define SPLL_REF_DIV(x) … #define SPLL_REF_DIV_MASK … #define SPLL_PDIV_A(x) … #define SPLL_PDIV_A_MASK … #define SPLL_PDIV_A_SHIFT … #define CG_SPLL_FUNC_CNTL_2 … #define SCLK_MUX_SEL(x) … #define SCLK_MUX_SEL_MASK … #define CG_SPLL_FUNC_CNTL_3 … #define SPLL_FB_DIV(x) … #define SPLL_FB_DIV_MASK … #define SPLL_FB_DIV_SHIFT … #define SPLL_DITHEN … #define CG_SPLL_FUNC_CNTL_4 … #define CG_SPLL_SPREAD_SPECTRUM … #define SSEN … #define CLK_S(x) … #define CLK_S_MASK … #define CLK_S_SHIFT … #define CG_SPLL_SPREAD_SPECTRUM_2 … #define CLK_V(x) … #define CLK_V_MASK … #define CLK_V_SHIFT … #define MPLL_BYPASSCLK_SEL … #define MPLL_CLKOUT_SEL(x) … #define MPLL_CLKOUT_SEL_MASK … #define CG_CLKPIN_CNTL … #define XTALIN_DIVIDE … #define BCLK_AS_XCLK … #define CG_CLKPIN_CNTL_2 … #define FORCE_BIF_REFCLK_EN … #define MUX_TCLK_TO_XCLK … #define THM_CLK_CNTL … #define CMON_CLK_SEL(x) … #define CMON_CLK_SEL_MASK … #define TMON_CLK_SEL(x) … #define TMON_CLK_SEL_MASK … #define MISC_CLK_CTRL … #define DEEP_SLEEP_CLK_SEL(x) … #define DEEP_SLEEP_CLK_SEL_MASK … #define ZCLK_SEL(x) … #define ZCLK_SEL_MASK … /* KV/KB */ #define CG_THERMAL_INT_CTRL … #define DIG_THERM_INTH(x) … #define DIG_THERM_INTH_MASK … #define DIG_THERM_INTH_SHIFT … #define DIG_THERM_INTL(x) … #define DIG_THERM_INTL_MASK … #define DIG_THERM_INTL_SHIFT … #define THERM_INTH_MASK … #define THERM_INTL_MASK … /* PCIE registers idx/data 0x38/0x3c */ #define PB0_PIF_PWRDOWN_0 … #define PLL_POWER_STATE_IN_TXS2_0(x) … #define PLL_POWER_STATE_IN_TXS2_0_MASK … #define PLL_POWER_STATE_IN_TXS2_0_SHIFT … #define PLL_POWER_STATE_IN_OFF_0(x) … #define PLL_POWER_STATE_IN_OFF_0_MASK … #define PLL_POWER_STATE_IN_OFF_0_SHIFT … #define PLL_RAMP_UP_TIME_0(x) … #define PLL_RAMP_UP_TIME_0_MASK … #define PLL_RAMP_UP_TIME_0_SHIFT … #define PB0_PIF_PWRDOWN_1 … #define PLL_POWER_STATE_IN_TXS2_1(x) … #define PLL_POWER_STATE_IN_TXS2_1_MASK … #define PLL_POWER_STATE_IN_TXS2_1_SHIFT … #define PLL_POWER_STATE_IN_OFF_1(x) … #define PLL_POWER_STATE_IN_OFF_1_MASK … #define PLL_POWER_STATE_IN_OFF_1_SHIFT … #define PLL_RAMP_UP_TIME_1(x) … #define PLL_RAMP_UP_TIME_1_MASK … #define PLL_RAMP_UP_TIME_1_SHIFT … #define PCIE_CNTL2 … #define SLV_MEM_LS_EN … #define SLV_MEM_AGGRESSIVE_LS_EN … #define MST_MEM_LS_EN … #define REPLAY_MEM_LS_EN … #define PCIE_LC_STATUS1 … #define LC_REVERSE_RCVR … #define LC_REVERSE_XMIT … #define LC_OPERATING_LINK_WIDTH_MASK … #define LC_OPERATING_LINK_WIDTH_SHIFT … #define LC_DETECTED_LINK_WIDTH_MASK … #define LC_DETECTED_LINK_WIDTH_SHIFT … #define PCIE_P_CNTL … #define P_IGNORE_EDB_ERR … #define PB1_PIF_PWRDOWN_0 … #define PB1_PIF_PWRDOWN_1 … #define PCIE_LC_CNTL … #define LC_L0S_INACTIVITY(x) … #define LC_L0S_INACTIVITY_MASK … #define LC_L0S_INACTIVITY_SHIFT … #define LC_L1_INACTIVITY(x) … #define LC_L1_INACTIVITY_MASK … #define LC_L1_INACTIVITY_SHIFT … #define LC_PMI_TO_L1_DIS … #define LC_ASPM_TO_L1_DIS … #define PCIE_LC_LINK_WIDTH_CNTL … #define LC_LINK_WIDTH_SHIFT … #define LC_LINK_WIDTH_MASK … #define LC_LINK_WIDTH_X0 … #define LC_LINK_WIDTH_X1 … #define LC_LINK_WIDTH_X2 … #define LC_LINK_WIDTH_X4 … #define LC_LINK_WIDTH_X8 … #define LC_LINK_WIDTH_X16 … #define LC_LINK_WIDTH_RD_SHIFT … #define LC_LINK_WIDTH_RD_MASK … #define LC_RECONFIG_ARC_MISSING_ESCAPE … #define LC_RECONFIG_NOW … #define LC_RENEGOTIATION_SUPPORT … #define LC_RENEGOTIATE_EN … #define LC_SHORT_RECONFIG_EN … #define LC_UPCONFIGURE_SUPPORT … #define LC_UPCONFIGURE_DIS … #define LC_DYN_LANES_PWR_STATE(x) … #define LC_DYN_LANES_PWR_STATE_MASK … #define LC_DYN_LANES_PWR_STATE_SHIFT … #define PCIE_LC_N_FTS_CNTL … #define LC_XMIT_N_FTS(x) … #define LC_XMIT_N_FTS_MASK … #define LC_XMIT_N_FTS_SHIFT … #define LC_XMIT_N_FTS_OVERRIDE_EN … #define LC_N_FTS_MASK … #define PCIE_LC_SPEED_CNTL … #define LC_GEN2_EN_STRAP … #define LC_GEN3_EN_STRAP … #define LC_TARGET_LINK_SPEED_OVERRIDE_EN … #define LC_TARGET_LINK_SPEED_OVERRIDE_MASK … #define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT … #define LC_FORCE_EN_SW_SPEED_CHANGE … #define LC_FORCE_DIS_SW_SPEED_CHANGE … #define LC_FORCE_EN_HW_SPEED_CHANGE … #define LC_FORCE_DIS_HW_SPEED_CHANGE … #define LC_INITIATE_LINK_SPEED_CHANGE … #define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK … #define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT … #define LC_CURRENT_DATA_RATE_MASK … #define LC_CURRENT_DATA_RATE_SHIFT … #define LC_CLR_FAILED_SPD_CHANGE_CNT … #define LC_OTHER_SIDE_EVER_SENT_GEN2 … #define LC_OTHER_SIDE_SUPPORTS_GEN2 … #define LC_OTHER_SIDE_EVER_SENT_GEN3 … #define LC_OTHER_SIDE_SUPPORTS_GEN3 … #define PCIE_LC_CNTL2 … #define LC_ALLOW_PDWN_IN_L1 … #define LC_ALLOW_PDWN_IN_L23 … #define PCIE_LC_CNTL3 … #define LC_GO_TO_RECOVERY … #define PCIE_LC_CNTL4 … #define LC_REDO_EQ … #define LC_SET_QUIESCE … /* direct registers */ #define PCIE_INDEX … #define PCIE_DATA … #define SMC_IND_INDEX_0 … #define SMC_IND_DATA_0 … #define SMC_IND_ACCESS_CNTL … #define AUTO_INCREMENT_IND_0 … #define SMC_MESSAGE_0 … #define SMC_MSG_MASK … #define SMC_RESP_0 … #define SMC_RESP_MASK … #define SMC_MSG_ARG_0 … #define VGA_HDP_CONTROL … #define VGA_MEMORY_DISABLE … #define DMIF_ADDR_CALC … #define PIPE0_DMIF_BUFFER_CONTROL … #define DMIF_BUFFERS_ALLOCATED(x) … #define DMIF_BUFFERS_ALLOCATED_COMPLETED … #define SRBM_GFX_CNTL … #define PIPEID(x) … #define MEID(x) … #define VMID(x) … #define QUEUEID(x) … #define SRBM_STATUS2 … #define SDMA_BUSY … #define SDMA1_BUSY … #define SRBM_STATUS … #define UVD_RQ_PENDING … #define GRBM_RQ_PENDING … #define VMC_BUSY … #define MCB_BUSY … #define MCB_NON_DISPLAY_BUSY … #define MCC_BUSY … #define MCD_BUSY … #define SEM_BUSY … #define IH_BUSY … #define UVD_BUSY … #define SRBM_SOFT_RESET … #define SOFT_RESET_BIF … #define SOFT_RESET_R0PLL … #define SOFT_RESET_DC … #define SOFT_RESET_SDMA1 … #define SOFT_RESET_GRBM … #define SOFT_RESET_HDP … #define SOFT_RESET_IH … #define SOFT_RESET_MC … #define SOFT_RESET_ROM … #define SOFT_RESET_SEM … #define SOFT_RESET_VMC … #define SOFT_RESET_SDMA … #define SOFT_RESET_TST … #define SOFT_RESET_REGBB … #define SOFT_RESET_ORB … #define SOFT_RESET_VCE … #define SRBM_READ_ERROR … #define SRBM_INT_CNTL … #define SRBM_INT_ACK … #define VM_L2_CNTL … #define ENABLE_L2_CACHE … #define ENABLE_L2_FRAGMENT_PROCESSING … #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) … #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) … #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE … #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE … #define EFFECTIVE_L2_QUEUE_SIZE(x) … #define CONTEXT1_IDENTITY_ACCESS_MODE(x) … #define VM_L2_CNTL2 … #define INVALIDATE_ALL_L1_TLBS … #define INVALIDATE_L2_CACHE … #define INVALIDATE_CACHE_MODE(x) … #define INVALIDATE_PTE_AND_PDE_CACHES … #define INVALIDATE_ONLY_PTE_CACHES … #define INVALIDATE_ONLY_PDE_CACHES … #define VM_L2_CNTL3 … #define BANK_SELECT(x) … #define L2_CACHE_UPDATE_MODE(x) … #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) … #define L2_CACHE_BIGK_ASSOCIATIVITY … #define VM_L2_STATUS … #define L2_BUSY … #define VM_CONTEXT0_CNTL … #define ENABLE_CONTEXT … #define PAGE_TABLE_DEPTH(x) … #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT … #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT … #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT … #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT … #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT … #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT … #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT … #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT … #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT … #define READ_PROTECTION_FAULT_ENABLE_DEFAULT … #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT … #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT … #define PAGE_TABLE_BLOCK_SIZE(x) … #define VM_CONTEXT1_CNTL … #define VM_CONTEXT0_CNTL2 … #define VM_CONTEXT1_CNTL2 … #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR … #define VM_INVALIDATE_REQUEST … #define VM_INVALIDATE_RESPONSE … #define VM_CONTEXT1_PROTECTION_FAULT_STATUS … #define PROTECTIONS_MASK … #define PROTECTIONS_SHIFT … /* bit 0: range * bit 1: pde0 * bit 2: valid * bit 3: read * bit 4: write */ #define MEMORY_CLIENT_ID_MASK … #define HAWAII_MEMORY_CLIENT_ID_MASK … #define MEMORY_CLIENT_ID_SHIFT … #define MEMORY_CLIENT_RW_MASK … #define MEMORY_CLIENT_RW_SHIFT … #define FAULT_VMID_MASK … #define FAULT_VMID_SHIFT … #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT … #define VM_CONTEXT1_PROTECTION_FAULT_ADDR … #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR … #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR … #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR … #define VM_CONTEXT0_PAGE_TABLE_START_ADDR … #define VM_CONTEXT1_PAGE_TABLE_START_ADDR … #define VM_CONTEXT0_PAGE_TABLE_END_ADDR … #define VM_CONTEXT1_PAGE_TABLE_END_ADDR … #define VM_L2_CG … #define MC_CG_ENABLE … #define MC_LS_ENABLE … #define MC_SHARED_CHMAP … #define NOOFCHAN_SHIFT … #define NOOFCHAN_MASK … #define MC_SHARED_CHREMAP … #define CHUB_CONTROL … #define BYPASS_VM … #define MC_VM_FB_LOCATION … #define MC_VM_AGP_TOP … #define MC_VM_AGP_BOT … #define MC_VM_AGP_BASE … #define MC_VM_SYSTEM_APERTURE_LOW_ADDR … #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR … #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR … #define MC_VM_MX_L1_TLB_CNTL … #define ENABLE_L1_TLB … #define ENABLE_L1_FRAGMENT_PROCESSING … #define SYSTEM_ACCESS_MODE_PA_ONLY … #define SYSTEM_ACCESS_MODE_USE_SYS_MAP … #define SYSTEM_ACCESS_MODE_IN_SYS … #define SYSTEM_ACCESS_MODE_NOT_IN_SYS … #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU … #define ENABLE_ADVANCED_DRIVER_MODEL … #define MC_VM_FB_OFFSET … #define MC_SHARED_BLACKOUT_CNTL … #define MC_HUB_MISC_HUB_CG … #define MC_HUB_MISC_VM_CG … #define MC_HUB_MISC_SIP_CG … #define MC_XPB_CLK_GAT … #define MC_CITF_MISC_RD_CG … #define MC_CITF_MISC_WR_CG … #define MC_CITF_MISC_VM_CG … #define MC_ARB_RAMCFG … #define NOOFBANK_SHIFT … #define NOOFBANK_MASK … #define NOOFRANK_SHIFT … #define NOOFRANK_MASK … #define NOOFROWS_SHIFT … #define NOOFROWS_MASK … #define NOOFCOLS_SHIFT … #define NOOFCOLS_MASK … #define CHANSIZE_SHIFT … #define CHANSIZE_MASK … #define NOOFGROUPS_SHIFT … #define NOOFGROUPS_MASK … #define MC_ARB_DRAM_TIMING … #define MC_ARB_DRAM_TIMING2 … #define MC_ARB_BURST_TIME … #define STATE0(x) … #define STATE0_MASK … #define STATE0_SHIFT … #define STATE1(x) … #define STATE1_MASK … #define STATE1_SHIFT … #define STATE2(x) … #define STATE2_MASK … #define STATE2_SHIFT … #define STATE3(x) … #define STATE3_MASK … #define STATE3_SHIFT … #define MC_SEQ_RAS_TIMING … #define MC_SEQ_CAS_TIMING … #define MC_SEQ_MISC_TIMING … #define MC_SEQ_MISC_TIMING2 … #define MC_SEQ_PMG_TIMING … #define MC_SEQ_RD_CTL_D0 … #define MC_SEQ_RD_CTL_D1 … #define MC_SEQ_WR_CTL_D0 … #define MC_SEQ_WR_CTL_D1 … #define MC_SEQ_SUP_CNTL … #define RUN_MASK … #define MC_SEQ_SUP_PGM … #define MC_PMG_AUTO_CMD … #define MC_SEQ_TRAIN_WAKEUP_CNTL … #define TRAIN_DONE_D0 … #define TRAIN_DONE_D1 … #define MC_IO_PAD_CNTL_D0 … #define MEM_FALL_OUT_CMD … #define MC_SEQ_MISC0 … #define MC_SEQ_MISC0_VEN_ID_SHIFT … #define MC_SEQ_MISC0_VEN_ID_MASK … #define MC_SEQ_MISC0_VEN_ID_VALUE … #define MC_SEQ_MISC0_REV_ID_SHIFT … #define MC_SEQ_MISC0_REV_ID_MASK … #define MC_SEQ_MISC0_REV_ID_VALUE … #define MC_SEQ_MISC0_GDDR5_SHIFT … #define MC_SEQ_MISC0_GDDR5_MASK … #define MC_SEQ_MISC0_GDDR5_VALUE … #define MC_SEQ_MISC1 … #define MC_SEQ_RESERVE_M … #define MC_PMG_CMD_EMRS … #define MC_SEQ_IO_DEBUG_INDEX … #define MC_SEQ_IO_DEBUG_DATA … #define MC_SEQ_MISC5 … #define MC_SEQ_MISC6 … #define MC_SEQ_MISC7 … #define MC_SEQ_RAS_TIMING_LP … #define MC_SEQ_CAS_TIMING_LP … #define MC_SEQ_MISC_TIMING_LP … #define MC_SEQ_MISC_TIMING2_LP … #define MC_SEQ_WR_CTL_D0_LP … #define MC_SEQ_WR_CTL_D1_LP … #define MC_SEQ_PMG_CMD_EMRS_LP … #define MC_SEQ_PMG_CMD_MRS_LP … #define MC_PMG_CMD_MRS … #define MC_SEQ_RD_CTL_D0_LP … #define MC_SEQ_RD_CTL_D1_LP … #define MC_PMG_CMD_MRS1 … #define MC_SEQ_PMG_CMD_MRS1_LP … #define MC_SEQ_PMG_TIMING_LP … #define MC_SEQ_WR_CTL_2 … #define MC_SEQ_WR_CTL_2_LP … #define MC_PMG_CMD_MRS2 … #define MC_SEQ_PMG_CMD_MRS2_LP … #define MCLK_PWRMGT_CNTL … #define DLL_SPEED(x) … #define DLL_SPEED_MASK … #define DLL_READY … #define MC_INT_CNTL … #define MRDCK0_PDNB … #define MRDCK1_PDNB … #define MRDCK0_RESET … #define MRDCK1_RESET … #define DLL_READY_READ … #define DLL_CNTL … #define MRDCK0_BYPASS … #define MRDCK1_BYPASS … #define MPLL_FUNC_CNTL … #define BWCTRL(x) … #define BWCTRL_MASK … #define MPLL_FUNC_CNTL_1 … #define VCO_MODE(x) … #define VCO_MODE_MASK … #define CLKFRAC(x) … #define CLKFRAC_MASK … #define CLKF(x) … #define CLKF_MASK … #define MPLL_FUNC_CNTL_2 … #define MPLL_AD_FUNC_CNTL … #define YCLK_POST_DIV(x) … #define YCLK_POST_DIV_MASK … #define MPLL_DQ_FUNC_CNTL … #define YCLK_SEL(x) … #define YCLK_SEL_MASK … #define MPLL_SS1 … #define CLKV(x) … #define CLKV_MASK … #define MPLL_SS2 … #define CLKS(x) … #define CLKS_MASK … #define HDP_HOST_PATH_CNTL … #define CLOCK_GATING_DIS … #define HDP_NONSURFACE_BASE … #define HDP_NONSURFACE_INFO … #define HDP_NONSURFACE_SIZE … #define HDP_ADDR_CONFIG … #define HDP_MISC_CNTL … #define HDP_FLUSH_INVALIDATE_CACHE … #define HDP_MEM_POWER_LS … #define HDP_LS_ENABLE … #define ATC_MISC_CG … #define GMCON_RENG_EXECUTE … #define RENG_EXECUTE_ON_PWR_UP … #define GMCON_MISC … #define RENG_EXECUTE_ON_REG_UPDATE … #define STCTRL_STUTTER_EN … #define GMCON_PGFSM_CONFIG … #define GMCON_PGFSM_WRITE … #define GMCON_PGFSM_READ … #define GMCON_MISC3 … #define MC_SEQ_CNTL_3 … #define CAC_EN … #define MC_SEQ_G5PDX_CTRL … #define MC_SEQ_G5PDX_CTRL_LP … #define MC_SEQ_G5PDX_CMD0 … #define MC_SEQ_G5PDX_CMD0_LP … #define MC_SEQ_G5PDX_CMD1 … #define MC_SEQ_G5PDX_CMD1_LP … #define MC_SEQ_PMG_DVS_CTL … #define MC_SEQ_PMG_DVS_CTL_LP … #define MC_SEQ_PMG_DVS_CMD … #define MC_SEQ_PMG_DVS_CMD_LP … #define MC_SEQ_DLL_STBY … #define MC_SEQ_DLL_STBY_LP … #define IH_RB_CNTL … #define IH_RB_ENABLE … #define IH_RB_SIZE(x) … #define IH_RB_FULL_DRAIN_ENABLE … #define IH_WPTR_WRITEBACK_ENABLE … #define IH_WPTR_WRITEBACK_TIMER(x) … #define IH_WPTR_OVERFLOW_ENABLE … #define IH_WPTR_OVERFLOW_CLEAR … #define IH_RB_BASE … #define IH_RB_RPTR … #define IH_RB_WPTR … #define RB_OVERFLOW … #define WPTR_OFFSET_MASK … #define IH_RB_WPTR_ADDR_HI … #define IH_RB_WPTR_ADDR_LO … #define IH_CNTL … #define ENABLE_INTR … #define IH_MC_SWAP(x) … #define IH_MC_SWAP_NONE … #define IH_MC_SWAP_16BIT … #define IH_MC_SWAP_32BIT … #define IH_MC_SWAP_64BIT … #define RPTR_REARM … #define MC_WRREQ_CREDIT(x) … #define MC_WR_CLEAN_CNT(x) … #define MC_VMID(x) … #define BIF_LNCNT_RESET … #define RESET_LNCNT_EN … #define CONFIG_MEMSIZE … #define INTERRUPT_CNTL … #define IH_DUMMY_RD_OVERRIDE … #define IH_DUMMY_RD_EN … #define IH_REQ_NONSNOOP_EN … #define GEN_IH_INT_EN … #define INTERRUPT_CNTL2 … #define HDP_MEM_COHERENCY_FLUSH_CNTL … #define BIF_FB_EN … #define FB_READ_EN … #define FB_WRITE_EN … #define HDP_REG_COHERENCY_FLUSH_CNTL … #define GPU_HDP_FLUSH_REQ … #define GPU_HDP_FLUSH_DONE … #define CP0 … #define CP1 … #define CP2 … #define CP3 … #define CP4 … #define CP5 … #define CP6 … #define CP7 … #define CP8 … #define CP9 … #define SDMA0 … #define SDMA1 … /* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */ #define LB_MEMORY_CTRL … #define LB_MEMORY_SIZE(x) … #define LB_MEMORY_CONFIG(x) … #define DPG_WATERMARK_MASK_CONTROL … #define LATENCY_WATERMARK_MASK(x) … #define DPG_PIPE_LATENCY_CONTROL … #define LATENCY_LOW_WATERMARK(x) … #define LATENCY_HIGH_WATERMARK(x) … /* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */ #define LB_VLINE_STATUS … #define VLINE_OCCURRED … #define VLINE_ACK … #define VLINE_STAT … #define VLINE_INTERRUPT … #define VLINE_INTERRUPT_TYPE … /* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */ #define LB_VBLANK_STATUS … #define VBLANK_OCCURRED … #define VBLANK_ACK … #define VBLANK_STAT … #define VBLANK_INTERRUPT … #define VBLANK_INTERRUPT_TYPE … /* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */ #define LB_INTERRUPT_MASK … #define VBLANK_INTERRUPT_MASK … #define VLINE_INTERRUPT_MASK … #define VLINE2_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS … #define LB_D1_VLINE_INTERRUPT … #define LB_D1_VBLANK_INTERRUPT … #define DC_HPD1_INTERRUPT … #define DC_HPD1_RX_INTERRUPT … #define DACA_AUTODETECT_INTERRUPT … #define DACB_AUTODETECT_INTERRUPT … #define DC_I2C_SW_DONE_INTERRUPT … #define DC_I2C_HW_DONE_INTERRUPT … #define DISP_INTERRUPT_STATUS_CONTINUE … #define LB_D2_VLINE_INTERRUPT … #define LB_D2_VBLANK_INTERRUPT … #define DC_HPD2_INTERRUPT … #define DC_HPD2_RX_INTERRUPT … #define DISP_TIMER_INTERRUPT … #define DISP_INTERRUPT_STATUS_CONTINUE2 … #define LB_D3_VLINE_INTERRUPT … #define LB_D3_VBLANK_INTERRUPT … #define DC_HPD3_INTERRUPT … #define DC_HPD3_RX_INTERRUPT … #define DISP_INTERRUPT_STATUS_CONTINUE3 … #define LB_D4_VLINE_INTERRUPT … #define LB_D4_VBLANK_INTERRUPT … #define DC_HPD4_INTERRUPT … #define DC_HPD4_RX_INTERRUPT … #define DISP_INTERRUPT_STATUS_CONTINUE4 … #define LB_D5_VLINE_INTERRUPT … #define LB_D5_VBLANK_INTERRUPT … #define DC_HPD5_INTERRUPT … #define DC_HPD5_RX_INTERRUPT … #define DISP_INTERRUPT_STATUS_CONTINUE5 … #define LB_D6_VLINE_INTERRUPT … #define LB_D6_VBLANK_INTERRUPT … #define DC_HPD6_INTERRUPT … #define DC_HPD6_RX_INTERRUPT … #define DISP_INTERRUPT_STATUS_CONTINUE6 … /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ #define GRPH_INT_STATUS … #define GRPH_PFLIP_INT_OCCURRED … #define GRPH_PFLIP_INT_CLEAR … /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ #define GRPH_INT_CONTROL … #define GRPH_PFLIP_INT_MASK … #define GRPH_PFLIP_INT_TYPE … #define DAC_AUTODETECT_INT_CONTROL … #define DC_HPD1_INT_STATUS … #define DC_HPD2_INT_STATUS … #define DC_HPD3_INT_STATUS … #define DC_HPD4_INT_STATUS … #define DC_HPD5_INT_STATUS … #define DC_HPD6_INT_STATUS … #define DC_HPDx_INT_STATUS … #define DC_HPDx_SENSE … #define DC_HPDx_SENSE_DELAYED … #define DC_HPDx_RX_INT_STATUS … #define DC_HPD1_INT_CONTROL … #define DC_HPD2_INT_CONTROL … #define DC_HPD3_INT_CONTROL … #define DC_HPD4_INT_CONTROL … #define DC_HPD5_INT_CONTROL … #define DC_HPD6_INT_CONTROL … #define DC_HPDx_INT_ACK … #define DC_HPDx_INT_POLARITY … #define DC_HPDx_INT_EN … #define DC_HPDx_RX_INT_ACK … #define DC_HPDx_RX_INT_EN … #define DC_HPD1_CONTROL … #define DC_HPD2_CONTROL … #define DC_HPD3_CONTROL … #define DC_HPD4_CONTROL … #define DC_HPD5_CONTROL … #define DC_HPD6_CONTROL … #define DC_HPDx_CONNECTION_TIMER(x) … #define DC_HPDx_RX_INT_TIMER(x) … #define DC_HPDx_EN … #define DPG_PIPE_STUTTER_CONTROL … #define STUTTER_ENABLE … /* DCE8 FMT blocks */ #define FMT_DYNAMIC_EXP_CNTL … #define FMT_DYNAMIC_EXP_EN … #define FMT_DYNAMIC_EXP_MODE … /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */ #define FMT_CONTROL … #define FMT_PIXEL_ENCODING … /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */ #define FMT_BIT_DEPTH_CONTROL … #define FMT_TRUNCATE_EN … #define FMT_TRUNCATE_MODE … #define FMT_TRUNCATE_DEPTH(x) … #define FMT_SPATIAL_DITHER_EN … #define FMT_SPATIAL_DITHER_MODE(x) … #define FMT_SPATIAL_DITHER_DEPTH(x) … #define FMT_FRAME_RANDOM_ENABLE … #define FMT_RGB_RANDOM_ENABLE … #define FMT_HIGHPASS_RANDOM_ENABLE … #define FMT_TEMPORAL_DITHER_EN … #define FMT_TEMPORAL_DITHER_DEPTH(x) … #define FMT_TEMPORAL_DITHER_OFFSET(x) … #define FMT_TEMPORAL_LEVEL … #define FMT_TEMPORAL_DITHER_RESET … #define FMT_25FRC_SEL(x) … #define FMT_50FRC_SEL(x) … #define FMT_75FRC_SEL(x) … #define FMT_CLAMP_CONTROL … #define FMT_CLAMP_DATA_EN … #define FMT_CLAMP_COLOR_FORMAT(x) … #define FMT_CLAMP_6BPC … #define FMT_CLAMP_8BPC … #define FMT_CLAMP_10BPC … #define GRBM_CNTL … #define GRBM_READ_TIMEOUT(x) … #define GRBM_STATUS2 … #define ME0PIPE1_CMDFIFO_AVAIL_MASK … #define ME0PIPE1_CF_RQ_PENDING … #define ME0PIPE1_PF_RQ_PENDING … #define ME1PIPE0_RQ_PENDING … #define ME1PIPE1_RQ_PENDING … #define ME1PIPE2_RQ_PENDING … #define ME1PIPE3_RQ_PENDING … #define ME2PIPE0_RQ_PENDING … #define ME2PIPE1_RQ_PENDING … #define ME2PIPE2_RQ_PENDING … #define ME2PIPE3_RQ_PENDING … #define RLC_RQ_PENDING … #define RLC_BUSY … #define TC_BUSY … #define CPF_BUSY … #define CPC_BUSY … #define CPG_BUSY … #define GRBM_STATUS … #define ME0PIPE0_CMDFIFO_AVAIL_MASK … #define SRBM_RQ_PENDING … #define ME0PIPE0_CF_RQ_PENDING … #define ME0PIPE0_PF_RQ_PENDING … #define GDS_DMA_RQ_PENDING … #define DB_CLEAN … #define CB_CLEAN … #define TA_BUSY … #define GDS_BUSY … #define WD_BUSY_NO_DMA … #define VGT_BUSY … #define IA_BUSY_NO_DMA … #define IA_BUSY … #define SX_BUSY … #define WD_BUSY … #define SPI_BUSY … #define BCI_BUSY … #define SC_BUSY … #define PA_BUSY … #define DB_BUSY … #define CP_COHERENCY_BUSY … #define CP_BUSY … #define CB_BUSY … #define GUI_ACTIVE … #define GRBM_STATUS_SE0 … #define GRBM_STATUS_SE1 … #define GRBM_STATUS_SE2 … #define GRBM_STATUS_SE3 … #define SE_DB_CLEAN … #define SE_CB_CLEAN … #define SE_BCI_BUSY … #define SE_VGT_BUSY … #define SE_PA_BUSY … #define SE_TA_BUSY … #define SE_SX_BUSY … #define SE_SPI_BUSY … #define SE_SC_BUSY … #define SE_DB_BUSY … #define SE_CB_BUSY … #define GRBM_SOFT_RESET … #define SOFT_RESET_CP … #define SOFT_RESET_RLC … #define SOFT_RESET_GFX … #define SOFT_RESET_CPF … #define SOFT_RESET_CPC … #define SOFT_RESET_CPG … #define GRBM_INT_CNTL … #define RDERR_INT_ENABLE … #define GUI_IDLE_INT_ENABLE … #define CP_CPC_STATUS … #define CP_CPC_BUSY_STAT … #define CP_CPC_STALLED_STAT1 … #define CP_CPF_STATUS … #define CP_CPF_BUSY_STAT … #define CP_CPF_STALLED_STAT1 … #define CP_MEC_CNTL … #define MEC_ME2_HALT … #define MEC_ME1_HALT … #define CP_MEC_CNTL … #define MEC_ME2_HALT … #define MEC_ME1_HALT … #define CP_STALLED_STAT3 … #define CP_STALLED_STAT1 … #define CP_STALLED_STAT2 … #define CP_STAT … #define CP_ME_CNTL … #define CP_CE_HALT … #define CP_PFP_HALT … #define CP_ME_HALT … #define CP_RB0_RPTR … #define CP_RB_WPTR_DELAY … #define CP_RB_WPTR_POLL_CNTL … #define IDLE_POLL_COUNT(x) … #define IDLE_POLL_COUNT_MASK … #define CP_MEQ_THRESHOLDS … #define MEQ1_START(x) … #define MEQ2_START(x) … #define VGT_VTX_VECT_EJECT_REG … #define VGT_CACHE_INVALIDATION … #define CACHE_INVALIDATION(x) … #define VC_ONLY … #define TC_ONLY … #define VC_AND_TC … #define AUTO_INVLD_EN(x) … #define NO_AUTO … #define ES_AUTO … #define GS_AUTO … #define ES_AND_GS_AUTO … #define VGT_GS_VERTEX_REUSE … #define CC_GC_SHADER_ARRAY_CONFIG … #define INACTIVE_CUS_MASK … #define INACTIVE_CUS_SHIFT … #define GC_USER_SHADER_ARRAY_CONFIG … #define PA_CL_ENHANCE … #define CLIP_VTX_REORDER_ENA … #define NUM_CLIP_SEQ(x) … #define PA_SC_FORCE_EOV_MAX_CNTS … #define FORCE_EOV_MAX_CLK_CNT(x) … #define FORCE_EOV_MAX_REZ_CNT(x) … #define PA_SC_FIFO_SIZE … #define SC_FRONTEND_PRIM_FIFO_SIZE(x) … #define SC_BACKEND_PRIM_FIFO_SIZE(x) … #define SC_HIZ_TILE_FIFO_SIZE(x) … #define SC_EARLYZ_TILE_FIFO_SIZE(x) … #define PA_SC_ENHANCE … #define ENABLE_PA_SC_OUT_OF_ORDER … #define DISABLE_PA_SC_GUIDANCE … #define SQ_CONFIG … #define SH_MEM_BASES … /* if PTR32, these are the bases for scratch and lds */ #define PRIVATE_BASE(x) … #define SHARED_BASE(x) … #define SH_MEM_APE1_BASE … /* if PTR32, this is the base location of GPUVM */ #define SH_MEM_APE1_LIMIT … /* if PTR32, this is the upper limit of GPUVM */ #define SH_MEM_CONFIG … #define PTR32 … #define ALIGNMENT_MODE(x) … #define SH_MEM_ALIGNMENT_MODE_DWORD … #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT … #define SH_MEM_ALIGNMENT_MODE_STRICT … #define SH_MEM_ALIGNMENT_MODE_UNALIGNED … #define DEFAULT_MTYPE(x) … #define APE1_MTYPE(x) … /* valid for both DEFAULT_MTYPE and APE1_MTYPE */ #define MTYPE_CACHED … #define MTYPE_NONCACHED … #define SX_DEBUG_1 … #define SPI_CONFIG_CNTL … #define SPI_CONFIG_CNTL_1 … #define VTX_DONE_DELAY(x) … #define INTERP_ONE_PRIM_PER_ROW … #define TA_CNTL_AUX … #define DB_DEBUG … #define DB_DEBUG2 … #define DB_DEBUG3 … #define CC_RB_BACKEND_DISABLE … #define BACKEND_DISABLE(x) … #define GB_ADDR_CONFIG … #define NUM_PIPES(x) … #define NUM_PIPES_MASK … #define NUM_PIPES_SHIFT … #define PIPE_INTERLEAVE_SIZE(x) … #define PIPE_INTERLEAVE_SIZE_MASK … #define PIPE_INTERLEAVE_SIZE_SHIFT … #define NUM_SHADER_ENGINES(x) … #define NUM_SHADER_ENGINES_MASK … #define NUM_SHADER_ENGINES_SHIFT … #define SHADER_ENGINE_TILE_SIZE(x) … #define SHADER_ENGINE_TILE_SIZE_MASK … #define SHADER_ENGINE_TILE_SIZE_SHIFT … #define ROW_SIZE(x) … #define ROW_SIZE_MASK … #define ROW_SIZE_SHIFT … #define GB_TILE_MODE0 … #define ARRAY_MODE(x) … #define ARRAY_LINEAR_GENERAL … #define ARRAY_LINEAR_ALIGNED … #define ARRAY_1D_TILED_THIN1 … #define ARRAY_2D_TILED_THIN1 … #define ARRAY_PRT_TILED_THIN1 … #define ARRAY_PRT_2D_TILED_THIN1 … #define PIPE_CONFIG(x) … #define ADDR_SURF_P2 … #define ADDR_SURF_P4_8x16 … #define ADDR_SURF_P4_16x16 … #define ADDR_SURF_P4_16x32 … #define ADDR_SURF_P4_32x32 … #define ADDR_SURF_P8_16x16_8x16 … #define ADDR_SURF_P8_16x32_8x16 … #define ADDR_SURF_P8_32x32_8x16 … #define ADDR_SURF_P8_16x32_16x16 … #define ADDR_SURF_P8_32x32_16x16 … #define ADDR_SURF_P8_32x32_16x32 … #define ADDR_SURF_P8_32x64_32x32 … #define ADDR_SURF_P16_32x32_8x16 … #define ADDR_SURF_P16_32x32_16x16 … #define TILE_SPLIT(x) … #define ADDR_SURF_TILE_SPLIT_64B … #define ADDR_SURF_TILE_SPLIT_128B … #define ADDR_SURF_TILE_SPLIT_256B … #define ADDR_SURF_TILE_SPLIT_512B … #define ADDR_SURF_TILE_SPLIT_1KB … #define ADDR_SURF_TILE_SPLIT_2KB … #define ADDR_SURF_TILE_SPLIT_4KB … #define MICRO_TILE_MODE_NEW(x) … #define ADDR_SURF_DISPLAY_MICRO_TILING … #define ADDR_SURF_THIN_MICRO_TILING … #define ADDR_SURF_DEPTH_MICRO_TILING … #define ADDR_SURF_ROTATED_MICRO_TILING … #define SAMPLE_SPLIT(x) … #define ADDR_SURF_SAMPLE_SPLIT_1 … #define ADDR_SURF_SAMPLE_SPLIT_2 … #define ADDR_SURF_SAMPLE_SPLIT_4 … #define ADDR_SURF_SAMPLE_SPLIT_8 … #define GB_MACROTILE_MODE0 … #define BANK_WIDTH(x) … #define ADDR_SURF_BANK_WIDTH_1 … #define ADDR_SURF_BANK_WIDTH_2 … #define ADDR_SURF_BANK_WIDTH_4 … #define ADDR_SURF_BANK_WIDTH_8 … #define BANK_HEIGHT(x) … #define ADDR_SURF_BANK_HEIGHT_1 … #define ADDR_SURF_BANK_HEIGHT_2 … #define ADDR_SURF_BANK_HEIGHT_4 … #define ADDR_SURF_BANK_HEIGHT_8 … #define MACRO_TILE_ASPECT(x) … #define ADDR_SURF_MACRO_ASPECT_1 … #define ADDR_SURF_MACRO_ASPECT_2 … #define ADDR_SURF_MACRO_ASPECT_4 … #define ADDR_SURF_MACRO_ASPECT_8 … #define NUM_BANKS(x) … #define ADDR_SURF_2_BANK … #define ADDR_SURF_4_BANK … #define ADDR_SURF_8_BANK … #define ADDR_SURF_16_BANK … #define CB_HW_CONTROL … #define GC_USER_RB_BACKEND_DISABLE … #define BACKEND_DISABLE_MASK … #define BACKEND_DISABLE_SHIFT … #define TCP_CHAN_STEER_LO … #define TCP_CHAN_STEER_HI … #define TC_CFG_L1_LOAD_POLICY0 … #define TC_CFG_L1_LOAD_POLICY1 … #define TC_CFG_L1_STORE_POLICY … #define TC_CFG_L2_LOAD_POLICY0 … #define TC_CFG_L2_LOAD_POLICY1 … #define TC_CFG_L2_STORE_POLICY0 … #define TC_CFG_L2_STORE_POLICY1 … #define TC_CFG_L2_ATOMIC_POLICY … #define TC_CFG_L1_VOLATILE … #define TC_CFG_L2_VOLATILE … #define CP_RB0_BASE … #define CP_RB0_CNTL … #define RB_BUFSZ(x) … #define RB_BLKSZ(x) … #define BUF_SWAP_32BIT … #define RB_NO_UPDATE … #define RB_RPTR_WR_ENA … #define CP_RB0_RPTR_ADDR … #define RB_RPTR_SWAP_32BIT … #define CP_RB0_RPTR_ADDR_HI … #define CP_RB0_WPTR … #define CP_DEVICE_ID … #define CP_ENDIAN_SWAP … #define CP_RB_VMID … #define CP_PFP_UCODE_ADDR … #define CP_PFP_UCODE_DATA … #define CP_ME_RAM_RADDR … #define CP_ME_RAM_WADDR … #define CP_ME_RAM_DATA … #define CP_CE_UCODE_ADDR … #define CP_CE_UCODE_DATA … #define CP_MEC_ME1_UCODE_ADDR … #define CP_MEC_ME1_UCODE_DATA … #define CP_MEC_ME2_UCODE_ADDR … #define CP_MEC_ME2_UCODE_DATA … #define CP_INT_CNTL_RING0 … #define CNTX_BUSY_INT_ENABLE … #define CNTX_EMPTY_INT_ENABLE … #define PRIV_INSTR_INT_ENABLE … #define PRIV_REG_INT_ENABLE … #define OPCODE_ERROR_INT_ENABLE … #define TIME_STAMP_INT_ENABLE … #define CP_RINGID2_INT_ENABLE … #define CP_RINGID1_INT_ENABLE … #define CP_RINGID0_INT_ENABLE … #define CP_INT_STATUS_RING0 … #define PRIV_INSTR_INT_STAT … #define PRIV_REG_INT_STAT … #define TIME_STAMP_INT_STAT … #define CP_RINGID2_INT_STAT … #define CP_RINGID1_INT_STAT … #define CP_RINGID0_INT_STAT … #define CP_MEM_SLP_CNTL … #define CP_MEM_LS_EN … #define CP_CPF_DEBUG … #define CP_PQ_WPTR_POLL_CNTL … #define WPTR_POLL_EN … #define CP_ME1_PIPE0_INT_CNTL … #define CP_ME1_PIPE1_INT_CNTL … #define CP_ME1_PIPE2_INT_CNTL … #define CP_ME1_PIPE3_INT_CNTL … #define CP_ME2_PIPE0_INT_CNTL … #define CP_ME2_PIPE1_INT_CNTL … #define CP_ME2_PIPE2_INT_CNTL … #define CP_ME2_PIPE3_INT_CNTL … #define DEQUEUE_REQUEST_INT_ENABLE … #define WRM_POLL_TIMEOUT_INT_ENABLE … #define PRIV_REG_INT_ENABLE … #define TIME_STAMP_INT_ENABLE … #define GENERIC2_INT_ENABLE … #define GENERIC1_INT_ENABLE … #define GENERIC0_INT_ENABLE … #define CP_ME1_PIPE0_INT_STATUS … #define CP_ME1_PIPE1_INT_STATUS … #define CP_ME1_PIPE2_INT_STATUS … #define CP_ME1_PIPE3_INT_STATUS … #define CP_ME2_PIPE0_INT_STATUS … #define CP_ME2_PIPE1_INT_STATUS … #define CP_ME2_PIPE2_INT_STATUS … #define CP_ME2_PIPE3_INT_STATUS … #define DEQUEUE_REQUEST_INT_STATUS … #define WRM_POLL_TIMEOUT_INT_STATUS … #define PRIV_REG_INT_STATUS … #define TIME_STAMP_INT_STATUS … #define GENERIC2_INT_STATUS … #define GENERIC1_INT_STATUS … #define GENERIC0_INT_STATUS … #define CP_MAX_CONTEXT … #define CP_RB0_BASE_HI … #define RLC_CNTL … #define RLC_ENABLE … #define RLC_MC_CNTL … #define RLC_MEM_SLP_CNTL … #define RLC_MEM_LS_EN … #define RLC_LB_CNTR_MAX … #define RLC_LB_CNTL … #define LOAD_BALANCE_ENABLE … #define RLC_LB_CNTR_INIT … #define RLC_SAVE_AND_RESTORE_BASE … #define RLC_DRIVER_DMA_STATUS … #define RLC_CP_TABLE_RESTORE … #define RLC_PG_DELAY_2 … #define RLC_GPM_UCODE_ADDR … #define RLC_GPM_UCODE_DATA … #define RLC_GPU_CLOCK_COUNT_LSB … #define RLC_GPU_CLOCK_COUNT_MSB … #define RLC_CAPTURE_GPU_CLOCK_COUNT … #define RLC_UCODE_CNTL … #define RLC_GPM_STAT … #define RLC_GPM_BUSY … #define GFX_POWER_STATUS … #define GFX_CLOCK_STATUS … #define RLC_PG_CNTL … #define GFX_PG_ENABLE … #define GFX_PG_SRC … #define DYN_PER_CU_PG_ENABLE … #define STATIC_PER_CU_PG_ENABLE … #define DISABLE_GDS_PG … #define DISABLE_CP_PG … #define SMU_CLK_SLOWDOWN_ON_PU_ENABLE … #define SMU_CLK_SLOWDOWN_ON_PD_ENABLE … #define RLC_CGTT_MGCG_OVERRIDE … #define RLC_CGCG_CGLS_CTRL … #define CGCG_EN … #define CGLS_EN … #define RLC_PG_DELAY … #define RLC_LB_INIT_CU_MASK … #define RLC_LB_PARAMS … #define RLC_PG_AO_CU_MASK … #define RLC_MAX_PG_CU … #define MAX_PU_CU(x) … #define MAX_PU_CU_MASK … #define RLC_AUTO_PG_CTRL … #define AUTO_PG_EN … #define GRBM_REG_SGIT(x) … #define GRBM_REG_SGIT_MASK … #define RLC_SERDES_WR_CU_MASTER_MASK … #define RLC_SERDES_WR_NONCU_MASTER_MASK … #define RLC_SERDES_WR_CTRL … #define BPM_ADDR(x) … #define BPM_ADDR_MASK … #define CGLS_ENABLE … #define CGCG_OVERRIDE_0 … #define MGCG_OVERRIDE_0 … #define MGCG_OVERRIDE_1 … #define RLC_SERDES_CU_MASTER_BUSY … #define RLC_SERDES_NONCU_MASTER_BUSY … #define SE_MASTER_BUSY_MASK … #define GC_MASTER_BUSY … #define TC0_MASTER_BUSY … #define TC1_MASTER_BUSY … #define RLC_GPM_SCRATCH_ADDR … #define RLC_GPM_SCRATCH_DATA … #define RLC_GPR_REG2 … #define REQ … #define MESSAGE(x) … #define MESSAGE_MASK … #define MSG_ENTER_RLC_SAFE_MODE … #define MSG_EXIT_RLC_SAFE_MODE … #define CP_HPD_EOP_BASE_ADDR … #define CP_HPD_EOP_BASE_ADDR_HI … #define CP_HPD_EOP_VMID … #define CP_HPD_EOP_CONTROL … #define EOP_SIZE(x) … #define EOP_SIZE_MASK … #define CP_MQD_BASE_ADDR … #define CP_MQD_BASE_ADDR_HI … #define CP_HQD_ACTIVE … #define CP_HQD_VMID … #define CP_HQD_PERSISTENT_STATE … #define DEFAULT_CP_HQD_PERSISTENT_STATE … #define CP_HQD_PIPE_PRIORITY … #define CP_HQD_QUEUE_PRIORITY … #define CP_HQD_QUANTUM … #define QUANTUM_EN … #define QUANTUM_SCALE_1MS … #define QUANTUM_DURATION(x) … #define CP_HQD_PQ_BASE … #define CP_HQD_PQ_BASE_HI … #define CP_HQD_PQ_RPTR … #define CP_HQD_PQ_RPTR_REPORT_ADDR … #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI … #define CP_HQD_PQ_WPTR_POLL_ADDR … #define CP_HQD_PQ_WPTR_POLL_ADDR_HI … #define CP_HQD_PQ_DOORBELL_CONTROL … #define DOORBELL_OFFSET(x) … #define DOORBELL_OFFSET_MASK … #define DOORBELL_SOURCE … #define DOORBELL_SCHD_HIT … #define DOORBELL_EN … #define DOORBELL_HIT … #define CP_HQD_PQ_WPTR … #define CP_HQD_PQ_CONTROL … #define QUEUE_SIZE(x) … #define QUEUE_SIZE_MASK … #define RPTR_BLOCK_SIZE(x) … #define RPTR_BLOCK_SIZE_MASK … #define PQ_VOLATILE … #define NO_UPDATE_RPTR … #define UNORD_DISPATCH … #define ROQ_PQ_IB_FLIP … #define PRIV_STATE … #define KMD_QUEUE … #define CP_HQD_IB_BASE_ADDR … #define CP_HQD_IB_BASE_ADDR_HI … #define CP_HQD_IB_RPTR … #define CP_HQD_IB_CONTROL … #define IB_ATC_EN … #define DEFAULT_MIN_IB_AVAIL_SIZE … #define CP_HQD_DEQUEUE_REQUEST … #define DEQUEUE_REQUEST_DRAIN … #define DEQUEUE_REQUEST_RESET … #define CP_MQD_CONTROL … #define MQD_VMID(x) … #define MQD_VMID_MASK … #define CP_HQD_SEMA_CMD … #define CP_HQD_MSG_TYPE … #define CP_HQD_ATOMIC0_PREOP_LO … #define CP_HQD_ATOMIC0_PREOP_HI … #define CP_HQD_ATOMIC1_PREOP_LO … #define CP_HQD_ATOMIC1_PREOP_HI … #define CP_HQD_HQ_SCHEDULER0 … #define CP_HQD_HQ_SCHEDULER1 … #define SH_STATIC_MEM_CONFIG … #define DB_RENDER_CONTROL … #define PA_SC_RASTER_CONFIG … #define RASTER_CONFIG_RB_MAP_0 … #define RASTER_CONFIG_RB_MAP_1 … #define RASTER_CONFIG_RB_MAP_2 … #define RASTER_CONFIG_RB_MAP_3 … #define PKR_MAP(x) … #define VGT_EVENT_INITIATOR … #define SAMPLE_STREAMOUTSTATS1 … #define SAMPLE_STREAMOUTSTATS2 … #define SAMPLE_STREAMOUTSTATS3 … #define CACHE_FLUSH_TS … #define CACHE_FLUSH … #define CS_PARTIAL_FLUSH … #define VGT_STREAMOUT_RESET … #define END_OF_PIPE_INCR_DE … #define END_OF_PIPE_IB_END … #define RST_PIX_CNT … #define VS_PARTIAL_FLUSH … #define PS_PARTIAL_FLUSH … #define CACHE_FLUSH_AND_INV_TS_EVENT … #define ZPASS_DONE … #define CACHE_FLUSH_AND_INV_EVENT … #define PERFCOUNTER_START … #define PERFCOUNTER_STOP … #define PIPELINESTAT_START … #define PIPELINESTAT_STOP … #define PERFCOUNTER_SAMPLE … #define SAMPLE_PIPELINESTAT … #define SO_VGT_STREAMOUT_FLUSH … #define SAMPLE_STREAMOUTSTATS … #define RESET_VTX_CNT … #define VGT_FLUSH … #define BOTTOM_OF_PIPE_TS … #define DB_CACHE_FLUSH_AND_INV … #define FLUSH_AND_INV_DB_DATA_TS … #define FLUSH_AND_INV_DB_META … #define FLUSH_AND_INV_CB_DATA_TS … #define FLUSH_AND_INV_CB_META … #define CS_DONE … #define PS_DONE … #define FLUSH_AND_INV_CB_PIXEL_DATA … #define THREAD_TRACE_START … #define THREAD_TRACE_STOP … #define THREAD_TRACE_FLUSH … #define THREAD_TRACE_FINISH … #define PIXEL_PIPE_STAT_CONTROL … #define PIXEL_PIPE_STAT_DUMP … #define PIXEL_PIPE_STAT_RESET … #define SCRATCH_REG0 … #define SCRATCH_REG1 … #define SCRATCH_REG2 … #define SCRATCH_REG3 … #define SCRATCH_REG4 … #define SCRATCH_REG5 … #define SCRATCH_REG6 … #define SCRATCH_REG7 … #define SCRATCH_UMSK … #define SCRATCH_ADDR … #define CP_SEM_WAIT_TIMER … #define CP_SEM_INCOMPLETE_TIMER_CNTL … #define CP_WAIT_REG_MEM_TIMEOUT … #define GRBM_GFX_INDEX … #define INSTANCE_INDEX(x) … #define SH_INDEX(x) … #define SE_INDEX(x) … #define SH_BROADCAST_WRITES … #define INSTANCE_BROADCAST_WRITES … #define SE_BROADCAST_WRITES … #define VGT_ESGS_RING_SIZE … #define VGT_GSVS_RING_SIZE … #define VGT_PRIMITIVE_TYPE … #define VGT_INDEX_TYPE … #define VGT_NUM_INDICES … #define VGT_NUM_INSTANCES … #define VGT_TF_RING_SIZE … #define VGT_HS_OFFCHIP_PARAM … #define VGT_TF_MEMORY_BASE … #define PA_SU_LINE_STIPPLE_VALUE … #define PA_SC_LINE_STIPPLE_STATE … #define SQC_CACHES … #define CP_PERFMON_CNTL … #define CGTS_SM_CTRL_REG … #define SM_MODE(x) … #define SM_MODE_MASK … #define SM_MODE_ENABLE … #define CGTS_OVERRIDE … #define CGTS_LS_OVERRIDE … #define ON_MONITOR_ADD_EN … #define ON_MONITOR_ADD(x) … #define ON_MONITOR_ADD_MASK … #define CGTS_TCC_DISABLE … #define CGTS_USER_TCC_DISABLE … #define TCC_DISABLE_MASK … #define TCC_DISABLE_SHIFT … #define CB_CGTT_SCLK_CTRL … /* * PM4 */ #define PACKET_TYPE0 … #define PACKET_TYPE1 … #define PACKET_TYPE2 … #define PACKET_TYPE3 … #define CP_PACKET_GET_TYPE(h) … #define CP_PACKET_GET_COUNT(h) … #define CP_PACKET0_GET_REG(h) … #define CP_PACKET3_GET_OPCODE(h) … #define PACKET0(reg, n) … #define CP_PACKET2 … #define PACKET2_PAD_SHIFT … #define PACKET2_PAD_MASK … #define PACKET2(v) … #define PACKET3(op, n) … #define PACKET3_COMPUTE(op, n) … /* Packet 3 types */ #define PACKET3_NOP … #define PACKET3_SET_BASE … #define PACKET3_BASE_INDEX(x) … #define CE_PARTITION_BASE … #define PACKET3_CLEAR_STATE … #define PACKET3_INDEX_BUFFER_SIZE … #define PACKET3_DISPATCH_DIRECT … #define PACKET3_DISPATCH_INDIRECT … #define PACKET3_ATOMIC_GDS … #define PACKET3_ATOMIC_MEM … #define PACKET3_OCCLUSION_QUERY … #define PACKET3_SET_PREDICATION … #define PACKET3_REG_RMW … #define PACKET3_COND_EXEC … #define PACKET3_PRED_EXEC … #define PACKET3_DRAW_INDIRECT … #define PACKET3_DRAW_INDEX_INDIRECT … #define PACKET3_INDEX_BASE … #define PACKET3_DRAW_INDEX_2 … #define PACKET3_CONTEXT_CONTROL … #define PACKET3_INDEX_TYPE … #define PACKET3_DRAW_INDIRECT_MULTI … #define PACKET3_DRAW_INDEX_AUTO … #define PACKET3_NUM_INSTANCES … #define PACKET3_DRAW_INDEX_MULTI_AUTO … #define PACKET3_INDIRECT_BUFFER_CONST … #define PACKET3_STRMOUT_BUFFER_UPDATE … #define PACKET3_DRAW_INDEX_OFFSET_2 … #define PACKET3_DRAW_PREAMBLE … #define PACKET3_WRITE_DATA … #define WRITE_DATA_DST_SEL(x) … /* 0 - register * 1 - memory (sync - via GRBM) * 2 - gl2 * 3 - gds * 4 - reserved * 5 - memory (async - direct) */ #define WR_ONE_ADDR … #define WR_CONFIRM … #define WRITE_DATA_CACHE_POLICY(x) … /* 0 - LRU * 1 - Stream */ #define WRITE_DATA_ENGINE_SEL(x) … /* 0 - me * 1 - pfp * 2 - ce */ #define PACKET3_DRAW_INDEX_INDIRECT_MULTI … #define PACKET3_MEM_SEMAPHORE … #define PACKET3_SEM_USE_MAILBOX … #define PACKET3_SEM_SEL_SIGNAL_TYPE … #define PACKET3_SEM_CLIENT_CODE … #define PACKET3_SEM_SEL_SIGNAL … #define PACKET3_SEM_SEL_WAIT … #define PACKET3_COPY_DW … #define PACKET3_WAIT_REG_MEM … #define WAIT_REG_MEM_FUNCTION(x) … /* 0 - always * 1 - < * 2 - <= * 3 - == * 4 - != * 5 - >= * 6 - > */ #define WAIT_REG_MEM_MEM_SPACE(x) … /* 0 - reg * 1 - mem */ #define WAIT_REG_MEM_OPERATION(x) … /* 0 - wait_reg_mem * 1 - wr_wait_wr_reg */ #define WAIT_REG_MEM_ENGINE(x) … /* 0 - me * 1 - pfp */ #define PACKET3_INDIRECT_BUFFER … #define INDIRECT_BUFFER_TCL2_VOLATILE … #define INDIRECT_BUFFER_VALID … #define INDIRECT_BUFFER_CACHE_POLICY(x) … /* 0 - LRU * 1 - Stream * 2 - Bypass */ #define PACKET3_COPY_DATA … #define PACKET3_PFP_SYNC_ME … #define PACKET3_SURFACE_SYNC … #define PACKET3_DEST_BASE_0_ENA … #define PACKET3_DEST_BASE_1_ENA … #define PACKET3_CB0_DEST_BASE_ENA … #define PACKET3_CB1_DEST_BASE_ENA … #define PACKET3_CB2_DEST_BASE_ENA … #define PACKET3_CB3_DEST_BASE_ENA … #define PACKET3_CB4_DEST_BASE_ENA … #define PACKET3_CB5_DEST_BASE_ENA … #define PACKET3_CB6_DEST_BASE_ENA … #define PACKET3_CB7_DEST_BASE_ENA … #define PACKET3_DB_DEST_BASE_ENA … #define PACKET3_TCL1_VOL_ACTION_ENA … #define PACKET3_TC_VOL_ACTION_ENA … #define PACKET3_TC_WB_ACTION_ENA … #define PACKET3_DEST_BASE_2_ENA … #define PACKET3_DEST_BASE_3_ENA … #define PACKET3_TCL1_ACTION_ENA … #define PACKET3_TC_ACTION_ENA … #define PACKET3_CB_ACTION_ENA … #define PACKET3_DB_ACTION_ENA … #define PACKET3_SH_KCACHE_ACTION_ENA … #define PACKET3_SH_KCACHE_VOL_ACTION_ENA … #define PACKET3_SH_ICACHE_ACTION_ENA … #define PACKET3_COND_WRITE … #define PACKET3_EVENT_WRITE … #define EVENT_TYPE(x) … #define EVENT_INDEX(x) … /* 0 - any non-TS event * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* * 2 - SAMPLE_PIPELINESTAT * 3 - SAMPLE_STREAMOUTSTAT* * 4 - *S_PARTIAL_FLUSH * 5 - EOP events * 6 - EOS events */ #define PACKET3_EVENT_WRITE_EOP … #define EOP_TCL1_VOL_ACTION_EN … #define EOP_TC_VOL_ACTION_EN … #define EOP_TC_WB_ACTION_EN … #define EOP_TCL1_ACTION_EN … #define EOP_TC_ACTION_EN … #define EOP_TCL2_VOLATILE … #define EOP_CACHE_POLICY(x) … /* 0 - LRU * 1 - Stream * 2 - Bypass */ #define DATA_SEL(x) … /* 0 - discard * 1 - send low 32bit data * 2 - send 64bit data * 3 - send 64bit GPU counter value * 4 - send 64bit sys counter value */ #define INT_SEL(x) … /* 0 - none * 1 - interrupt only (DATA_SEL = 0) * 2 - interrupt when data write is confirmed */ #define DST_SEL(x) … /* 0 - MC * 1 - TC/L2 */ #define PACKET3_EVENT_WRITE_EOS … #define PACKET3_RELEASE_MEM … #define PACKET3_PREAMBLE_CNTL … #define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE … #define PACKET3_PREAMBLE_END_CLEAR_STATE … #define PACKET3_DMA_DATA … /* 1. header * 2. CONTROL * 3. SRC_ADDR_LO or DATA [31:0] * 4. SRC_ADDR_HI [31:0] * 5. DST_ADDR_LO [31:0] * 6. DST_ADDR_HI [7:0] * 7. COMMAND [30:21] | BYTE_COUNT [20:0] */ /* CONTROL */ #define PACKET3_DMA_DATA_ENGINE(x) … /* 0 - ME * 1 - PFP */ #define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) … /* 0 - LRU * 1 - Stream * 2 - Bypass */ #define PACKET3_DMA_DATA_SRC_VOLATILE … #define PACKET3_DMA_DATA_DST_SEL(x) … /* 0 - DST_ADDR using DAS * 1 - GDS * 3 - DST_ADDR using L2 */ #define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) … /* 0 - LRU * 1 - Stream * 2 - Bypass */ #define PACKET3_DMA_DATA_DST_VOLATILE … #define PACKET3_DMA_DATA_SRC_SEL(x) … /* 0 - SRC_ADDR using SAS * 1 - GDS * 2 - DATA * 3 - SRC_ADDR using L2 */ #define PACKET3_DMA_DATA_CP_SYNC … /* COMMAND */ #define PACKET3_DMA_DATA_DIS_WC … #define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) … /* 0 - none * 1 - 8 in 16 * 2 - 8 in 32 * 3 - 8 in 64 */ #define PACKET3_DMA_DATA_CMD_DST_SWAP(x) … /* 0 - none * 1 - 8 in 16 * 2 - 8 in 32 * 3 - 8 in 64 */ #define PACKET3_DMA_DATA_CMD_SAS … /* 0 - memory * 1 - register */ #define PACKET3_DMA_DATA_CMD_DAS … /* 0 - memory * 1 - register */ #define PACKET3_DMA_DATA_CMD_SAIC … #define PACKET3_DMA_DATA_CMD_DAIC … #define PACKET3_DMA_DATA_CMD_RAW_WAIT … #define PACKET3_AQUIRE_MEM … #define PACKET3_REWIND … #define PACKET3_LOAD_UCONFIG_REG … #define PACKET3_LOAD_SH_REG … #define PACKET3_LOAD_CONFIG_REG … #define PACKET3_LOAD_CONTEXT_REG … #define PACKET3_SET_CONFIG_REG … #define PACKET3_SET_CONFIG_REG_START … #define PACKET3_SET_CONFIG_REG_END … #define PACKET3_SET_CONTEXT_REG … #define PACKET3_SET_CONTEXT_REG_START … #define PACKET3_SET_CONTEXT_REG_END … #define PACKET3_SET_CONTEXT_REG_INDIRECT … #define PACKET3_SET_SH_REG … #define PACKET3_SET_SH_REG_START … #define PACKET3_SET_SH_REG_END … #define PACKET3_SET_SH_REG_OFFSET … #define PACKET3_SET_QUEUE_REG … #define PACKET3_SET_UCONFIG_REG … #define PACKET3_SET_UCONFIG_REG_START … #define PACKET3_SET_UCONFIG_REG_END … #define PACKET3_SCRATCH_RAM_WRITE … #define PACKET3_SCRATCH_RAM_READ … #define PACKET3_LOAD_CONST_RAM … #define PACKET3_WRITE_CONST_RAM … #define PACKET3_DUMP_CONST_RAM … #define PACKET3_INCREMENT_CE_COUNTER … #define PACKET3_INCREMENT_DE_COUNTER … #define PACKET3_WAIT_ON_CE_COUNTER … #define PACKET3_WAIT_ON_DE_COUNTER_DIFF … #define PACKET3_SWITCH_BUFFER … /* SDMA - first instance at 0xd000, second at 0xd800 */ #define SDMA0_REGISTER_OFFSET … #define SDMA1_REGISTER_OFFSET … #define SDMA0_UCODE_ADDR … #define SDMA0_UCODE_DATA … #define SDMA0_POWER_CNTL … #define SDMA0_CLK_CTRL … #define SDMA0_CNTL … #define TRAP_ENABLE … #define SEM_INCOMPLETE_INT_ENABLE … #define SEM_WAIT_INT_ENABLE … #define DATA_SWAP_ENABLE … #define FENCE_SWAP_ENABLE … #define AUTO_CTXSW_ENABLE … #define CTXEMPTY_INT_ENABLE … #define SDMA0_TILING_CONFIG … #define SDMA0_SEM_INCOMPLETE_TIMER_CNTL … #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL … #define SDMA0_STATUS_REG … #define SDMA_IDLE … #define SDMA0_ME_CNTL … #define SDMA_HALT … #define SDMA0_GFX_RB_CNTL … #define SDMA_RB_ENABLE … #define SDMA_RB_SIZE(x) … #define SDMA_RB_SWAP_ENABLE … #define SDMA_RPTR_WRITEBACK_ENABLE … #define SDMA_RPTR_WRITEBACK_SWAP_ENABLE … #define SDMA_RPTR_WRITEBACK_TIMER(x) … #define SDMA0_GFX_RB_BASE … #define SDMA0_GFX_RB_BASE_HI … #define SDMA0_GFX_RB_RPTR … #define SDMA0_GFX_RB_WPTR … #define SDMA0_GFX_RB_RPTR_ADDR_HI … #define SDMA0_GFX_RB_RPTR_ADDR_LO … #define SDMA0_GFX_IB_CNTL … #define SDMA_IB_ENABLE … #define SDMA_IB_SWAP_ENABLE … #define SDMA_SWITCH_INSIDE_IB … #define SDMA_CMD_VMID(x) … #define SDMA0_GFX_VIRTUAL_ADDR … #define SDMA0_GFX_APE1_CNTL … #define SDMA_PACKET(op, sub_op, e) … /* sDMA opcodes */ #define SDMA_OPCODE_NOP … #define SDMA_OPCODE_COPY … #define SDMA_COPY_SUB_OPCODE_LINEAR … #define SDMA_COPY_SUB_OPCODE_TILED … #define SDMA_COPY_SUB_OPCODE_SOA … #define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW … #define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW … #define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW … #define SDMA_OPCODE_WRITE … #define SDMA_WRITE_SUB_OPCODE_LINEAR … #define SDMA_WRITE_SUB_OPCODE_TILED … #define SDMA_OPCODE_INDIRECT_BUFFER … #define SDMA_OPCODE_FENCE … #define SDMA_OPCODE_TRAP … #define SDMA_OPCODE_SEMAPHORE … #define SDMA_SEMAPHORE_EXTRA_O … /* 0 - increment * 1 - write 1 */ #define SDMA_SEMAPHORE_EXTRA_S … /* 0 - wait * 1 - signal */ #define SDMA_SEMAPHORE_EXTRA_M … /* mailbox */ #define SDMA_OPCODE_POLL_REG_MEM … #define SDMA_POLL_REG_MEM_EXTRA_OP(x) … /* 0 - wait_reg_mem * 1 - wr_wait_wr_reg */ #define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) … /* 0 - always * 1 - < * 2 - <= * 3 - == * 4 - != * 5 - >= * 6 - > */ #define SDMA_POLL_REG_MEM_EXTRA_M … /* 0 = register * 1 = memory */ #define SDMA_OPCODE_COND_EXEC … #define SDMA_OPCODE_CONSTANT_FILL … #define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) … /* 0 = byte fill * 2 = DW fill */ #define SDMA_OPCODE_GENERATE_PTE_PDE … #define SDMA_OPCODE_TIMESTAMP … #define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL … #define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL … #define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL … #define SDMA_OPCODE_SRBM_WRITE … #define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) … /* byte mask */ /* UVD */ #define UVD_UDEC_ADDR_CONFIG … #define UVD_UDEC_DB_ADDR_CONFIG … #define UVD_UDEC_DBW_ADDR_CONFIG … #define UVD_NO_OP … #define UVD_LMI_EXT40_ADDR … #define UVD_GP_SCRATCH4 … #define UVD_LMI_ADDR_EXT … #define UVD_VCPU_CACHE_OFFSET0 … #define UVD_VCPU_CACHE_SIZE0 … #define UVD_VCPU_CACHE_OFFSET1 … #define UVD_VCPU_CACHE_SIZE1 … #define UVD_VCPU_CACHE_OFFSET2 … #define UVD_VCPU_CACHE_SIZE2 … #define UVD_RBC_RB_RPTR … #define UVD_RBC_RB_WPTR … #define UVD_CGC_CTRL … #define DCM … #define CG_DT(x) … #define CG_DT_MASK … #define CLK_OD(x) … #define CLK_OD_MASK … #define UVD_STATUS … /* UVD clocks */ #define CG_DCLK_CNTL … #define DCLK_DIVIDER_MASK … #define DCLK_DIR_CNTL_EN … #define CG_DCLK_STATUS … #define DCLK_STATUS … #define CG_VCLK_CNTL … #define CG_VCLK_STATUS … /* UVD CTX indirect */ #define UVD_CGC_MEM_CTRL … /* VCE */ #define VCE_VCPU_CACHE_OFFSET0 … #define VCE_VCPU_CACHE_SIZE0 … #define VCE_VCPU_CACHE_OFFSET1 … #define VCE_VCPU_CACHE_SIZE1 … #define VCE_VCPU_CACHE_OFFSET2 … #define VCE_VCPU_CACHE_SIZE2 … #define VCE_RB_RPTR2 … #define VCE_RB_WPTR2 … #define VCE_RB_RPTR … #define VCE_RB_WPTR … #define VCE_CLOCK_GATING_A … #define CGC_CLK_GATE_DLY_TIMER_MASK … #define CGC_CLK_GATE_DLY_TIMER(x) … #define CGC_CLK_GATER_OFF_DLY_TIMER_MASK … #define CGC_CLK_GATER_OFF_DLY_TIMER(x) … #define CGC_UENC_WAIT_AWAKE … #define VCE_CLOCK_GATING_B … #define VCE_CGTT_CLK_OVERRIDE … #define VCE_UENC_CLOCK_GATING … #define CLOCK_ON_DELAY_MASK … #define CLOCK_ON_DELAY(x) … #define CLOCK_OFF_DELAY_MASK … #define CLOCK_OFF_DELAY(x) … #define VCE_UENC_REG_CLOCK_GATING … #define VCE_SYS_INT_EN … #define VCE_SYS_INT_TRAP_INTERRUPT_EN … #define VCE_LMI_VCPU_CACHE_40BIT_BAR … #define VCE_LMI_CTRL2 … #define VCE_LMI_CTRL … #define VCE_LMI_VM_CTRL … #define VCE_LMI_SWAP_CNTL … #define VCE_LMI_SWAP_CNTL1 … #define VCE_LMI_CACHE_CTRL … #define VCE_CMD_NO_OP … #define VCE_CMD_END … #define VCE_CMD_IB … #define VCE_CMD_FENCE … #define VCE_CMD_TRAP … #define VCE_CMD_IB_AUTO … #define VCE_CMD_SEMAPHORE … #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS … #define ATC_VMID0_PASID_MAPPING … #define ATC_VMID_PASID_MAPPING_PASID_MASK … #define ATC_VMID_PASID_MAPPING_PASID_SHIFT … #define ATC_VMID_PASID_MAPPING_VALID_MASK … #define ATC_VMID_PASID_MAPPING_VALID_SHIFT … #define ATC_VM_APERTURE0_CNTL … #define ATS_ACCESS_MODE_NEVER … #define ATS_ACCESS_MODE_ALWAYS … #define ATC_VM_APERTURE0_CNTL2 … #define ATC_VM_APERTURE0_HIGH_ADDR … #define ATC_VM_APERTURE0_LOW_ADDR … #define ATC_VM_APERTURE1_CNTL … #define ATC_VM_APERTURE1_CNTL2 … #define ATC_VM_APERTURE1_HIGH_ADDR … #define ATC_VM_APERTURE1_LOW_ADDR … #define IH_VMID_0_LUT … #endif
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