/* * Copyright 2011 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef RV6XXD_H #define RV6XXD_H /* RV6xx power management */ #define SPLL_CNTL_MODE … #define SPLL_DIV_SYNC … #define GENERAL_PWRMGT … #define GLOBAL_PWRMGT_EN … #define STATIC_PM_EN … #define MOBILE_SU … #define THERMAL_PROTECTION_DIS … #define THERMAL_PROTECTION_TYPE … #define ENABLE_GEN2PCIE … #define SW_GPIO_INDEX(x) … #define SW_GPIO_INDEX_MASK … #define LOW_VOLT_D2_ACPI … #define LOW_VOLT_D3_ACPI … #define VOLT_PWRMGT_EN … #define BACKBIAS_PAD_EN … #define BACKBIAS_VALUE … #define BACKBIAS_DPM_CNTL … #define DYN_SPREAD_SPECTRUM_EN … #define MCLK_PWRMGT_CNTL … #define MPLL_PWRMGT_OFF … #define YCLK_TURNOFF … #define MPLL_TURNOFF … #define SU_MCLK_USE_BCLK … #define DLL_READY … #define MC_BUSY … #define MC_INT_CNTL … #define MRDCKA_SLEEP … #define MRDCKB_SLEEP … #define MRDCKC_SLEEP … #define MRDCKD_SLEEP … #define MRDCKE_SLEEP … #define MRDCKF_SLEEP … #define MRDCKG_SLEEP … #define MRDCKH_SLEEP … #define MRDCKA_RESET … #define MRDCKB_RESET … #define MRDCKC_RESET … #define MRDCKD_RESET … #define MRDCKE_RESET … #define MRDCKF_RESET … #define MRDCKG_RESET … #define MRDCKH_RESET … #define DLL_READY_READ … #define USE_DISPLAY_GAP … #define USE_DISPLAY_URGENT_NORMAL … #define USE_DISPLAY_GAP_CTXSW … #define MPLL_TURNOFF_D2 … #define USE_DISPLAY_URGENT_CTXSW … #define MPLL_FREQ_LEVEL_0 … #define LEVEL0_MPLL_POST_DIV(x) … #define LEVEL0_MPLL_POST_DIV_MASK … #define LEVEL0_MPLL_FB_DIV(x) … #define LEVEL0_MPLL_FB_DIV_MASK … #define LEVEL0_MPLL_REF_DIV(x) … #define LEVEL0_MPLL_REF_DIV_MASK … #define LEVEL0_MPLL_DIV_EN … #define LEVEL0_DLL_BYPASS … #define LEVEL0_DLL_RESET … #define VID_RT … #define VID_CRT(x) … #define VID_CRT_MASK … #define VID_CRTU(x) … #define VID_CRTU_MASK … #define SSTU(x) … #define SSTU_MASK … #define VID_SWT(x) … #define VID_SWT_MASK … #define BRT(x) … #define BRT_MASK … #define TARGET_AND_CURRENT_PROFILE_INDEX … #define TARGET_PROFILE_INDEX_MASK … #define TARGET_PROFILE_INDEX_SHIFT … #define CURRENT_PROFILE_INDEX_MASK … #define CURRENT_PROFILE_INDEX_SHIFT … #define DYN_PWR_ENTER_INDEX(x) … #define DYN_PWR_ENTER_INDEX_MASK … #define DYN_PWR_ENTER_INDEX_SHIFT … #define CURR_MCLK_INDEX_MASK … #define CURR_MCLK_INDEX_SHIFT … #define CURR_SCLK_INDEX_MASK … #define CURR_SCLK_INDEX_SHIFT … #define CURR_VID_INDEX_MASK … #define CURR_VID_INDEX_SHIFT … #define VID_UPPER_GPIO_CNTL … #define CTXSW_UPPER_GPIO_VALUES(x) … #define CTXSW_UPPER_GPIO_VALUES_MASK … #define HIGH_UPPER_GPIO_VALUES(x) … #define HIGH_UPPER_GPIO_VALUES_MASK … #define MEDIUM_UPPER_GPIO_VALUES(x) … #define MEDIUM_UPPER_GPIO_VALUES_MASK … #define LOW_UPPER_GPIO_VALUES(x) … #define LOW_UPPER_GPIO_VALUES_MASK … #define CTXSW_BACKBIAS_VALUE … #define HIGH_BACKBIAS_VALUE … #define MEDIUM_BACKBIAS_VALUE … #define LOW_BACKBIAS_VALUE … #define CG_DISPLAY_GAP_CNTL … #define DISP1_GAP(x) … #define DISP1_GAP_MASK … #define DISP2_GAP(x) … #define DISP2_GAP_MASK … #define VBI_TIMER_COUNT(x) … #define VBI_TIMER_COUNT_MASK … #define VBI_TIMER_UNIT(x) … #define VBI_TIMER_UNIT_MASK … #define DISP1_GAP_MCHG(x) … #define DISP1_GAP_MCHG_MASK … #define DISP2_GAP_MCHG(x) … #define DISP2_GAP_MCHG_MASK … #define CG_THERMAL_CTRL … #define DPM_EVENT_SRC(x) … #define DPM_EVENT_SRC_MASK … #define THERM_INC_CLK … #define TOFFSET(x) … #define TOFFSET_MASK … #define DIG_THERM_DPM(x) … #define DIG_THERM_DPM_MASK … #define CTF_SEL(x) … #define CTF_SEL_MASK … #define CTF_PAD_POLARITY … #define CTF_PAD_EN … #define CG_SPLL_SPREAD_SPECTRUM_LOW … #define SSEN … #define CLKS(x) … #define CLKS_MASK … #define CLKS_SHIFT … #define CLKV(x) … #define CLKV_MASK … #define CLKV_SHIFT … #define CG_MPLL_SPREAD_SPECTRUM … #define CITF_CNTL … #define BLACKOUT_RD … #define BLACKOUT_WR … #define RAMCFG … #define NOOFBANK_SHIFT … #define NOOFBANK_MASK … #define NOOFRANK_SHIFT … #define NOOFRANK_MASK … #define NOOFROWS_SHIFT … #define NOOFROWS_MASK … #define NOOFCOLS_SHIFT … #define NOOFCOLS_MASK … #define CHANSIZE_SHIFT … #define CHANSIZE_MASK … #define BURSTLENGTH_SHIFT … #define BURSTLENGTH_MASK … #define CHANSIZE_OVERRIDE … #define SQM_RATIO … #define STATE0(x) … #define STATE0_MASK … #define STATE1(x) … #define STATE1_MASK … #define STATE2(x) … #define STATE2_MASK … #define STATE3(x) … #define STATE3_MASK … #define ARB_RFSH_CNTL … #define ENABLE … #define ARB_RFSH_RATE … #define POWERMODE0(x) … #define POWERMODE0_MASK … #define POWERMODE1(x) … #define POWERMODE1_MASK … #define POWERMODE2(x) … #define POWERMODE2_MASK … #define POWERMODE3(x) … #define POWERMODE3_MASK … #define MC_SEQ_DRAM … #define CKE_DYN … #define MC_SEQ_CMD … #define MC_SEQ_RESERVE_S … #define MC_SEQ_RESERVE_M … #define LVTMA_DATA_SYNCHRONIZATION … #define LVTMA_PFREQCHG … #define DCE3_LVTMA_DATA_SYNCHRONIZATION … /* PCIE indirect regs */ #define PCIE_P_CNTL … #define P_PLL_PWRDN_IN_L1L23 … #define P_PLL_BUF_PDNB … #define P_PLL_PDNB … #define P_ALLOW_PRX_FRONTEND_SHUTOFF … /* PCIE PORT indirect regs */ #define PCIE_LC_CNTL … #define LC_L0S_INACTIVITY(x) … #define LC_L0S_INACTIVITY_MASK … #define LC_L0S_INACTIVITY_SHIFT … #define LC_L1_INACTIVITY(x) … #define LC_L1_INACTIVITY_MASK … #define LC_L1_INACTIVITY_SHIFT … #define LC_PMI_TO_L1_DIS … #define LC_ASPM_TO_L1_DIS … #define PCIE_LC_SPEED_CNTL … #define LC_GEN2_EN … #define LC_INITIATE_LINK_SPEED_CHANGE … #define LC_CURRENT_DATA_RATE … #define LC_HW_VOLTAGE_IF_CONTROL(x) … #define LC_HW_VOLTAGE_IF_CONTROL_MASK … #define LC_HW_VOLTAGE_IF_CONTROL_SHIFT … #define LC_OTHER_SIDE_EVER_SENT_GEN2 … #define LC_OTHER_SIDE_SUPPORTS_GEN2 … #endif
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