#include "amdgpu.h"
#include "amdgpu_atombios.h"
#include "nbif_v6_3_1.h"
#include "nbif/nbif_6_3_1_offset.h"
#include "nbif/nbif_6_3_1_sh_mask.h"
#include "pcie/pcie_6_1_0_offset.h"
#include "pcie/pcie_6_1_0_sh_mask.h"
#include <uapi/linux/kfd_ioctl.h>
static void nbif_v6_3_1_remap_hdp_registers(struct amdgpu_device *adev)
{ … }
static u32 nbif_v6_3_1_get_rev_id(struct amdgpu_device *adev)
{ … }
static void nbif_v6_3_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
{ … }
static u32 nbif_v6_3_1_get_memsize(struct amdgpu_device *adev)
{ … }
static void nbif_v6_3_1_sdma_doorbell_range(struct amdgpu_device *adev,
int instance, bool use_doorbell,
int doorbell_index,
int doorbell_size)
{ … }
static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev,
bool use_doorbell, int doorbell_index,
int instance)
{ … }
static void nbif_v6_3_1_gc_doorbell_init(struct amdgpu_device *adev)
{ … }
static void nbif_v6_3_1_enable_doorbell_aperture(struct amdgpu_device *adev,
bool enable)
{ … }
static void
nbif_v6_3_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
bool enable)
{ … }
static void nbif_v6_3_1_ih_doorbell_range(struct amdgpu_device *adev,
bool use_doorbell, int doorbell_index)
{ … }
static void nbif_v6_3_1_ih_control(struct amdgpu_device *adev)
{ … }
static void
nbif_v6_3_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
bool enable)
{ … }
static void
nbif_v6_3_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
bool enable)
{ … }
static void
nbif_v6_3_1_get_clockgating_state(struct amdgpu_device *adev,
u64 *flags)
{ … }
static u32 nbif_v6_3_1_get_hdp_flush_req_offset(struct amdgpu_device *adev)
{ … }
static u32 nbif_v6_3_1_get_hdp_flush_done_offset(struct amdgpu_device *adev)
{ … }
static u32 nbif_v6_3_1_get_pcie_index_offset(struct amdgpu_device *adev)
{ … }
static u32 nbif_v6_3_1_get_pcie_data_offset(struct amdgpu_device *adev)
{ … }
const struct nbio_hdp_flush_reg nbif_v6_3_1_hdp_flush_reg = …;
static void nbif_v6_3_1_init_registers(struct amdgpu_device *adev)
{ … }
static u32 nbif_v6_3_1_get_rom_offset(struct amdgpu_device *adev)
{ … }
#ifdef CONFIG_PCIEASPM
static void nbif_v6_3_1_program_ltr(struct amdgpu_device *adev)
{ … }
#endif
static void nbif_v6_3_1_program_aspm(struct amdgpu_device *adev)
{ … }
#define MMIO_REG_HOLE_OFFSET …
static void nbif_v6_3_1_set_reg_remap(struct amdgpu_device *adev)
{ … }
const struct amdgpu_nbio_funcs nbif_v6_3_1_funcs = …;
static void nbif_v6_3_1_sriov_ih_doorbell_range(struct amdgpu_device *adev,
bool use_doorbell, int doorbell_index)
{ … }
static void nbif_v6_3_1_sriov_sdma_doorbell_range(struct amdgpu_device *adev,
int instance, bool use_doorbell,
int doorbell_index,
int doorbell_size)
{ … }
static void nbif_v6_3_1_sriov_vcn_doorbell_range(struct amdgpu_device *adev,
bool use_doorbell,
int doorbell_index, int instance)
{ … }
static void nbif_v6_3_1_sriov_gc_doorbell_init(struct amdgpu_device *adev)
{ … }
const struct amdgpu_nbio_funcs nbif_v6_3_1_sriov_funcs = …;