/* * Copyright 2011 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Alex Deucher */ #include "radeon.h" #include "radeon_asic.h" #include "rv770.h" #include "rv770d.h" #include "r600_dpm.h" #include "rv770_dpm.h" #include "cypress_dpm.h" #include "atom.h" #include "evergreen.h" #include <linux/seq_file.h> #define MC_CG_ARB_FREQ_F0 … #define MC_CG_ARB_FREQ_F1 … #define MC_CG_ARB_FREQ_F2 … #define MC_CG_ARB_FREQ_F3 … #define MC_CG_SEQ_DRAMCONF_S0 … #define MC_CG_SEQ_DRAMCONF_S1 … #define PCIE_BUS_CLK … #define TCLK … #define SMC_RAM_END … struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps) { … } struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev) { … } struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev) { … } static void rv770_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable) { … } static void rv770_enable_l0s(struct radeon_device *rdev) { … } static void rv770_enable_l1(struct radeon_device *rdev) { … } static void rv770_enable_pll_sleep_in_l1(struct radeon_device *rdev) { … } static void rv770_gfx_clock_gating_enable(struct radeon_device *rdev, bool enable) { … } static void rv770_mg_clock_gating_enable(struct radeon_device *rdev, bool enable) { … } void rv770_restore_cgcg(struct radeon_device *rdev) { … } static void rv770_start_dpm(struct radeon_device *rdev) { … } void rv770_stop_dpm(struct radeon_device *rdev) { … } bool rv770_dpm_enabled(struct radeon_device *rdev) { … } void rv770_enable_thermal_protection(struct radeon_device *rdev, bool enable) { … } void rv770_enable_acpi_pm(struct radeon_device *rdev) { … } u8 rv770_get_seq_value(struct radeon_device *rdev, struct rv7xx_pl *pl) { … } #if 0 int rv770_read_smc_soft_register(struct radeon_device *rdev, u16 reg_offset, u32 *value) { struct rv7xx_power_info *pi = rv770_get_pi(rdev); return rv770_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset, value, pi->sram_end); } #endif int rv770_write_smc_soft_register(struct radeon_device *rdev, u16 reg_offset, u32 value) { … } int rv770_populate_smc_t(struct radeon_device *rdev, struct radeon_ps *radeon_state, RV770_SMC_SWSTATE *smc_state) { … } int rv770_populate_smc_sp(struct radeon_device *rdev, struct radeon_ps *radeon_state, RV770_SMC_SWSTATE *smc_state) { … } static void rv770_calculate_fractional_mpll_feedback_divider(u32 memory_clock, u32 reference_clock, bool gddr5, struct atom_clock_dividers *dividers, u32 *clkf, u32 *clkfrac) { … } static int rv770_encode_yclk_post_div(u32 postdiv, u32 *encoded_postdiv) { … } u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf) { … } static int rv770_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, RV7XX_SMC_MCLK_VALUE *mclk) { … } static int rv770_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, RV770_SMC_SCLK_VALUE *sclk) { … } int rv770_populate_vddc_value(struct radeon_device *rdev, u16 vddc, RV770_SMC_VOLTAGE_VALUE *voltage) { … } int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, RV770_SMC_VOLTAGE_VALUE *voltage) { … } static int rv770_convert_power_level_to_smc(struct radeon_device *rdev, struct rv7xx_pl *pl, RV770_SMC_HW_PERFORMANCE_LEVEL *level, u8 watermark_level) { … } static int rv770_convert_power_state_to_smc(struct radeon_device *rdev, struct radeon_ps *radeon_state, RV770_SMC_SWSTATE *smc_state) { … } u32 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev, u32 engine_clock) { … } static void rv770_program_memory_timing_parameters(struct radeon_device *rdev, struct radeon_ps *radeon_state) { … } void rv770_enable_backbias(struct radeon_device *rdev, bool enable) { … } static void rv770_enable_spread_spectrum(struct radeon_device *rdev, bool enable) { … } static void rv770_program_mpll_timing_parameters(struct radeon_device *rdev) { … } void rv770_setup_bsp(struct radeon_device *rdev) { … } void rv770_program_git(struct radeon_device *rdev) { … } void rv770_program_tp(struct radeon_device *rdev) { … } void rv770_program_tpp(struct radeon_device *rdev) { … } void rv770_program_sstp(struct radeon_device *rdev) { … } void rv770_program_engine_speed_parameters(struct radeon_device *rdev) { … } static void rv770_enable_display_gap(struct radeon_device *rdev) { … } void rv770_program_vc(struct radeon_device *rdev) { … } void rv770_clear_vc(struct radeon_device *rdev) { … } int rv770_upload_firmware(struct radeon_device *rdev) { … } static int rv770_populate_smc_acpi_state(struct radeon_device *rdev, RV770_SMC_STATETABLE *table) { … } int rv770_populate_initial_mvdd_value(struct radeon_device *rdev, RV770_SMC_VOLTAGE_VALUE *voltage) { … } static int rv770_populate_smc_initial_state(struct radeon_device *rdev, struct radeon_ps *radeon_state, RV770_SMC_STATETABLE *table) { … } static int rv770_populate_smc_vddc_table(struct radeon_device *rdev, RV770_SMC_STATETABLE *table) { … } static int rv770_populate_smc_mvdd_table(struct radeon_device *rdev, RV770_SMC_STATETABLE *table) { … } static int rv770_init_smc_table(struct radeon_device *rdev, struct radeon_ps *radeon_boot_state) { … } static int rv770_construct_vddc_table(struct radeon_device *rdev) { … } static u32 rv770_get_mclk_split_point(struct atom_memory_info *memory_info) { … } static int rv770_get_mvdd_pin_configuration(struct radeon_device *rdev) { … } u8 rv770_get_memory_module_index(struct radeon_device *rdev) { … } static int rv770_get_mvdd_configuration(struct radeon_device *rdev) { … } void rv770_enable_voltage_control(struct radeon_device *rdev, bool enable) { … } static void rv770_program_display_gap(struct radeon_device *rdev) { … } static void rv770_enable_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable) { … } static void r7xx_program_memory_timing_parameters(struct radeon_device *rdev, struct radeon_ps *radeon_new_state) { … } static int rv770_upload_sw_state(struct radeon_device *rdev, struct radeon_ps *radeon_new_state) { … } int rv770_halt_smc(struct radeon_device *rdev) { … } int rv770_resume_smc(struct radeon_device *rdev) { … } int rv770_set_sw_state(struct radeon_device *rdev) { … } int rv770_set_boot_state(struct radeon_device *rdev) { … } void rv770_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, struct radeon_ps *new_ps, struct radeon_ps *old_ps) { … } void rv770_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, struct radeon_ps *new_ps, struct radeon_ps *old_ps) { … } int rv770_restrict_performance_levels_before_switch(struct radeon_device *rdev) { … } int rv770_dpm_force_performance_level(struct radeon_device *rdev, enum radeon_dpm_forced_level level) { … } void r7xx_start_smc(struct radeon_device *rdev) { … } void r7xx_stop_smc(struct radeon_device *rdev) { … } static void rv770_read_clock_registers(struct radeon_device *rdev) { … } static void r7xx_read_clock_registers(struct radeon_device *rdev) { … } void rv770_read_voltage_smio_registers(struct radeon_device *rdev) { … } void rv770_reset_smio_status(struct radeon_device *rdev) { … } void rv770_get_memory_type(struct radeon_device *rdev) { … } void rv770_get_pcie_gen2_status(struct radeon_device *rdev) { … } #if 0 static int rv770_enter_ulp_state(struct radeon_device *rdev) { struct rv7xx_power_info *pi = rv770_get_pi(rdev); if (pi->gfx_clock_gating) { WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); RREG32(GB_TILING_CONFIG); } WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower), ~HOST_SMC_MSG_MASK); udelay(7000); return 0; } static int rv770_exit_ulp_state(struct radeon_device *rdev) { struct rv7xx_power_info *pi = rv770_get_pi(rdev); int i; WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_ResumeFromMinimumPower), ~HOST_SMC_MSG_MASK); udelay(7000); for (i = 0; i < rdev->usec_timeout; i++) { if (((RREG32(SMC_MSG) & HOST_SMC_RESP_MASK) >> HOST_SMC_RESP_SHIFT) == 1) break; udelay(1000); } if (pi->gfx_clock_gating) WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); return 0; } #endif static void rv770_get_mclk_odt_threshold(struct radeon_device *rdev) { … } void rv770_get_max_vddc(struct radeon_device *rdev) { … } void rv770_program_response_times(struct radeon_device *rdev) { … } static void rv770_program_dcodt_before_state_switch(struct radeon_device *rdev, struct radeon_ps *radeon_new_state, struct radeon_ps *radeon_current_state) { … } static void rv770_program_dcodt_after_state_switch(struct radeon_device *rdev, struct radeon_ps *radeon_new_state, struct radeon_ps *radeon_current_state) { … } static void rv770_retrieve_odt_values(struct radeon_device *rdev) { … } static void rv770_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) { … } void rv770_enable_auto_throttle_source(struct radeon_device *rdev, enum radeon_dpm_auto_throttle_src source, bool enable) { … } static int rv770_set_thermal_temperature_range(struct radeon_device *rdev, int min_temp, int max_temp) { … } int rv770_dpm_enable(struct radeon_device *rdev) { … } int rv770_dpm_late_enable(struct radeon_device *rdev) { … } void rv770_dpm_disable(struct radeon_device *rdev) { … } int rv770_dpm_set_power_state(struct radeon_device *rdev) { … } #if 0 void rv770_dpm_reset_asic(struct radeon_device *rdev) { struct rv7xx_power_info *pi = rv770_get_pi(rdev); struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; rv770_restrict_performance_levels_before_switch(rdev); if (pi->dcodt) rv770_program_dcodt_before_state_switch(rdev, boot_ps, boot_ps); rv770_set_boot_state(rdev); if (pi->dcodt) rv770_program_dcodt_after_state_switch(rdev, boot_ps, boot_ps); } #endif void rv770_dpm_setup_asic(struct radeon_device *rdev) { … } void rv770_dpm_display_configuration_changed(struct radeon_device *rdev) { … } power_info; pplib_clock_info; pplib_power_state; static void rv7xx_parse_pplib_non_clock_info(struct radeon_device *rdev, struct radeon_ps *rps, struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, u8 table_rev) { … } static void rv7xx_parse_pplib_clock_info(struct radeon_device *rdev, struct radeon_ps *rps, int index, union pplib_clock_info *clock_info) { … } int rv7xx_parse_power_table(struct radeon_device *rdev) { … } void rv770_get_engine_memory_ss(struct radeon_device *rdev) { … } int rv770_dpm_init(struct radeon_device *rdev) { … } void rv770_dpm_print_power_state(struct radeon_device *rdev, struct radeon_ps *rps) { … } void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, struct seq_file *m) { … } u32 rv770_dpm_get_current_sclk(struct radeon_device *rdev) { … } u32 rv770_dpm_get_current_mclk(struct radeon_device *rdev) { … } void rv770_dpm_fini(struct radeon_device *rdev) { … } u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low) { … } u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low) { … } bool rv770_dpm_vblank_too_short(struct radeon_device *rdev) { … }
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