/* * Copyright 2011 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef RV730_H #define RV730_H #define CG_SPLL_FUNC_CNTL … #define SPLL_RESET … #define SPLL_SLEEP … #define SPLL_DIVEN … #define SPLL_BYPASS_EN … #define SPLL_REF_DIV(x) … #define SPLL_REF_DIV_MASK … #define SPLL_HILEN(x) … #define SPLL_HILEN_MASK … #define SPLL_LOLEN(x) … #define SPLL_LOLEN_MASK … #define CG_SPLL_FUNC_CNTL_2 … #define SCLK_MUX_SEL(x) … #define SCLK_MUX_SEL_MASK … #define CG_SPLL_FUNC_CNTL_3 … #define SPLL_FB_DIV(x) … #define SPLL_FB_DIV_MASK … #define SPLL_DITHEN … #define CG_MPLL_FUNC_CNTL … #define MPLL_RESET … #define MPLL_SLEEP … #define MPLL_DIVEN … #define MPLL_BYPASS_EN … #define MPLL_REF_DIV(x) … #define MPLL_REF_DIV_MASK … #define MPLL_HILEN(x) … #define MPLL_HILEN_MASK … #define MPLL_LOLEN(x) … #define MPLL_LOLEN_MASK … #define CG_MPLL_FUNC_CNTL_2 … #define MCLK_MUX_SEL(x) … #define MCLK_MUX_SEL_MASK … #define CG_MPLL_FUNC_CNTL_3 … #define MPLL_FB_DIV(x) … #define MPLL_FB_DIV_MASK … #define MPLL_DITHEN … #define CG_TCI_MPLL_SPREAD_SPECTRUM … #define CG_TCI_MPLL_SPREAD_SPECTRUM_2 … #define GENERAL_PWRMGT … #define GLOBAL_PWRMGT_EN … #define STATIC_PM_EN … #define THERMAL_PROTECTION_DIS … #define THERMAL_PROTECTION_TYPE … #define ENABLE_GEN2PCIE … #define ENABLE_GEN2XSP … #define SW_SMIO_INDEX(x) … #define SW_SMIO_INDEX_MASK … #define LOW_VOLT_D2_ACPI … #define LOW_VOLT_D3_ACPI … #define VOLT_PWRMGT_EN … #define BACKBIAS_PAD_EN … #define BACKBIAS_VALUE … #define DYN_SPREAD_SPECTRUM_EN … #define AC_DC_SW … #define SCLK_PWRMGT_CNTL … #define SCLK_PWRMGT_OFF … #define SCLK_LOW_D1 … #define FIR_RESET … #define FIR_FORCE_TREND_SEL … #define FIR_TREND_MODE … #define DYN_GFX_CLK_OFF_EN … #define GFX_CLK_FORCE_ON … #define GFX_CLK_REQUEST_OFF … #define GFX_CLK_FORCE_OFF … #define GFX_CLK_OFF_ACPI_D1 … #define GFX_CLK_OFF_ACPI_D2 … #define GFX_CLK_OFF_ACPI_D3 … #define TCI_MCLK_PWRMGT_CNTL … #define MPLL_PWRMGT_OFF … #define DLL_READY … #define MC_INT_CNTL … #define MRDCKA_SLEEP … #define MRDCKB_SLEEP … #define MRDCKC_SLEEP … #define MRDCKD_SLEEP … #define MRDCKE_SLEEP … #define MRDCKF_SLEEP … #define MRDCKG_SLEEP … #define MRDCKH_SLEEP … #define MRDCKA_RESET … #define MRDCKB_RESET … #define MRDCKC_RESET … #define MRDCKD_RESET … #define MRDCKE_RESET … #define MRDCKF_RESET … #define MRDCKG_RESET … #define MRDCKH_RESET … #define DLL_READY_READ … #define USE_DISPLAY_GAP … #define USE_DISPLAY_URGENT_NORMAL … #define MPLL_TURNOFF_D2 … #define TCI_DLL_CNTL … #define CG_PG_CNTL … #define PWRGATE_ENABLE … #define CG_AT … #define CG_R(x) … #define CG_R_MASK … #define CG_L(x) … #define CG_L_MASK … #define CG_SPLL_SPREAD_SPECTRUM … #define SSEN … #define CLK_S(x) … #define CLK_S_MASK … #define CG_SPLL_SPREAD_SPECTRUM_2 … #define CLK_V(x) … #define CLK_V_MASK … #define MC_ARB_DRAM_TIMING … #define MC_ARB_DRAM_TIMING2 … #define MC_ARB_RFSH_RATE … #define POWERMODE0(x) … #define POWERMODE0_MASK … #define POWERMODE1(x) … #define POWERMODE1_MASK … #define POWERMODE2(x) … #define POWERMODE2_MASK … #define POWERMODE3(x) … #define POWERMODE3_MASK … #define MC_ARB_DRAM_TIMING_1 … #define MC_ARB_DRAM_TIMING_2 … #define MC_ARB_DRAM_TIMING_3 … #define MC_ARB_DRAM_TIMING2_1 … #define MC_ARB_DRAM_TIMING2_2 … #define MC_ARB_DRAM_TIMING2_3 … #define MC4_IO_DQ_PAD_CNTL_D0_I0 … #define MC4_IO_DQ_PAD_CNTL_D0_I1 … #define MC4_IO_QS_PAD_CNTL_D0_I0 … #define MC4_IO_QS_PAD_CNTL_D0_I1 … #endif
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