/* * Copyright 2010 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Alex Deucher */ #ifndef _BTCD_H_ #define _BTCD_H_ /* pm registers */ #define GENERAL_PWRMGT … #define GLOBAL_PWRMGT_EN … #define STATIC_PM_EN … #define THERMAL_PROTECTION_DIS … #define THERMAL_PROTECTION_TYPE … #define ENABLE_GEN2PCIE … #define ENABLE_GEN2XSP … #define SW_SMIO_INDEX(x) … #define SW_SMIO_INDEX_MASK … #define SW_SMIO_INDEX_SHIFT … #define LOW_VOLT_D2_ACPI … #define LOW_VOLT_D3_ACPI … #define VOLT_PWRMGT_EN … #define BACKBIAS_PAD_EN … #define BACKBIAS_VALUE … #define DYN_SPREAD_SPECTRUM_EN … #define AC_DC_SW … #define TARGET_AND_CURRENT_PROFILE_INDEX … #define CURRENT_PROFILE_INDEX_MASK … #define CURRENT_PROFILE_INDEX_SHIFT … #define CG_BIF_REQ_AND_RSP … #define CG_CLIENT_REQ(x) … #define CG_CLIENT_REQ_MASK … #define CG_CLIENT_REQ_SHIFT … #define CG_CLIENT_RESP(x) … #define CG_CLIENT_RESP_MASK … #define CG_CLIENT_RESP_SHIFT … #define CLIENT_CG_REQ(x) … #define CLIENT_CG_REQ_MASK … #define CLIENT_CG_REQ_SHIFT … #define CLIENT_CG_RESP(x) … #define CLIENT_CG_RESP_MASK … #define CLIENT_CG_RESP_SHIFT … #define SCLK_PSKIP_CNTL … #define PSKIP_ON_ALLOW_STOP_HI(x) … #define PSKIP_ON_ALLOW_STOP_HI_MASK … #define PSKIP_ON_ALLOW_STOP_HI_SHIFT … #define CG_ULV_CONTROL … #define CG_ULV_PARAMETER … #define MC_ARB_DRAM_TIMING … #define MC_ARB_DRAM_TIMING2 … #define MC_ARB_RFSH_RATE … #define POWERMODE0(x) … #define POWERMODE0_MASK … #define POWERMODE0_SHIFT … #define POWERMODE1(x) … #define POWERMODE1_MASK … #define POWERMODE1_SHIFT … #define POWERMODE2(x) … #define POWERMODE2_MASK … #define POWERMODE2_SHIFT … #define POWERMODE3(x) … #define POWERMODE3_MASK … #define POWERMODE3_SHIFT … #define MC_ARB_BURST_TIME … #define STATE0(x) … #define STATE0_MASK … #define STATE0_SHIFT … #define STATE1(x) … #define STATE1_MASK … #define STATE1_SHIFT … #define STATE2(x) … #define STATE2_MASK … #define STATE2_SHIFT … #define STATE3(x) … #define STATE3_MASK … #define STATE3_SHIFT … #define MC_SEQ_RAS_TIMING … #define MC_SEQ_CAS_TIMING … #define MC_SEQ_MISC_TIMING … #define MC_SEQ_MISC_TIMING2 … #define MC_SEQ_RD_CTL_D0 … #define MC_SEQ_RD_CTL_D1 … #define MC_SEQ_WR_CTL_D0 … #define MC_SEQ_WR_CTL_D1 … #define MC_PMG_AUTO_CFG … #define MC_SEQ_STATUS_M … #define PMG_PWRSTATE … #define MC_SEQ_MISC0 … #define MC_SEQ_MISC0_GDDR5_SHIFT … #define MC_SEQ_MISC0_GDDR5_MASK … #define MC_SEQ_MISC0_GDDR5_VALUE … #define MC_SEQ_MISC1 … #define MC_SEQ_RESERVE_M … #define MC_PMG_CMD_EMRS … #define MC_SEQ_MISC3 … #define MC_SEQ_MISC5 … #define MC_SEQ_MISC6 … #define MC_SEQ_MISC7 … #define MC_SEQ_CG … #define CG_SEQ_REQ(x) … #define CG_SEQ_REQ_MASK … #define CG_SEQ_REQ_SHIFT … #define CG_SEQ_RESP(x) … #define CG_SEQ_RESP_MASK … #define CG_SEQ_RESP_SHIFT … #define SEQ_CG_REQ(x) … #define SEQ_CG_REQ_MASK … #define SEQ_CG_REQ_SHIFT … #define SEQ_CG_RESP(x) … #define SEQ_CG_RESP_MASK … #define SEQ_CG_RESP_SHIFT … #define MC_SEQ_RAS_TIMING_LP … #define MC_SEQ_CAS_TIMING_LP … #define MC_SEQ_MISC_TIMING_LP … #define MC_SEQ_MISC_TIMING2_LP … #define MC_SEQ_WR_CTL_D0_LP … #define MC_SEQ_WR_CTL_D1_LP … #define MC_SEQ_PMG_CMD_EMRS_LP … #define MC_SEQ_PMG_CMD_MRS_LP … #define MC_PMG_CMD_MRS … #define MC_SEQ_RD_CTL_D0_LP … #define MC_SEQ_RD_CTL_D1_LP … #define MC_PMG_CMD_MRS1 … #define MC_SEQ_PMG_CMD_MRS1_LP … #define LB_SYNC_RESET_SEL … #define LB_SYNC_RESET_SEL_MASK … #define LB_SYNC_RESET_SEL_SHIFT … /* PCIE link stuff */ #define PCIE_LC_SPEED_CNTL … #define LC_GEN2_EN_STRAP … #define LC_TARGET_LINK_SPEED_OVERRIDE_EN … #define LC_FORCE_EN_HW_SPEED_CHANGE … #define LC_FORCE_DIS_HW_SPEED_CHANGE … #define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK … #define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT … #define LC_CURRENT_DATA_RATE … #define LC_HW_VOLTAGE_IF_CONTROL(x) … #define LC_HW_VOLTAGE_IF_CONTROL_MASK … #define LC_HW_VOLTAGE_IF_CONTROL_SHIFT … #define LC_VOLTAGE_TIMER_SEL_MASK … #define LC_CLR_FAILED_SPD_CHANGE_CNT … #define LC_OTHER_SIDE_EVER_SENT_GEN2 … #define LC_OTHER_SIDE_SUPPORTS_GEN2 … #endif
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