/* * Copyright 2012 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __SUMO_DPM_H__ #define __SUMO_DPM_H__ #include "atom.h" #include "radeon.h" #define SUMO_MAX_HARDWARE_POWERLEVELS … #define SUMO_PM_NUMBER_OF_TC … struct sumo_pl { … }; /* used for the flags field */ #define SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE … #define SUMO_POWERSTATE_FLAGS_BOOST_STATE … struct sumo_ps { … }; #define NUMBER_OF_M3ARB_PARAM_SETS … #define SUMO_MAX_NUMBER_VOLTAGES … struct sumo_disp_clock_voltage_mapping_table { … }; struct sumo_vid_mapping_entry { … }; struct sumo_vid_mapping_table { … }; struct sumo_sclk_voltage_mapping_entry { … }; struct sumo_sclk_voltage_mapping_table { … }; struct sumo_sys_info { … }; struct sumo_power_info { … }; #define SUMO_UTC_DFLT_00 … #define SUMO_UTC_DFLT_01 … #define SUMO_UTC_DFLT_02 … #define SUMO_UTC_DFLT_03 … #define SUMO_UTC_DFLT_04 … #define SUMO_UTC_DFLT_05 … #define SUMO_UTC_DFLT_06 … #define SUMO_UTC_DFLT_07 … #define SUMO_UTC_DFLT_08 … #define SUMO_UTC_DFLT_09 … #define SUMO_UTC_DFLT_10 … #define SUMO_UTC_DFLT_11 … #define SUMO_UTC_DFLT_12 … #define SUMO_UTC_DFLT_13 … #define SUMO_UTC_DFLT_14 … #define SUMO_DTC_DFLT_00 … #define SUMO_DTC_DFLT_01 … #define SUMO_DTC_DFLT_02 … #define SUMO_DTC_DFLT_03 … #define SUMO_DTC_DFLT_04 … #define SUMO_DTC_DFLT_05 … #define SUMO_DTC_DFLT_06 … #define SUMO_DTC_DFLT_07 … #define SUMO_DTC_DFLT_08 … #define SUMO_DTC_DFLT_09 … #define SUMO_DTC_DFLT_10 … #define SUMO_DTC_DFLT_11 … #define SUMO_DTC_DFLT_12 … #define SUMO_DTC_DFLT_13 … #define SUMO_DTC_DFLT_14 … #define SUMO_AH_DFLT … #define SUMO_R_DFLT0 … #define SUMO_R_DFLT1 … #define SUMO_R_DFLT2 … #define SUMO_R_DFLT3 … #define SUMO_R_DFLT4 … #define SUMO_L_DFLT0 … #define SUMO_L_DFLT1 … #define SUMO_L_DFLT2 … #define SUMO_L_DFLT3 … #define SUMO_L_DFLT4 … #define SUMO_VRC_DFLT … #define SUMO_MGCGTTLOCAL0_DFLT … #define SUMO_MGCGTTLOCAL1_DFLT … #define SUMO_GICST_DFLT … #define SUMO_SST_DFLT … #define SUMO_VOLTAGEDROPT_DFLT … #define SUMO_GFXPOWERGATINGT_DFLT … /* sumo_dpm.c */ void sumo_gfx_clockgating_initialize(struct radeon_device *rdev); void sumo_program_vc(struct radeon_device *rdev, u32 vrc); void sumo_clear_vc(struct radeon_device *rdev); void sumo_program_sstp(struct radeon_device *rdev); void sumo_take_smu_control(struct radeon_device *rdev, bool enable); void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev, struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table, ATOM_AVAILABLE_SCLK_LIST *table); void sumo_construct_vid_mapping_table(struct radeon_device *rdev, struct sumo_vid_mapping_table *vid_mapping_table, ATOM_AVAILABLE_SCLK_LIST *table); u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev, struct sumo_vid_mapping_table *vid_mapping_table, u32 vid_2bit); u32 sumo_get_sleep_divider_from_id(u32 id); u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev, u32 sclk, u32 min_sclk_in_sr); struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev); /* sumo_smc.c */ void sumo_initialize_m3_arb(struct radeon_device *rdev); void sumo_smu_pg_init(struct radeon_device *rdev); void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit); void sumo_smu_notify_alt_vddnb_change(struct radeon_device *rdev, bool powersaving, bool force_nbps1); void sumo_boost_state_enable(struct radeon_device *rdev, bool enable); void sumo_enable_boost_timer(struct radeon_device *rdev); u32 sumo_get_running_fw_version(struct radeon_device *rdev); #endif
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