/* * Copyright 2012 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Alex Deucher */ #ifndef _SUMOD_H_ #define _SUMOD_H_ /* pm registers */ /* rcu */ #define RCU_FW_VERSION … #define RCU_PWR_GATING_SEQ0 … #define RCU_PWR_GATING_SEQ1 … #define RCU_PWR_GATING_CNTL … #define PWR_GATING_EN … #define RSVD_MASK … #define PCV(x) … #define PCV_MASK … #define PCV_SHIFT … #define PCP(x) … #define PCP_MASK … #define PCP_SHIFT … #define RPW(x) … #define RPW_MASK … #define RPW_SHIFT … #define ID(x) … #define ID_MASK … #define ID_SHIFT … #define PGS(x) … #define PGS_MASK … #define PGS_SHIFT … #define RCU_ALTVDDNB_NOTIFY … #define RCU_LCLK_SCALING_CNTL … #define LCLK_SCALING_EN … #define LCLK_SCALING_TYPE … #define LCLK_SCALING_TIMER_PRESCALER(x) … #define LCLK_SCALING_TIMER_PRESCALER_MASK … #define LCLK_SCALING_TIMER_PRESCALER_SHIFT … #define LCLK_SCALING_TIMER_PERIOD(x) … #define LCLK_SCALING_TIMER_PERIOD_MASK … #define LCLK_SCALING_TIMER_PERIOD_SHIFT … #define RCU_PWR_GATING_CNTL_2 … #define MPPU(x) … #define MPPU_MASK … #define MPPU_SHIFT … #define MPPD(x) … #define MPPD_MASK … #define MPPD_SHIFT … #define RCU_PWR_GATING_CNTL_3 … #define DPPU(x) … #define DPPU_MASK … #define DPPU_SHIFT … #define DPPD(x) … #define DPPD_MASK … #define DPPD_SHIFT … #define RCU_PWR_GATING_CNTL_4 … #define RT(x) … #define RT_MASK … #define RT_SHIFT … #define IT(x) … #define IT_MASK … #define IT_SHIFT … /* yes these two have the same address */ #define RCU_PWR_GATING_CNTL_5 … #define RCU_GPU_BOOST_DISABLE … #define MCU_M3ARB_INDEX … #define MCU_M3ARB_PARAMS … #define RCU_GNB_PWR_REP_TIMER_CNTL … #define RCU_SclkDpmTdpLimit01 … #define RCU_SclkDpmTdpLimit23 … #define RCU_SclkDpmTdpLimit47 … #define RCU_SclkDpmTdpLimitPG … #define GNB_TDP_LIMIT … #define RCU_BOOST_MARGIN … #define RCU_THROTTLE_MARGIN … #define SMU_PCIE_PG_ARGS … #define SMU_PCIE_PG_ARGS_2 … #define SMU_PCIE_PG_ARGS_3 … /* mmio */ #define RCU_STATUS … #define GMC_PWR_GATER_BUSY … #define GFX_PWR_GATER_BUSY … #define UVD_PWR_GATER_BUSY … #define PCIE_PWR_GATER_BUSY … #define GMC_PWR_GATER_STATE … #define GFX_PWR_GATER_STATE … #define UVD_PWR_GATER_STATE … #define PCIE_PWR_GATER_STATE … #define GFX1_PWR_GATER_BUSY … #define GFX2_PWR_GATER_BUSY … #define GFX1_PWR_GATER_STATE … #define GFX2_PWR_GATER_STATE … #define GFX_INT_REQ … #define INT_REQ … #define SERV_INDEX(x) … #define SERV_INDEX_MASK … #define SERV_INDEX_SHIFT … #define GFX_INT_STATUS … #define INT_ACK … #define INT_DONE … #define CG_SCLK_CNTL … #define SCLK_DIVIDER(x) … #define SCLK_DIVIDER_MASK … #define SCLK_DIVIDER_SHIFT … #define CG_SCLK_STATUS … #define SCLK_OVERCLK_DETECT … #define CG_DCLK_CNTL … #define DCLK_DIVIDER_MASK … #define DCLK_DIR_CNTL_EN … #define CG_DCLK_STATUS … #define DCLK_STATUS … #define CG_VCLK_CNTL … #define VCLK_DIVIDER_MASK … #define VCLK_DIR_CNTL_EN … #define CG_VCLK_STATUS … #define GENERAL_PWRMGT … #define STATIC_PM_EN … #define SCLK_PWRMGT_CNTL … #define SCLK_PWRMGT_OFF … #define SCLK_LOW_D1 … #define FIR_RESET … #define FIR_FORCE_TREND_SEL … #define FIR_TREND_MODE … #define DYN_GFX_CLK_OFF_EN … #define GFX_CLK_FORCE_ON … #define GFX_CLK_REQUEST_OFF … #define GFX_CLK_FORCE_OFF … #define GFX_CLK_OFF_ACPI_D1 … #define GFX_CLK_OFF_ACPI_D2 … #define GFX_CLK_OFF_ACPI_D3 … #define GFX_VOLTAGE_CHANGE_EN … #define GFX_VOLTAGE_CHANGE_MODE … #define TARGET_AND_CURRENT_PROFILE_INDEX … #define TARG_SCLK_INDEX(x) … #define TARG_SCLK_INDEX_MASK … #define TARG_SCLK_INDEX_SHIFT … #define CURR_SCLK_INDEX(x) … #define CURR_SCLK_INDEX_MASK … #define CURR_SCLK_INDEX_SHIFT … #define TARG_INDEX(x) … #define TARG_INDEX_MASK … #define TARG_INDEX_SHIFT … #define CURR_INDEX(x) … #define CURR_INDEX_MASK … #define CURR_INDEX_SHIFT … #define CG_SCLK_DPM_CTRL … #define SCLK_FSTATE_0_DIV(x) … #define SCLK_FSTATE_0_DIV_MASK … #define SCLK_FSTATE_0_DIV_SHIFT … #define SCLK_FSTATE_0_VLD … #define SCLK_FSTATE_1_DIV(x) … #define SCLK_FSTATE_1_DIV_MASK … #define SCLK_FSTATE_1_DIV_SHIFT … #define SCLK_FSTATE_1_VLD … #define SCLK_FSTATE_2_DIV(x) … #define SCLK_FSTATE_2_DIV_MASK … #define SCLK_FSTATE_2_DIV_SHIFT … #define SCLK_FSTATE_2_VLD … #define SCLK_FSTATE_3_DIV(x) … #define SCLK_FSTATE_3_DIV_MASK … #define SCLK_FSTATE_3_DIV_SHIFT … #define SCLK_FSTATE_3_VLD … #define CG_SCLK_DPM_CTRL_2 … #define CG_GCOOR … #define PHC(x) … #define PHC_MASK … #define PHC_SHIFT … #define SDC(x) … #define SDC_MASK … #define SDC_SHIFT … #define SU(x) … #define SU_MASK … #define SU_SHIFT … #define DIV_ID(x) … #define DIV_ID_MASK … #define DIV_ID_SHIFT … #define CG_FTV … #define CG_FFCT_0 … #define UTC_0(x) … #define UTC_0_MASK … #define UTC_0_SHIFT … #define DTC_0(x) … #define DTC_0_MASK … #define DTC_0_SHIFT … #define CG_GIT … #define CG_GICST(x) … #define CG_GICST_MASK … #define CG_GICST_SHIFT … #define CG_GIPOT(x) … #define CG_GIPOT_MASK … #define CG_GIPOT_SHIFT … #define CG_SCLK_DPM_CTRL_3 … #define FORCE_SCLK_STATE(x) … #define FORCE_SCLK_STATE_MASK … #define FORCE_SCLK_STATE_SHIFT … #define FORCE_SCLK_STATE_EN … #define GNB_TT(x) … #define GNB_TT_MASK … #define GNB_TT_SHIFT … #define GNB_THERMTHRO_MASK … #define CNB_THERMTHRO_MASK_SCLK … #define DPM_SCLK_ENABLE … #define GNB_SLOW_FSTATE_0_MASK … #define GNB_SLOW_FSTATE_0_SHIFT … #define FORCE_NB_PSTATE_1 … #define CG_SSP … #define SST(x) … #define SST_MASK … #define SST_SHIFT … #define SSTU(x) … #define SSTU_MASK … #define SSTU_SHIFT … #define CG_ACPI_CNTL … #define SCLK_ACPI_DIV(x) … #define SCLK_ACPI_DIV_MASK … #define SCLK_ACPI_DIV_SHIFT … #define CG_SCLK_DPM_CTRL_4 … #define DC_HDC(x) … #define DC_HDC_MASK … #define DC_HDC_SHIFT … #define DC_HU(x) … #define DC_HU_MASK … #define DC_HU_SHIFT … #define CG_SCLK_DPM_CTRL_5 … #define SCLK_FSTATE_BOOTUP(x) … #define SCLK_FSTATE_BOOTUP_MASK … #define SCLK_FSTATE_BOOTUP_SHIFT … #define TT_TP(x) … #define TT_TP_MASK … #define TT_TP_SHIFT … #define TT_TU(x) … #define TT_TU_MASK … #define TT_TU_SHIFT … #define CG_SCLK_DPM_CTRL_6 … #define CG_AT_0 … #define CG_R(x) … #define CG_R_MASK … #define CG_R_SHIFT … #define CG_L(x) … #define CG_L_MASK … #define CG_L_SHIFT … #define CG_AT_1 … #define CG_AT_2 … #define CG_THERMAL_INT … #define DIG_THERM_INTH(x) … #define DIG_THERM_INTH_MASK … #define DIG_THERM_INTH_SHIFT … #define DIG_THERM_INTL(x) … #define DIG_THERM_INTL_MASK … #define DIG_THERM_INTL_SHIFT … #define THERM_INT_MASK_HIGH … #define THERM_INT_MASK_LOW … #define CG_AT_3 … #define CG_AT_4 … #define CG_AT_5 … #define CG_AT_6 … #define CG_AT_7 … #define CG_BSP_0 … #define BSP(x) … #define BSP_MASK … #define BSP_SHIFT … #define BSU(x) … #define BSU_MASK … #define BSU_SHIFT … #define CG_CG_VOLTAGE_CNTL … #define REQ … #define LEVEL(x) … #define LEVEL_MASK … #define LEVEL_SHIFT … #define CG_VOLTAGE_EN … #define FORCE … #define PERIOD(x) … #define PERIOD_MASK … #define PERIOD_SHIFT … #define UNIT(x) … #define UNIT_MASK … #define UNIT_SHIFT … #define CG_ACPI_VOLTAGE_CNTL … #define ACPI_VOLTAGE_EN … #define CG_DPM_VOLTAGE_CNTL … #define DPM_STATE0_LEVEL_MASK … #define DPM_STATE0_LEVEL_SHIFT … #define DPM_VOLTAGE_EN … #define CG_PWR_GATING_CNTL … #define DYN_PWR_DOWN_EN … #define ACPI_PWR_DOWN_EN … #define GFX_CLK_OFF_PWR_DOWN_EN … #define IOC_DISGPU_PWR_DOWN_EN … #define FORCE_POWR_ON … #define PGP(x) … #define PGP_MASK … #define PGP_SHIFT … #define PGU(x) … #define PGU_MASK … #define PGU_SHIFT … #define CG_CGTT_LOCAL_0 … #define CG_CGTT_LOCAL_1 … #define DEEP_SLEEP_CNTL … #define R_DIS … #define HS(x) … #define HS_MASK … #define HS_SHIFT … #define ENABLE_DS … #define DEEP_SLEEP_CNTL2 … #define LB_UFP_EN … #define INOUT_C(x) … #define INOUT_C_MASK … #define INOUT_C_SHIFT … #define CG_SCRATCH2 … #define CG_SCLK_DPM_CTRL_11 … #define HW_REV … #define ATI_REV_ID_MASK … #define ATI_REV_ID_SHIFT … /* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */ #define DOUT_SCRATCH3 … #define GB_ADDR_CONFIG … #endif
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