/* * Copyright 2012 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Alex Deucher */ #ifndef _TRINITYD_H_ #define _TRINITYD_H_ /* pm registers */ /* cg */ #define CG_CGTT_LOCAL_0 … #define CG_CGTT_LOCAL_1 … /* smc */ #define SMU_SCLK_DPM_STATE_0_CNTL_0 … #define STATE_VALID(x) … #define STATE_VALID_MASK … #define STATE_VALID_SHIFT … #define CLK_DIVIDER(x) … #define CLK_DIVIDER_MASK … #define CLK_DIVIDER_SHIFT … #define VID(x) … #define VID_MASK … #define VID_SHIFT … #define LVRT(x) … #define LVRT_MASK … #define LVRT_SHIFT … #define SMU_SCLK_DPM_STATE_0_CNTL_1 … #define DS_DIV(x) … #define DS_DIV_MASK … #define DS_DIV_SHIFT … #define DS_SH_DIV(x) … #define DS_SH_DIV_MASK … #define DS_SH_DIV_SHIFT … #define DISPLAY_WM(x) … #define DISPLAY_WM_MASK … #define DISPLAY_WM_SHIFT … #define VCE_WM(x) … #define VCE_WM_MASK … #define VCE_WM_SHIFT … #define SMU_SCLK_DPM_STATE_0_CNTL_3 … #define GNB_SLOW(x) … #define GNB_SLOW_MASK … #define GNB_SLOW_SHIFT … #define FORCE_NBPS1(x) … #define FORCE_NBPS1_MASK … #define FORCE_NBPS1_SHIFT … #define SMU_SCLK_DPM_STATE_0_AT … #define AT(x) … #define AT_MASK … #define AT_SHIFT … #define SMU_SCLK_DPM_STATE_0_PG_CNTL … #define PD_SCLK_DIVIDER(x) … #define PD_SCLK_DIVIDER_MASK … #define PD_SCLK_DIVIDER_SHIFT … #define SMU_SCLK_DPM_STATE_1_CNTL_0 … #define SMU_SCLK_DPM_CNTL … #define SCLK_DPM_EN(x) … #define SCLK_DPM_EN_MASK … #define SCLK_DPM_EN_SHIFT … #define SCLK_DPM_BOOT_STATE(x) … #define SCLK_DPM_BOOT_STATE_MASK … #define SCLK_DPM_BOOT_STATE_SHIFT … #define VOLTAGE_CHG_EN(x) … #define VOLTAGE_CHG_EN_MASK … #define VOLTAGE_CHG_EN_SHIFT … #define SMU_SCLK_DPM_TT_CNTL … #define SCLK_TT_EN(x) … #define SCLK_TT_EN_MASK … #define SCLK_TT_EN_SHIFT … #define SMU_SCLK_DPM_TTT … #define LT(x) … #define LT_MASK … #define LT_SHIFT … #define HT(x) … #define HT_MASK … #define HT_SHIFT … #define SMU_UVD_DPM_STATES … #define SMU_UVD_DPM_CNTL … #define SMU_S_PG_CNTL … #define DS_PG_EN(x) … #define DS_PG_EN_MASK … #define DS_PG_EN_SHIFT … #define GFX_POWER_GATING_CNTL … #define PDS_DIV(x) … #define PDS_DIV_MASK … #define PDS_DIV_SHIFT … #define SSSD(x) … #define SSSD_MASK … #define SSSD_SHIFT … #define PM_CONFIG … #define SVI_Mode … #define PM_I_CNTL_1 … #define SCLK_DPM(x) … #define SCLK_DPM_MASK … #define SCLK_DPM_SHIFT … #define DS_PG_CNTL(x) … #define DS_PG_CNTL_MASK … #define DS_PG_CNTL_SHIFT … #define PM_TP … #define NB_PSTATE_CONFIG … #define Dpm0PgNbPsLo(x) … #define Dpm0PgNbPsLo_MASK … #define Dpm0PgNbPsLo_SHIFT … #define Dpm0PgNbPsHi(x) … #define Dpm0PgNbPsHi_MASK … #define Dpm0PgNbPsHi_SHIFT … #define DpmXNbPsLo(x) … #define DpmXNbPsLo_MASK … #define DpmXNbPsLo_SHIFT … #define DpmXNbPsHi(x) … #define DpmXNbPsHi_MASK … #define DpmXNbPsHi_SHIFT … #define DC_CAC_VALUE … #define GPU_CAC_AVRG_CNTL … #define WINDOW_SIZE(x) … #define WINDOW_SIZE_MASK … #define WINDOW_SIZE_SHIFT … #define CC_SMU_MISC_FUSES … #define MinSClkDid(x) … #define MinSClkDid_MASK … #define MinSClkDid_SHIFT … #define CC_SMU_TST_EFUSE1_MISC … #define RB_BACKEND_DISABLE(x) … #define RB_BACKEND_DISABLE_MASK … #define RB_BACKEND_DISABLE_SHIFT … #define SMU_SCRATCH_A … #define SMU_SCRATCH0 … /* mmio */ #define SMC_INT_REQ … #define SMC_MESSAGE_0 … #define SMC_RESP_0 … #define GENERAL_PWRMGT … #define GLOBAL_PWRMGT_EN … #define SCLK_PWRMGT_CNTL … #define DYN_PWR_DOWN_EN … #define RESET_BUSY_CNT … #define RESET_SCLK_CNT … #define DYN_GFX_CLK_OFF_EN … #define GFX_CLK_FORCE_ON … #define DYNAMIC_PM_EN … #define TARGET_AND_CURRENT_PROFILE_INDEX … #define TARGET_STATE(x) … #define TARGET_STATE_MASK … #define TARGET_STATE_SHIFT … #define CURRENT_STATE(x) … #define CURRENT_STATE_MASK … #define CURRENT_STATE_SHIFT … #define CG_GIPOTS … #define CG_GIPOT(x) … #define CG_GIPOT_MASK … #define CG_GIPOT_SHIFT … #define CG_PG_CTRL … #define SP(x) … #define SP_MASK … #define SP_SHIFT … #define SU(x) … #define SU_MASK … #define SU_SHIFT … #define CG_MISC_REG … #define CG_THERMAL_INT_CTRL … #define DIG_THERM_INTH(x) … #define DIG_THERM_INTH_MASK … #define DIG_THERM_INTH_SHIFT … #define DIG_THERM_INTL(x) … #define DIG_THERM_INTL_MASK … #define DIG_THERM_INTL_SHIFT … #define THERM_INTH_MASK … #define THERM_INTL_MASK … #define CG_CG_VOLTAGE_CNTL … #define EN … #define HW_REV … #define ATI_REV_ID_MASK … #define ATI_REV_ID_SHIFT … /* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */ #define CGTS_SM_CTRL_REG … #define GB_ADDR_CONFIG … #endif
Codebase Browser
linux